Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Agere Systems Inc. |
| 3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs |
| 4 | * |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 5 | * Copyright * 2005 Agere Systems Inc. |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 6 | * All rights reserved. |
| 7 | * http://www.agere.com |
| 8 | * |
| 9 | *------------------------------------------------------------------------------ |
| 10 | * |
| 11 | * et1310_phy.c - Routines for configuring and accessing the PHY |
| 12 | * |
| 13 | *------------------------------------------------------------------------------ |
| 14 | * |
| 15 | * SOFTWARE LICENSE |
| 16 | * |
| 17 | * This software is provided subject to the following terms and conditions, |
| 18 | * which you should read carefully before using the software. Using this |
| 19 | * software indicates your acceptance of these terms and conditions. If you do |
| 20 | * not agree with these terms and conditions, do not use the software. |
| 21 | * |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 22 | * Copyright * 2005 Agere Systems Inc. |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 23 | * All rights reserved. |
| 24 | * |
| 25 | * Redistribution and use in source or binary forms, with or without |
| 26 | * modifications, are permitted provided that the following conditions are met: |
| 27 | * |
| 28 | * . Redistributions of source code must retain the above copyright notice, this |
| 29 | * list of conditions and the following Disclaimer as comments in the code as |
| 30 | * well as in the documentation and/or other materials provided with the |
| 31 | * distribution. |
| 32 | * |
| 33 | * . Redistributions in binary form must reproduce the above copyright notice, |
| 34 | * this list of conditions and the following Disclaimer in the documentation |
| 35 | * and/or other materials provided with the distribution. |
| 36 | * |
| 37 | * . Neither the name of Agere Systems Inc. nor the names of the contributors |
| 38 | * may be used to endorse or promote products derived from this software |
| 39 | * without specific prior written permission. |
| 40 | * |
| 41 | * Disclaimer |
| 42 | * |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 43 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 44 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF |
| 45 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY |
| 46 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN |
| 47 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY |
| 48 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 49 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 50 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 51 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT |
| 52 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT |
| 53 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH |
| 54 | * DAMAGE. |
| 55 | * |
| 56 | */ |
| 57 | |
| 58 | #include "et131x_version.h" |
| 59 | #include "et131x_debug.h" |
| 60 | #include "et131x_defs.h" |
| 61 | |
| 62 | #include <linux/pci.h> |
| 63 | #include <linux/init.h> |
| 64 | #include <linux/module.h> |
| 65 | #include <linux/types.h> |
| 66 | #include <linux/kernel.h> |
| 67 | |
| 68 | #include <linux/sched.h> |
| 69 | #include <linux/ptrace.h> |
| 70 | #include <linux/slab.h> |
| 71 | #include <linux/ctype.h> |
| 72 | #include <linux/string.h> |
| 73 | #include <linux/timer.h> |
| 74 | #include <linux/interrupt.h> |
| 75 | #include <linux/in.h> |
| 76 | #include <linux/delay.h> |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 77 | #include <linux/io.h> |
| 78 | #include <linux/bitops.h> |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 79 | #include <asm/system.h> |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 80 | |
| 81 | #include <linux/netdevice.h> |
| 82 | #include <linux/etherdevice.h> |
| 83 | #include <linux/skbuff.h> |
| 84 | #include <linux/if_arp.h> |
| 85 | #include <linux/ioport.h> |
| 86 | #include <linux/random.h> |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 87 | |
| 88 | #include "et1310_phy.h" |
| 89 | #include "et1310_pm.h" |
| 90 | #include "et1310_jagcore.h" |
| 91 | |
| 92 | #include "et131x_adapter.h" |
| 93 | #include "et131x_netdev.h" |
| 94 | #include "et131x_initpci.h" |
| 95 | |
| 96 | #include "et1310_address_map.h" |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 97 | #include "et1310_tx.h" |
| 98 | #include "et1310_rx.h" |
| 99 | #include "et1310_mac.h" |
| 100 | |
| 101 | /* Data for debugging facilities */ |
| 102 | #ifdef CONFIG_ET131X_DEBUG |
| 103 | extern dbg_info_t *et131x_dbginfo; |
| 104 | #endif /* CONFIG_ET131X_DEBUG */ |
| 105 | |
| 106 | /* Prototypes for functions with local scope */ |
| 107 | static int et131x_xcvr_init(struct et131x_adapter *adapter); |
| 108 | |
| 109 | /** |
| 110 | * PhyMiRead - Read from the PHY through the MII Interface on the MAC |
| 111 | * @adapter: pointer to our private adapter structure |
| 112 | * @xcvrAddr: the address of the transciever |
| 113 | * @xcvrReg: the register to read |
| 114 | * @value: pointer to a 16-bit value in which the value will be stored |
| 115 | * |
| 116 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 117 | */ |
| 118 | int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr, |
| 119 | uint8_t xcvrReg, uint16_t *value) |
| 120 | { |
Alan Cox | f3f415a | 2009-08-27 10:59:30 +0100 | [diff] [blame] | 121 | struct _MAC_t __iomem *mac = &adapter->regs->mac; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 122 | int status = 0; |
| 123 | uint32_t delay; |
| 124 | MII_MGMT_ADDR_t miiAddr; |
| 125 | MII_MGMT_CMD_t miiCmd; |
| 126 | MII_MGMT_INDICATOR_t miiIndicator; |
| 127 | |
| 128 | /* Save a local copy of the registers we are dealing with so we can |
| 129 | * set them back |
| 130 | */ |
| 131 | miiAddr.value = readl(&mac->mii_mgmt_addr.value); |
| 132 | miiCmd.value = readl(&mac->mii_mgmt_cmd.value); |
| 133 | |
| 134 | /* Stop the current operation */ |
| 135 | writel(0, &mac->mii_mgmt_cmd.value); |
| 136 | |
| 137 | /* Set up the register we need to read from on the correct PHY */ |
| 138 | { |
| 139 | MII_MGMT_ADDR_t mii_mgmt_addr = { 0 }; |
| 140 | |
| 141 | mii_mgmt_addr.bits.phy_addr = xcvrAddr; |
| 142 | mii_mgmt_addr.bits.reg_addr = xcvrReg; |
| 143 | writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value); |
| 144 | } |
| 145 | |
| 146 | /* Kick the read cycle off */ |
| 147 | delay = 0; |
| 148 | |
| 149 | writel(0x1, &mac->mii_mgmt_cmd.value); |
| 150 | |
| 151 | do { |
| 152 | udelay(50); |
| 153 | delay++; |
| 154 | miiIndicator.value = readl(&mac->mii_mgmt_indicator.value); |
| 155 | } while ((miiIndicator.bits.not_valid || miiIndicator.bits.busy) && |
| 156 | delay < 50); |
| 157 | |
| 158 | /* If we hit the max delay, we could not read the register */ |
| 159 | if (delay >= 50) { |
| 160 | DBG_WARNING(et131x_dbginfo, |
| 161 | "xcvrReg 0x%08x could not be read\n", xcvrReg); |
| 162 | DBG_WARNING(et131x_dbginfo, "status is 0x%08x\n", |
| 163 | miiIndicator.value); |
| 164 | |
| 165 | status = -EIO; |
| 166 | } |
| 167 | |
| 168 | /* If we hit here we were able to read the register and we need to |
| 169 | * return the value to the caller |
| 170 | */ |
| 171 | /* TODO: make this stuff a simple readw()?! */ |
| 172 | { |
| 173 | MII_MGMT_STAT_t mii_mgmt_stat; |
| 174 | |
| 175 | mii_mgmt_stat.value = readl(&mac->mii_mgmt_stat.value); |
| 176 | *value = (uint16_t) mii_mgmt_stat.bits.phy_stat; |
| 177 | } |
| 178 | |
| 179 | /* Stop the read operation */ |
| 180 | writel(0, &mac->mii_mgmt_cmd.value); |
| 181 | |
| 182 | DBG_VERBOSE(et131x_dbginfo, " xcvr_addr = 0x%02x, " |
| 183 | "xcvr_reg = 0x%02x, " |
| 184 | "value = 0x%04x.\n", xcvrAddr, xcvrReg, *value); |
| 185 | |
| 186 | /* set the registers we touched back to the state at which we entered |
| 187 | * this function |
| 188 | */ |
| 189 | writel(miiAddr.value, &mac->mii_mgmt_addr.value); |
| 190 | writel(miiCmd.value, &mac->mii_mgmt_cmd.value); |
| 191 | |
| 192 | return status; |
| 193 | } |
| 194 | |
| 195 | /** |
| 196 | * MiWrite - Write to a PHY register through the MII interface of the MAC |
| 197 | * @adapter: pointer to our private adapter structure |
| 198 | * @xcvrReg: the register to read |
| 199 | * @value: 16-bit value to write |
| 200 | * |
| 201 | * Return 0 on success, errno on failure (as defined in errno.h) |
| 202 | */ |
| 203 | int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value) |
| 204 | { |
Alan Cox | f3f415a | 2009-08-27 10:59:30 +0100 | [diff] [blame] | 205 | struct _MAC_t __iomem *mac = &adapter->regs->mac; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 206 | int status = 0; |
| 207 | uint8_t xcvrAddr = adapter->Stats.xcvr_addr; |
| 208 | uint32_t delay; |
| 209 | MII_MGMT_ADDR_t miiAddr; |
| 210 | MII_MGMT_CMD_t miiCmd; |
| 211 | MII_MGMT_INDICATOR_t miiIndicator; |
| 212 | |
| 213 | /* Save a local copy of the registers we are dealing with so we can |
| 214 | * set them back |
| 215 | */ |
| 216 | miiAddr.value = readl(&mac->mii_mgmt_addr.value); |
| 217 | miiCmd.value = readl(&mac->mii_mgmt_cmd.value); |
| 218 | |
| 219 | /* Stop the current operation */ |
| 220 | writel(0, &mac->mii_mgmt_cmd.value); |
| 221 | |
| 222 | /* Set up the register we need to write to on the correct PHY */ |
| 223 | { |
| 224 | MII_MGMT_ADDR_t mii_mgmt_addr; |
| 225 | |
| 226 | mii_mgmt_addr.bits.phy_addr = xcvrAddr; |
| 227 | mii_mgmt_addr.bits.reg_addr = xcvrReg; |
| 228 | writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value); |
| 229 | } |
| 230 | |
| 231 | /* Add the value to write to the registers to the mac */ |
| 232 | writel(value, &mac->mii_mgmt_ctrl.value); |
| 233 | delay = 0; |
| 234 | |
| 235 | do { |
| 236 | udelay(50); |
| 237 | delay++; |
| 238 | miiIndicator.value = readl(&mac->mii_mgmt_indicator.value); |
| 239 | } while (miiIndicator.bits.busy && delay < 100); |
| 240 | |
| 241 | /* If we hit the max delay, we could not write the register */ |
| 242 | if (delay == 100) { |
| 243 | uint16_t TempValue; |
| 244 | |
| 245 | DBG_WARNING(et131x_dbginfo, |
| 246 | "xcvrReg 0x%08x could not be written", xcvrReg); |
| 247 | DBG_WARNING(et131x_dbginfo, "status is 0x%08x\n", |
| 248 | miiIndicator.value); |
| 249 | DBG_WARNING(et131x_dbginfo, "command is 0x%08x\n", |
| 250 | readl(&mac->mii_mgmt_cmd.value)); |
| 251 | |
| 252 | MiRead(adapter, xcvrReg, &TempValue); |
| 253 | |
| 254 | status = -EIO; |
| 255 | } |
| 256 | |
| 257 | /* Stop the write operation */ |
| 258 | writel(0, &mac->mii_mgmt_cmd.value); |
| 259 | |
| 260 | /* set the registers we touched back to the state at which we entered |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 261 | * this function |
| 262 | */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 263 | writel(miiAddr.value, &mac->mii_mgmt_addr.value); |
| 264 | writel(miiCmd.value, &mac->mii_mgmt_cmd.value); |
| 265 | |
| 266 | DBG_VERBOSE(et131x_dbginfo, " xcvr_addr = 0x%02x, " |
| 267 | "xcvr_reg = 0x%02x, " |
| 268 | "value = 0x%04x.\n", xcvrAddr, xcvrReg, value); |
| 269 | |
| 270 | return status; |
| 271 | } |
| 272 | |
| 273 | /** |
| 274 | * et131x_xcvr_find - Find the PHY ID |
| 275 | * @adapter: pointer to our private adapter structure |
| 276 | * |
| 277 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 278 | */ |
| 279 | int et131x_xcvr_find(struct et131x_adapter *adapter) |
| 280 | { |
| 281 | int status = -ENODEV; |
| 282 | uint8_t xcvr_addr; |
| 283 | MI_IDR1_t idr1; |
| 284 | MI_IDR2_t idr2; |
| 285 | uint32_t xcvr_id; |
| 286 | |
| 287 | DBG_ENTER(et131x_dbginfo); |
| 288 | |
| 289 | /* We need to get xcvr id and address we just get the first one */ |
| 290 | for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) { |
| 291 | /* Read the ID from the PHY */ |
| 292 | PhyMiRead(adapter, xcvr_addr, |
| 293 | (uint8_t) offsetof(MI_REGS_t, idr1), |
| 294 | &idr1.value); |
| 295 | PhyMiRead(adapter, xcvr_addr, |
| 296 | (uint8_t) offsetof(MI_REGS_t, idr2), |
| 297 | &idr2.value); |
| 298 | |
| 299 | xcvr_id = (uint32_t) ((idr1.value << 16) | idr2.value); |
| 300 | |
| 301 | if ((idr1.value != 0) && (idr1.value != 0xffff)) { |
| 302 | DBG_TRACE(et131x_dbginfo, |
| 303 | "Xcvr addr: 0x%02x\tXcvr_id: 0x%08x\n", |
| 304 | xcvr_addr, xcvr_id); |
| 305 | |
| 306 | adapter->Stats.xcvr_id = xcvr_id; |
| 307 | adapter->Stats.xcvr_addr = xcvr_addr; |
| 308 | |
| 309 | status = 0; |
| 310 | break; |
| 311 | } |
| 312 | } |
| 313 | |
| 314 | DBG_LEAVE(et131x_dbginfo); |
| 315 | return status; |
| 316 | } |
| 317 | |
| 318 | /** |
| 319 | * et131x_setphy_normal - Set PHY for normal operation. |
| 320 | * @adapter: pointer to our private adapter structure |
| 321 | * |
| 322 | * Used by Power Management to force the PHY into 10 Base T half-duplex mode, |
| 323 | * when going to D3 in WOL mode. Also used during initialization to set the |
| 324 | * PHY for normal operation. |
| 325 | */ |
| 326 | int et131x_setphy_normal(struct et131x_adapter *adapter) |
| 327 | { |
| 328 | int status; |
| 329 | |
| 330 | DBG_ENTER(et131x_dbginfo); |
| 331 | |
| 332 | /* Make sure the PHY is powered up */ |
| 333 | ET1310_PhyPowerDown(adapter, 0); |
| 334 | status = et131x_xcvr_init(adapter); |
| 335 | |
| 336 | DBG_LEAVE(et131x_dbginfo); |
| 337 | return status; |
| 338 | } |
| 339 | |
| 340 | /** |
| 341 | * et131x_xcvr_init - Init the phy if we are setting it into force mode |
| 342 | * @adapter: pointer to our private adapter structure |
| 343 | * |
| 344 | * Returns 0 on success, errno on failure (as defined in errno.h) |
| 345 | */ |
| 346 | static int et131x_xcvr_init(struct et131x_adapter *adapter) |
| 347 | { |
| 348 | int status = 0; |
| 349 | MI_IMR_t imr; |
| 350 | MI_ISR_t isr; |
| 351 | MI_LCR2_t lcr2; |
| 352 | |
| 353 | DBG_ENTER(et131x_dbginfo); |
| 354 | |
| 355 | /* Zero out the adapter structure variable representing BMSR */ |
| 356 | adapter->Bmsr.value = 0; |
| 357 | |
| 358 | MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, isr), &isr.value); |
| 359 | |
| 360 | MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, imr), &imr.value); |
| 361 | |
| 362 | /* Set the link status interrupt only. Bad behavior when link status |
| 363 | * and auto neg are set, we run into a nested interrupt problem |
| 364 | */ |
| 365 | imr.bits.int_en = 0x1; |
| 366 | imr.bits.link_status = 0x1; |
| 367 | imr.bits.autoneg_status = 0x1; |
| 368 | |
| 369 | MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, imr), imr.value); |
| 370 | |
| 371 | /* Set the LED behavior such that LED 1 indicates speed (off = |
| 372 | * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates |
| 373 | * link and activity (on for link, blink off for activity). |
| 374 | * |
| 375 | * NOTE: Some customizations have been added here for specific |
| 376 | * vendors; The LED behavior is now determined by vendor data in the |
| 377 | * EEPROM. However, the above description is the default. |
| 378 | */ |
| 379 | if ((adapter->eepromData[1] & 0x4) == 0) { |
| 380 | MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2), |
| 381 | &lcr2.value); |
| 382 | if ((adapter->eepromData[1] & 0x8) == 0) |
| 383 | lcr2.bits.led_tx_rx = 0x3; |
| 384 | else |
| 385 | lcr2.bits.led_tx_rx = 0x4; |
| 386 | lcr2.bits.led_link = 0xa; |
| 387 | MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2), |
| 388 | lcr2.value); |
| 389 | } |
| 390 | |
| 391 | /* Determine if we need to go into a force mode and set it */ |
| 392 | if (adapter->AiForceSpeed == 0 && adapter->AiForceDpx == 0) { |
| 393 | if ((adapter->RegistryFlowControl == TxOnly) || |
| 394 | (adapter->RegistryFlowControl == Both)) { |
| 395 | ET1310_PhyAccessMiBit(adapter, |
| 396 | TRUEPHY_BIT_SET, 4, 11, NULL); |
| 397 | } else { |
| 398 | ET1310_PhyAccessMiBit(adapter, |
| 399 | TRUEPHY_BIT_CLEAR, 4, 11, NULL); |
| 400 | } |
| 401 | |
| 402 | if (adapter->RegistryFlowControl == Both) { |
| 403 | ET1310_PhyAccessMiBit(adapter, |
| 404 | TRUEPHY_BIT_SET, 4, 10, NULL); |
| 405 | } else { |
| 406 | ET1310_PhyAccessMiBit(adapter, |
| 407 | TRUEPHY_BIT_CLEAR, 4, 10, NULL); |
| 408 | } |
| 409 | |
| 410 | /* Set the phy to autonegotiation */ |
| 411 | ET1310_PhyAutoNeg(adapter, true); |
| 412 | |
| 413 | /* NOTE - Do we need this? */ |
| 414 | ET1310_PhyAccessMiBit(adapter, TRUEPHY_BIT_SET, 0, 9, NULL); |
| 415 | |
| 416 | DBG_LEAVE(et131x_dbginfo); |
| 417 | return status; |
| 418 | } else { |
| 419 | ET1310_PhyAutoNeg(adapter, false); |
| 420 | |
| 421 | /* Set to the correct force mode. */ |
| 422 | if (adapter->AiForceDpx != 1) { |
| 423 | if ((adapter->RegistryFlowControl == TxOnly) || |
| 424 | (adapter->RegistryFlowControl == Both)) { |
| 425 | ET1310_PhyAccessMiBit(adapter, |
| 426 | TRUEPHY_BIT_SET, 4, 11, |
| 427 | NULL); |
| 428 | } else { |
| 429 | ET1310_PhyAccessMiBit(adapter, |
| 430 | TRUEPHY_BIT_CLEAR, 4, 11, |
| 431 | NULL); |
| 432 | } |
| 433 | |
| 434 | if (adapter->RegistryFlowControl == Both) { |
| 435 | ET1310_PhyAccessMiBit(adapter, |
| 436 | TRUEPHY_BIT_SET, 4, 10, |
| 437 | NULL); |
| 438 | } else { |
| 439 | ET1310_PhyAccessMiBit(adapter, |
| 440 | TRUEPHY_BIT_CLEAR, 4, 10, |
| 441 | NULL); |
| 442 | } |
| 443 | } else { |
| 444 | ET1310_PhyAccessMiBit(adapter, |
| 445 | TRUEPHY_BIT_CLEAR, 4, 10, NULL); |
| 446 | ET1310_PhyAccessMiBit(adapter, |
| 447 | TRUEPHY_BIT_CLEAR, 4, 11, NULL); |
| 448 | } |
| 449 | |
| 450 | switch (adapter->AiForceSpeed) { |
| 451 | case 10: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 452 | if (adapter->AiForceDpx == 1) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 453 | TPAL_SetPhy10HalfDuplex(adapter); |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 454 | else if (adapter->AiForceDpx == 2) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 455 | TPAL_SetPhy10FullDuplex(adapter); |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 456 | else |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 457 | TPAL_SetPhy10Force(adapter); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 458 | break; |
| 459 | case 100: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 460 | if (adapter->AiForceDpx == 1) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 461 | TPAL_SetPhy100HalfDuplex(adapter); |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 462 | else if (adapter->AiForceDpx == 2) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 463 | TPAL_SetPhy100FullDuplex(adapter); |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 464 | else |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 465 | TPAL_SetPhy100Force(adapter); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 466 | break; |
| 467 | case 1000: |
| 468 | TPAL_SetPhy1000FullDuplex(adapter); |
| 469 | break; |
| 470 | } |
| 471 | |
| 472 | DBG_LEAVE(et131x_dbginfo); |
| 473 | return status; |
| 474 | } |
| 475 | } |
| 476 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 477 | void et131x_Mii_check(struct et131x_adapter *etdev, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 478 | MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints) |
| 479 | { |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 480 | uint8_t link_status; |
| 481 | uint32_t autoneg_status; |
| 482 | uint32_t speed; |
| 483 | uint32_t duplex; |
| 484 | uint32_t mdi_mdix; |
| 485 | uint32_t masterslave; |
| 486 | uint32_t polarity; |
Alan Cox | 3762860 | 2009-08-19 18:21:50 +0100 | [diff] [blame] | 487 | unsigned long flags; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 488 | |
| 489 | DBG_ENTER(et131x_dbginfo); |
| 490 | |
| 491 | if (bmsr_ints.bits.link_status) { |
| 492 | if (bmsr.bits.link_status) { |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 493 | etdev->PoMgmt.TransPhyComaModeOnBoot = 20; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 494 | |
| 495 | /* Update our state variables and indicate the |
| 496 | * connected state |
| 497 | */ |
Alan Cox | 3762860 | 2009-08-19 18:21:50 +0100 | [diff] [blame] | 498 | spin_lock_irqsave(&etdev->Lock, flags); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 499 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 500 | etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT; |
Alan Cox | f6b35d6 | 2009-08-27 11:02:05 +0100 | [diff] [blame^] | 501 | etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 502 | |
Alan Cox | 3762860 | 2009-08-19 18:21:50 +0100 | [diff] [blame] | 503 | spin_unlock_irqrestore(&etdev->Lock, flags); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 504 | |
| 505 | /* Don't indicate state if we're in loopback mode */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 506 | if (etdev->RegistryPhyLoopbk == false) |
| 507 | netif_carrier_on(etdev->netdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 508 | } else { |
| 509 | DBG_WARNING(et131x_dbginfo, |
| 510 | "Link down cable problem\n"); |
| 511 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 512 | if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 513 | /* NOTE - Is there a way to query this without |
| 514 | * TruePHY? |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 515 | * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 516 | */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 517 | uint16_t Register18; |
| 518 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 519 | MiRead(etdev, 0x12, &Register18); |
| 520 | MiWrite(etdev, 0x12, Register18 | 0x4); |
| 521 | MiWrite(etdev, 0x10, Register18 | 0x8402); |
| 522 | MiWrite(etdev, 0x11, Register18 | 511); |
| 523 | MiWrite(etdev, 0x12, Register18); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 524 | } |
| 525 | |
| 526 | /* For the first N seconds of life, we are in "link |
| 527 | * detection" When we are in this state, we should |
| 528 | * only report "connected". When the LinkDetection |
| 529 | * Timer expires, we can report disconnected (handled |
| 530 | * in the LinkDetectionDPC). |
| 531 | */ |
Alan Cox | f6b35d6 | 2009-08-27 11:02:05 +0100 | [diff] [blame^] | 532 | if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) || |
| 533 | (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) { |
Alan Cox | 3762860 | 2009-08-19 18:21:50 +0100 | [diff] [blame] | 534 | spin_lock_irqsave(&etdev->Lock, flags); |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 535 | etdev->MediaState = |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 536 | NETIF_STATUS_MEDIA_DISCONNECT; |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 537 | spin_unlock_irqrestore(&etdev->Lock, |
Alan Cox | 3762860 | 2009-08-19 18:21:50 +0100 | [diff] [blame] | 538 | flags); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 539 | |
| 540 | /* Only indicate state if we're in loopback |
| 541 | * mode |
| 542 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 543 | if (etdev->RegistryPhyLoopbk == false) |
| 544 | netif_carrier_off(etdev->netdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 545 | } |
| 546 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 547 | etdev->linkspeed = 0; |
Alan Cox | 576b38e | 2009-08-27 11:00:47 +0100 | [diff] [blame] | 548 | etdev->duplex_mode = 0; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 549 | |
| 550 | /* Free the packets being actively sent & stopped */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 551 | et131x_free_busy_send_packets(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 552 | |
| 553 | /* Re-initialize the send structures */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 554 | et131x_init_send(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 555 | |
| 556 | /* Reset the RFD list and re-start RU */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 557 | et131x_reset_recv(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 558 | |
| 559 | /* |
| 560 | * Bring the device back to the state it was during |
| 561 | * init prior to autonegotiation being complete. This |
| 562 | * way, when we get the auto-neg complete interrupt, |
| 563 | * we can complete init by calling ConfigMacREGS2. |
| 564 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 565 | et131x_soft_reset(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 566 | |
| 567 | /* Setup ET1310 as per the documentation */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 568 | et131x_adapter_setup(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 569 | |
| 570 | /* Setup the PHY into coma mode until the cable is |
| 571 | * plugged back in |
| 572 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 573 | if (etdev->RegistryPhyComa == 1) |
| 574 | EnablePhyComa(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 575 | } |
| 576 | } |
| 577 | |
| 578 | if (bmsr_ints.bits.auto_neg_complete || |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 579 | (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) { |
| 580 | if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) { |
| 581 | ET1310_PhyLinkStatus(etdev, |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 582 | &link_status, &autoneg_status, |
| 583 | &speed, &duplex, &mdi_mdix, |
| 584 | &masterslave, &polarity); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 585 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 586 | etdev->linkspeed = speed; |
| 587 | etdev->duplex_mode = duplex; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 588 | |
| 589 | DBG_TRACE(et131x_dbginfo, |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 590 | "etdev->linkspeed 0x%04x, etdev->duplex_mode 0x%08x\n", |
| 591 | etdev->linkspeed, |
| 592 | etdev->duplex_mode); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 593 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 594 | etdev->PoMgmt.TransPhyComaModeOnBoot = 20; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 595 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 596 | if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 597 | /* |
| 598 | * NOTE - Is there a way to query this without |
| 599 | * TruePHY? |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 600 | * && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 601 | */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 602 | uint16_t Register18; |
| 603 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 604 | MiRead(etdev, 0x12, &Register18); |
| 605 | MiWrite(etdev, 0x12, Register18 | 0x4); |
| 606 | MiWrite(etdev, 0x10, Register18 | 0x8402); |
| 607 | MiWrite(etdev, 0x11, Register18 | 511); |
| 608 | MiWrite(etdev, 0x12, Register18); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 609 | } |
| 610 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 611 | ConfigFlowControl(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 612 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 613 | if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS && |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 614 | etdev->RegistryJumboPacket > 2048) |
| 615 | ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff, |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 616 | 0x2000); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 617 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 618 | SetRxDmaTimer(etdev); |
| 619 | ConfigMACRegs2(etdev); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 620 | } |
| 621 | } |
| 622 | |
| 623 | DBG_LEAVE(et131x_dbginfo); |
| 624 | } |
| 625 | |
| 626 | /** |
| 627 | * TPAL_SetPhy10HalfDuplex - Force the phy into 10 Base T Half Duplex mode. |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 628 | * @etdev: pointer to the adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 629 | * |
| 630 | * Also sets the MAC so it is syncd up properly |
| 631 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 632 | void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 633 | { |
| 634 | DBG_ENTER(et131x_dbginfo); |
| 635 | |
| 636 | /* Power down PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 637 | ET1310_PhyPowerDown(etdev, 1); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 638 | |
| 639 | /* First we need to turn off all other advertisement */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 640 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 641 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 642 | ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 643 | |
| 644 | /* Set our advertise values accordingly */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 645 | ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_HALF); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 646 | |
| 647 | /* Power up PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 648 | ET1310_PhyPowerDown(etdev, 0); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 649 | |
| 650 | DBG_LEAVE(et131x_dbginfo); |
| 651 | } |
| 652 | |
| 653 | /** |
| 654 | * TPAL_SetPhy10FullDuplex - Force the phy into 10 Base T Full Duplex mode. |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 655 | * @etdev: pointer to the adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 656 | * |
| 657 | * Also sets the MAC so it is syncd up properly |
| 658 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 659 | void TPAL_SetPhy10FullDuplex(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 660 | { |
| 661 | DBG_ENTER(et131x_dbginfo); |
| 662 | |
| 663 | /* Power down PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 664 | ET1310_PhyPowerDown(etdev, 1); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 665 | |
| 666 | /* First we need to turn off all other advertisement */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 667 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 668 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 669 | ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 670 | |
| 671 | /* Set our advertise values accordingly */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 672 | ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 673 | |
| 674 | /* Power up PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 675 | ET1310_PhyPowerDown(etdev, 0); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 676 | |
| 677 | DBG_LEAVE(et131x_dbginfo); |
| 678 | } |
| 679 | |
| 680 | /** |
| 681 | * TPAL_SetPhy10Force - Force Base-T FD mode WITHOUT using autonegotiation |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 682 | * @etdev: pointer to the adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 683 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 684 | void TPAL_SetPhy10Force(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 685 | { |
| 686 | DBG_ENTER(et131x_dbginfo); |
| 687 | |
| 688 | /* Power down PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 689 | ET1310_PhyPowerDown(etdev, 1); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 690 | |
| 691 | /* Disable autoneg */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 692 | ET1310_PhyAutoNeg(etdev, false); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 693 | |
| 694 | /* Disable all advertisement */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 695 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
| 696 | ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
| 697 | ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 698 | |
| 699 | /* Force 10 Mbps */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 700 | ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 701 | |
| 702 | /* Force Full duplex */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 703 | ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 704 | |
| 705 | /* Power up PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 706 | ET1310_PhyPowerDown(etdev, 0); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 707 | |
| 708 | DBG_LEAVE(et131x_dbginfo); |
| 709 | } |
| 710 | |
| 711 | /** |
| 712 | * TPAL_SetPhy100HalfDuplex - Force 100 Base T Half Duplex mode. |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 713 | * @etdev: pointer to the adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 714 | * |
| 715 | * Also sets the MAC so it is syncd up properly. |
| 716 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 717 | void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 718 | { |
| 719 | DBG_ENTER(et131x_dbginfo); |
| 720 | |
| 721 | /* Power down PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 722 | ET1310_PhyPowerDown(etdev, 1); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 723 | |
| 724 | /* first we need to turn off all other advertisement */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 725 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 726 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 727 | ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 728 | |
| 729 | /* Set our advertise values accordingly */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 730 | ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_HALF); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 731 | |
| 732 | /* Set speed */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 733 | ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 734 | |
| 735 | /* Power up PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 736 | ET1310_PhyPowerDown(etdev, 0); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 737 | |
| 738 | DBG_LEAVE(et131x_dbginfo); |
| 739 | } |
| 740 | |
| 741 | /** |
| 742 | * TPAL_SetPhy100FullDuplex - Force 100 Base T Full Duplex mode. |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 743 | * @etdev: pointer to the adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 744 | * |
| 745 | * Also sets the MAC so it is syncd up properly |
| 746 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 747 | void TPAL_SetPhy100FullDuplex(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 748 | { |
| 749 | DBG_ENTER(et131x_dbginfo); |
| 750 | |
| 751 | /* Power down PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 752 | ET1310_PhyPowerDown(etdev, 1); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 753 | |
| 754 | /* First we need to turn off all other advertisement */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 755 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 756 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 757 | ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 758 | |
| 759 | /* Set our advertise values accordingly */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 760 | ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 761 | |
| 762 | /* Power up PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 763 | ET1310_PhyPowerDown(etdev, 0); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 764 | |
| 765 | DBG_LEAVE(et131x_dbginfo); |
| 766 | } |
| 767 | |
| 768 | /** |
| 769 | * TPAL_SetPhy100Force - Force 100 BaseT FD mode WITHOUT using autonegotiation |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 770 | * @etdev: pointer to the adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 771 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 772 | void TPAL_SetPhy100Force(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 773 | { |
| 774 | DBG_ENTER(et131x_dbginfo); |
| 775 | |
| 776 | /* Power down PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 777 | ET1310_PhyPowerDown(etdev, 1); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 778 | |
| 779 | /* Disable autoneg */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 780 | ET1310_PhyAutoNeg(etdev, false); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 781 | |
| 782 | /* Disable all advertisement */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 783 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
| 784 | ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
| 785 | ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 786 | |
| 787 | /* Force 100 Mbps */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 788 | ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 789 | |
| 790 | /* Force Full duplex */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 791 | ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 792 | |
| 793 | /* Power up PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 794 | ET1310_PhyPowerDown(etdev, 0); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 795 | |
| 796 | DBG_LEAVE(et131x_dbginfo); |
| 797 | } |
| 798 | |
| 799 | /** |
| 800 | * TPAL_SetPhy1000FullDuplex - Force 1000 Base T Full Duplex mode |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 801 | * @etdev: pointer to the adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 802 | * |
| 803 | * Also sets the MAC so it is syncd up properly. |
| 804 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 805 | void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 806 | { |
| 807 | DBG_ENTER(et131x_dbginfo); |
| 808 | |
| 809 | /* Power down PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 810 | ET1310_PhyPowerDown(etdev, 1); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 811 | |
| 812 | /* first we need to turn off all other advertisement */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 813 | ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 814 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 815 | ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 816 | |
| 817 | /* set our advertise values accordingly */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 818 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 819 | |
| 820 | /* power up PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 821 | ET1310_PhyPowerDown(etdev, 0); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 822 | |
| 823 | DBG_LEAVE(et131x_dbginfo); |
| 824 | } |
| 825 | |
| 826 | /** |
| 827 | * TPAL_SetPhyAutoNeg - Set phy to autonegotiation mode. |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 828 | * @etdev: pointer to the adapter structure |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 829 | */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 830 | void TPAL_SetPhyAutoNeg(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 831 | { |
| 832 | DBG_ENTER(et131x_dbginfo); |
| 833 | |
| 834 | /* Power down PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 835 | ET1310_PhyPowerDown(etdev, 1); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 836 | |
| 837 | /* Turn on advertisement of all capabilities */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 838 | ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_BOTH); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 839 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 840 | ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_BOTH); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 841 | |
Alan Cox | 5ec3487 | 2009-08-27 10:59:13 +0100 | [diff] [blame] | 842 | if (etdev->pdev->device != ET131X_PCI_DEVICE_ID_FAST) |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 843 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL); |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 844 | else |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 845 | ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 846 | |
| 847 | /* Make sure auto-neg is ON (it is disabled in FORCE modes) */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 848 | ET1310_PhyAutoNeg(etdev, true); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 849 | |
| 850 | /* Power up PHY */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 851 | ET1310_PhyPowerDown(etdev, 0); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 852 | |
| 853 | DBG_LEAVE(et131x_dbginfo); |
| 854 | } |
| 855 | |
| 856 | |
| 857 | /* |
| 858 | * The routines which follow provide low-level access to the PHY, and are used |
| 859 | * primarily by the routines above (although there are a few places elsewhere |
| 860 | * in the driver where this level of access is required). |
| 861 | */ |
| 862 | |
| 863 | static const uint16_t ConfigPhy[25][2] = { |
| 864 | /* Reg Value Register */ |
| 865 | /* Addr */ |
| 866 | {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */ |
| 867 | {0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */ |
| 868 | {0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */ |
| 869 | |
| 870 | {0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */ |
| 871 | {0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */ |
| 872 | {0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */ |
| 873 | |
| 874 | {0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */ |
| 875 | {0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */ |
| 876 | {0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */ |
| 877 | |
| 878 | {0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */ |
| 879 | {0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */ |
| 880 | {0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */ |
| 881 | |
| 882 | {0x300D, 1}, /* DisableNorm */ |
| 883 | |
| 884 | {0x280C, 0x0180}, /* LinkHoldEnd */ |
| 885 | |
| 886 | {0x1C21, 0x0002}, /* AlphaM */ |
| 887 | |
| 888 | {0x3821, 6}, /* FfeLkgTx0 */ |
| 889 | {0x381D, 1}, /* FfeLkg1g4 */ |
| 890 | {0x381E, 1}, /* FfeLkg1g5 */ |
| 891 | {0x381F, 1}, /* FfeLkg1g6 */ |
| 892 | {0x3820, 1}, /* FfeLkg1g7 */ |
| 893 | |
| 894 | {0x8402, 0x01F0}, /* Btinact */ |
| 895 | {0x800E, 20}, /* LftrainTime */ |
| 896 | {0x800F, 24}, /* DvguardTime */ |
| 897 | {0x8010, 46}, /* IdlguardTime */ |
| 898 | |
| 899 | {0, 0} |
| 900 | |
| 901 | }; |
| 902 | |
| 903 | /* condensed version of the phy initialization routine */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 904 | void ET1310_PhyInit(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 905 | { |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 906 | uint16_t data, index; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 907 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 908 | if (etdev == NULL) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 909 | return; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 910 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 911 | /* get the identity (again ?) */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 912 | MiRead(etdev, PHY_ID_1, &data); |
| 913 | MiRead(etdev, PHY_ID_2, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 914 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 915 | /* what does this do/achieve ? */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 916 | MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 917 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 918 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 919 | /* read modem register 0402, should I do something with the return |
| 920 | data ? */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 921 | MiWrite(etdev, PHY_INDEX_REG, 0x0402); |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 922 | MiRead(etdev, PHY_DATA_REG, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 923 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 924 | /* what does this do/achieve ? */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 925 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 926 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 927 | /* get the identity (again ?) */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 928 | MiRead(etdev, PHY_ID_1, &data); |
| 929 | MiRead(etdev, PHY_ID_2, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 930 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 931 | /* what does this achieve ? */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 932 | MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 933 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 934 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 935 | /* read modem register 0402, should I do something with |
| 936 | the return data? */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 937 | MiWrite(etdev, PHY_INDEX_REG, 0x0402); |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 938 | MiRead(etdev, PHY_DATA_REG, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 939 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 940 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 941 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 942 | /* what does this achieve (should return 0x1040) */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 943 | MiRead(etdev, PHY_CONTROL, &data); |
| 944 | MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 945 | MiWrite(etdev, PHY_CONTROL, 0x1840); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 946 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 947 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 948 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 949 | /* here the writing of the array starts.... */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 950 | index = 0; |
| 951 | while (ConfigPhy[index][0] != 0x0000) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 952 | /* write value */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 953 | MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]); |
| 954 | MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 955 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 956 | /* read it back */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 957 | MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]); |
| 958 | MiRead(etdev, PHY_DATA_REG, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 959 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 960 | /* do a check on the value read back ? */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 961 | index++; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 962 | } |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 963 | /* here the writing of the array ends... */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 964 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 965 | MiRead(etdev, PHY_CONTROL, &data); /* 0x1840 */ |
| 966 | MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 967 | MiWrite(etdev, PHY_CONTROL, 0x1040); |
| 968 | MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 969 | } |
| 970 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 971 | void ET1310_PhyReset(struct et131x_adapter *etdev) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 972 | { |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 973 | MiWrite(etdev, PHY_CONTROL, 0x8000); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 974 | } |
| 975 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 976 | void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 977 | { |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 978 | uint16_t data; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 979 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 980 | MiRead(etdev, PHY_CONTROL, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 981 | |
| 982 | if (down == false) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 983 | /* Power UP */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 984 | data &= ~0x0800; |
| 985 | MiWrite(etdev, PHY_CONTROL, data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 986 | } else { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 987 | /* Power DOWN */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 988 | data |= 0x0800; |
| 989 | MiWrite(etdev, PHY_CONTROL, data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 990 | } |
| 991 | } |
| 992 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 993 | void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 994 | { |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 995 | uint16_t data; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 996 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 997 | MiRead(etdev, PHY_CONTROL, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 998 | |
| 999 | if (enable == true) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1000 | /* Autonegotiation ON */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1001 | data |= 0x1000; |
| 1002 | MiWrite(etdev, PHY_CONTROL, data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1003 | } else { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1004 | /* Autonegotiation OFF */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1005 | data &= ~0x1000; |
| 1006 | MiWrite(etdev, PHY_CONTROL, data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1007 | } |
| 1008 | } |
| 1009 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1010 | void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, uint16_t duplex) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1011 | { |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1012 | uint16_t data; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1013 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1014 | MiRead(etdev, PHY_CONTROL, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1015 | |
| 1016 | if (duplex == TRUEPHY_DUPLEX_FULL) { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1017 | /* Set Full Duplex */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1018 | data |= 0x100; |
| 1019 | MiWrite(etdev, PHY_CONTROL, data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1020 | } else { |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1021 | /* Set Half Duplex */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1022 | data &= ~0x100; |
| 1023 | MiWrite(etdev, PHY_CONTROL, data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1024 | } |
| 1025 | } |
| 1026 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1027 | void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, uint16_t speed) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1028 | { |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1029 | uint16_t data; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1030 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1031 | /* Read the PHY control register */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1032 | MiRead(etdev, PHY_CONTROL, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1033 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1034 | /* Clear all Speed settings (Bits 6, 13) */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1035 | data &= ~0x2040; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1036 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1037 | /* Reset the speed bits based on user selection */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1038 | switch (speed) { |
| 1039 | case TRUEPHY_SPEED_10MBPS: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1040 | /* Bits already cleared above, do nothing */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1041 | break; |
| 1042 | |
| 1043 | case TRUEPHY_SPEED_100MBPS: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1044 | /* 100M == Set bit 13 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1045 | data |= 0x2000; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1046 | break; |
| 1047 | |
| 1048 | case TRUEPHY_SPEED_1000MBPS: |
| 1049 | default: |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1050 | data |= 0x0040; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1051 | break; |
| 1052 | } |
| 1053 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1054 | /* Write back the new speed */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1055 | MiWrite(etdev, PHY_CONTROL, data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1056 | } |
| 1057 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1058 | void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1059 | uint16_t duplex) |
| 1060 | { |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1061 | uint16_t data; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1062 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1063 | /* Read the PHY 1000 Base-T Control Register */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1064 | MiRead(etdev, PHY_1000_CONTROL, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1065 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1066 | /* Clear Bits 8,9 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1067 | data &= ~0x0300; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1068 | |
| 1069 | switch (duplex) { |
| 1070 | case TRUEPHY_ADV_DUPLEX_NONE: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1071 | /* Duplex already cleared, do nothing */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1072 | break; |
| 1073 | |
| 1074 | case TRUEPHY_ADV_DUPLEX_FULL: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1075 | /* Set Bit 9 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1076 | data |= 0x0200; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1077 | break; |
| 1078 | |
| 1079 | case TRUEPHY_ADV_DUPLEX_HALF: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1080 | /* Set Bit 8 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1081 | data |= 0x0100; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1082 | break; |
| 1083 | |
| 1084 | case TRUEPHY_ADV_DUPLEX_BOTH: |
| 1085 | default: |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1086 | data |= 0x0300; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1087 | break; |
| 1088 | } |
| 1089 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1090 | /* Write back advertisement */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1091 | MiWrite(etdev, PHY_1000_CONTROL, data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1092 | } |
| 1093 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1094 | void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1095 | uint16_t duplex) |
| 1096 | { |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1097 | uint16_t data; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1098 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1099 | /* Read the Autonegotiation Register (10/100) */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1100 | MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1101 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1102 | /* Clear bits 7,8 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1103 | data &= ~0x0180; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1104 | |
| 1105 | switch (duplex) { |
| 1106 | case TRUEPHY_ADV_DUPLEX_NONE: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1107 | /* Duplex already cleared, do nothing */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1108 | break; |
| 1109 | |
| 1110 | case TRUEPHY_ADV_DUPLEX_FULL: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1111 | /* Set Bit 8 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1112 | data |= 0x0100; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1113 | break; |
| 1114 | |
| 1115 | case TRUEPHY_ADV_DUPLEX_HALF: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1116 | /* Set Bit 7 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1117 | data |= 0x0080; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1118 | break; |
| 1119 | |
| 1120 | case TRUEPHY_ADV_DUPLEX_BOTH: |
| 1121 | default: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1122 | /* Set Bits 7,8 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1123 | data |= 0x0180; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1124 | break; |
| 1125 | } |
| 1126 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1127 | /* Write back advertisement */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1128 | MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1129 | } |
| 1130 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1131 | void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1132 | uint16_t duplex) |
| 1133 | { |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1134 | uint16_t data; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1135 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1136 | /* Read the Autonegotiation Register (10/100) */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1137 | MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1138 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1139 | /* Clear bits 5,6 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1140 | data &= ~0x0060; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1141 | |
| 1142 | switch (duplex) { |
| 1143 | case TRUEPHY_ADV_DUPLEX_NONE: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1144 | /* Duplex already cleared, do nothing */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1145 | break; |
| 1146 | |
| 1147 | case TRUEPHY_ADV_DUPLEX_FULL: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1148 | /* Set Bit 6 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1149 | data |= 0x0040; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1150 | break; |
| 1151 | |
| 1152 | case TRUEPHY_ADV_DUPLEX_HALF: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1153 | /* Set Bit 5 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1154 | data |= 0x0020; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1155 | break; |
| 1156 | |
| 1157 | case TRUEPHY_ADV_DUPLEX_BOTH: |
| 1158 | default: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1159 | /* Set Bits 5,6 */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1160 | data |= 0x0060; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1161 | break; |
| 1162 | } |
| 1163 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1164 | /* Write back advertisement */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1165 | MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1166 | } |
| 1167 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1168 | void ET1310_PhyLinkStatus(struct et131x_adapter *etdev, |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1169 | uint8_t *link_status, |
| 1170 | uint32_t *autoneg, |
| 1171 | uint32_t *linkspeed, |
| 1172 | uint32_t *duplex_mode, |
| 1173 | uint32_t *mdi_mdix, |
| 1174 | uint32_t *masterslave, uint32_t *polarity) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1175 | { |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1176 | uint16_t mistatus = 0; |
| 1177 | uint16_t is1000BaseT = 0; |
| 1178 | uint16_t vmi_phystatus = 0; |
| 1179 | uint16_t control = 0; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1180 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1181 | MiRead(etdev, PHY_STATUS, &mistatus); |
| 1182 | MiRead(etdev, PHY_1000_STATUS, &is1000BaseT); |
| 1183 | MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus); |
| 1184 | MiRead(etdev, PHY_CONTROL, &control); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1185 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1186 | if (link_status) { |
| 1187 | *link_status = |
| 1188 | (unsigned char)((vmi_phystatus & 0x0040) ? 1 : 0); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1189 | } |
| 1190 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1191 | if (autoneg) { |
| 1192 | *autoneg = |
| 1193 | (control & 0x1000) ? ((vmi_phystatus & 0x0020) ? |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1194 | TRUEPHY_ANEG_COMPLETE : |
| 1195 | TRUEPHY_ANEG_NOT_COMPLETE) : |
| 1196 | TRUEPHY_ANEG_DISABLED; |
| 1197 | } |
| 1198 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1199 | if (linkspeed) |
| 1200 | *linkspeed = (vmi_phystatus & 0x0300) >> 8; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1201 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1202 | if (duplex_mode) |
| 1203 | *duplex_mode = (vmi_phystatus & 0x0080) >> 7; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1204 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1205 | if (mdi_mdix) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1206 | /* NOTE: Need to complete this */ |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1207 | *mdi_mdix = 0; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1208 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1209 | if (masterslave) { |
| 1210 | *masterslave = |
| 1211 | (is1000BaseT & 0x4000) ? TRUEPHY_CFG_MASTER : |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1212 | TRUEPHY_CFG_SLAVE; |
| 1213 | } |
| 1214 | |
Alan Cox | 9fa8109 | 2009-08-27 11:00:36 +0100 | [diff] [blame] | 1215 | if (polarity) { |
| 1216 | *polarity = |
| 1217 | (vmi_phystatus & 0x0400) ? TRUEPHY_POLARITY_INVERTED : |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1218 | TRUEPHY_POLARITY_NORMAL; |
| 1219 | } |
| 1220 | } |
| 1221 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1222 | void ET1310_PhyAndOrReg(struct et131x_adapter *etdev, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1223 | uint16_t regnum, uint16_t andMask, uint16_t orMask) |
| 1224 | { |
| 1225 | uint16_t reg; |
| 1226 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1227 | /* Read the requested register */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1228 | MiRead(etdev, regnum, ®); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1229 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1230 | /* Apply the AND mask */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1231 | reg &= andMask; |
| 1232 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1233 | /* Apply the OR mask */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1234 | reg |= orMask; |
| 1235 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1236 | /* Write the value back to the register */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1237 | MiWrite(etdev, regnum, reg); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1238 | } |
| 1239 | |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1240 | void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, uint16_t action, |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1241 | uint16_t regnum, uint16_t bitnum, uint8_t *value) |
| 1242 | { |
| 1243 | uint16_t reg; |
| 1244 | uint16_t mask = 0; |
| 1245 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1246 | /* Create a mask to isolate the requested bit */ |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1247 | mask = 0x0001 << bitnum; |
| 1248 | |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1249 | /* Read the requested register */ |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1250 | MiRead(etdev, regnum, ®); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1251 | |
| 1252 | switch (action) { |
| 1253 | case TRUEPHY_BIT_READ: |
Alan Cox | 64f9303 | 2009-06-10 17:30:41 +0100 | [diff] [blame] | 1254 | if (value != NULL) |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1255 | *value = (reg & mask) >> bitnum; |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1256 | break; |
| 1257 | |
| 1258 | case TRUEPHY_BIT_SET: |
| 1259 | reg |= mask; |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1260 | MiWrite(etdev, regnum, reg); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1261 | break; |
| 1262 | |
| 1263 | case TRUEPHY_BIT_CLEAR: |
| 1264 | reg &= ~mask; |
Alan Cox | 25ad00b | 2009-08-19 18:21:44 +0100 | [diff] [blame] | 1265 | MiWrite(etdev, regnum, reg); |
Greg Kroah-Hartman | cfb739b | 2008-04-03 17:30:53 -0700 | [diff] [blame] | 1266 | break; |
| 1267 | |
| 1268 | default: |
| 1269 | break; |
| 1270 | } |
| 1271 | } |