blob: ea4febaa4bb1caf50f2ef92cc6c711e94c4285e2 [file] [log] [blame]
David Daney5b3b1682009-01-08 16:46:40 -08001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
7 * Copyright (C) 2000, 2001 Ralf Baechle <ralf@gnu.org>
8 * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
9 * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
10 * IP32 changes by Ilya.
David Daneyb93b2ab2010-10-01 13:27:34 -070011 * Copyright (C) 2010 Cavium Networks, Inc.
David Daney5b3b1682009-01-08 16:46:40 -080012 */
David Daneye8635b42009-04-23 17:44:38 -070013#include <linux/dma-mapping.h>
David Daneye8635b42009-04-23 17:44:38 -070014#include <linux/scatterlist.h>
David Daneyb93b2ab2010-10-01 13:27:34 -070015#include <linux/bootmem.h>
Paul Gortmakercae39d12011-07-28 18:46:31 -040016#include <linux/export.h>
David Daneyb93b2ab2010-10-01 13:27:34 -070017#include <linux/swiotlb.h>
18#include <linux/types.h>
19#include <linux/init.h>
20#include <linux/mm.h>
David Daneye8635b42009-04-23 17:44:38 -070021
David Daneyb93b2ab2010-10-01 13:27:34 -070022#include <asm/bootinfo.h>
David Daneye8635b42009-04-23 17:44:38 -070023
24#include <asm/octeon/octeon.h>
David Daney5b3b1682009-01-08 16:46:40 -080025
David Daneye8635b42009-04-23 17:44:38 -070026#ifdef CONFIG_PCI
David Daney01a62212009-06-29 17:18:51 -070027#include <asm/octeon/pci-octeon.h>
David Daneyb93b2ab2010-10-01 13:27:34 -070028#include <asm/octeon/cvmx-npi-defs.h>
29#include <asm/octeon/cvmx-pci-defs.h>
David Daneye8635b42009-04-23 17:44:38 -070030
David Daneyb93b2ab2010-10-01 13:27:34 -070031static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
David Daney5b3b1682009-01-08 16:46:40 -080032{
David Daneyb93b2ab2010-10-01 13:27:34 -070033 if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
34 return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
David Daneye8635b42009-04-23 17:44:38 -070035 else
David Daneyb93b2ab2010-10-01 13:27:34 -070036 return paddr;
David Daney5b3b1682009-01-08 16:46:40 -080037}
38
David Daneyb93b2ab2010-10-01 13:27:34 -070039static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
David Daney5b3b1682009-01-08 16:46:40 -080040{
David Daneyb93b2ab2010-10-01 13:27:34 -070041 if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
42 return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
43 else
44 return daddr;
45}
David Daneye8635b42009-04-23 17:44:38 -070046
David Daneyb93b2ab2010-10-01 13:27:34 -070047static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
48{
49 if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
50 paddr -= 0x400000000ull;
51 return octeon_hole_phys_to_dma(paddr);
52}
53
54static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
55{
56 daddr = octeon_hole_dma_to_phys(daddr);
57
58 if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
59 daddr += 0x400000000ull;
60
61 return daddr;
62}
63
64static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
65{
66 if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
67 paddr -= 0x400000000ull;
68
69 /* Anything in the BAR1 hole or above goes via BAR2 */
70 if (paddr >= 0xf0000000ull)
71 paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
72
73 return paddr;
74}
75
76static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
77{
78 if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
79 daddr -= OCTEON_BAR2_PCI_ADDRESS;
80
81 if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
82 daddr += 0x400000000ull;
83 return daddr;
84}
85
86static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
87 phys_addr_t paddr)
88{
89 if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
90 paddr -= 0x400000000ull;
91
92 /* Anything not in the BAR1 range goes via BAR2 */
93 if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
94 paddr = paddr - octeon_bar1_pci_phys;
95 else
96 paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
97
98 return paddr;
99}
100
101static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
102 dma_addr_t daddr)
103{
104 if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
105 daddr -= OCTEON_BAR2_PCI_ADDRESS;
106 else
107 daddr += octeon_bar1_pci_phys;
108
109 if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
110 daddr += 0x400000000ull;
111 return daddr;
112}
113
114#endif /* CONFIG_PCI */
115
116static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page,
117 unsigned long offset, size_t size, enum dma_data_direction direction,
118 struct dma_attrs *attrs)
119{
120 dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size,
121 direction, attrs);
122 mb();
123
124 return daddr;
125}
126
127static int octeon_dma_map_sg(struct device *dev, struct scatterlist *sg,
128 int nents, enum dma_data_direction direction, struct dma_attrs *attrs)
129{
130 int r = swiotlb_map_sg_attrs(dev, sg, nents, direction, attrs);
131 mb();
132 return r;
133}
134
135static void octeon_dma_sync_single_for_device(struct device *dev,
136 dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
137{
138 swiotlb_sync_single_for_device(dev, dma_handle, size, direction);
139 mb();
140}
141
142static void octeon_dma_sync_sg_for_device(struct device *dev,
143 struct scatterlist *sg, int nelems, enum dma_data_direction direction)
144{
145 swiotlb_sync_sg_for_device(dev, sg, nelems, direction);
146 mb();
147}
148
149static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
150 dma_addr_t *dma_handle, gfp_t gfp)
151{
152 void *ret;
153
154 if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
155 return ret;
156
157 /* ignore region specifiers */
158 gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
159
160#ifdef CONFIG_ZONE_DMA
161 if (dev == NULL)
162 gfp |= __GFP_DMA;
163 else if (dev->coherent_dma_mask <= DMA_BIT_MASK(24))
164 gfp |= __GFP_DMA;
165 else
166#endif
167#ifdef CONFIG_ZONE_DMA32
168 if (dev->coherent_dma_mask <= DMA_BIT_MASK(32))
169 gfp |= __GFP_DMA32;
170 else
171#endif
172 ;
173
174 /* Don't invoke OOM killer */
175 gfp |= __GFP_NORETRY;
176
177 ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
178
179 mb();
180
181 return ret;
182}
183
184static void octeon_dma_free_coherent(struct device *dev, size_t size,
185 void *vaddr, dma_addr_t dma_handle)
186{
187 int order = get_order(size);
188
189 if (dma_release_from_coherent(dev, order, vaddr))
David Daneye8635b42009-04-23 17:44:38 -0700190 return;
191
David Daneyb93b2ab2010-10-01 13:27:34 -0700192 swiotlb_free_coherent(dev, size, vaddr, dma_handle);
193}
David Daneye8635b42009-04-23 17:44:38 -0700194
David Daneyb93b2ab2010-10-01 13:27:34 -0700195static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr)
196{
197 return paddr;
198}
David Daneye8635b42009-04-23 17:44:38 -0700199
David Daneyb93b2ab2010-10-01 13:27:34 -0700200static phys_addr_t octeon_unity_dma_to_phys(struct device *dev, dma_addr_t daddr)
201{
202 return daddr;
203}
David Daneye8635b42009-04-23 17:44:38 -0700204
David Daneyb93b2ab2010-10-01 13:27:34 -0700205struct octeon_dma_map_ops {
206 struct dma_map_ops dma_map_ops;
207 dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
208 phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
209};
210
211dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
212{
213 struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
214 struct octeon_dma_map_ops,
215 dma_map_ops);
216
217 return ops->phys_to_dma(dev, paddr);
218}
219EXPORT_SYMBOL(phys_to_dma);
220
221phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
222{
223 struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
224 struct octeon_dma_map_ops,
225 dma_map_ops);
226
227 return ops->dma_to_phys(dev, daddr);
228}
229EXPORT_SYMBOL(dma_to_phys);
230
231static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
232 .dma_map_ops = {
233 .alloc_coherent = octeon_dma_alloc_coherent,
234 .free_coherent = octeon_dma_free_coherent,
235 .map_page = octeon_dma_map_page,
236 .unmap_page = swiotlb_unmap_page,
237 .map_sg = octeon_dma_map_sg,
238 .unmap_sg = swiotlb_unmap_sg_attrs,
239 .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
240 .sync_single_for_device = octeon_dma_sync_single_for_device,
241 .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
242 .sync_sg_for_device = octeon_dma_sync_sg_for_device,
243 .mapping_error = swiotlb_dma_mapping_error,
244 .dma_supported = swiotlb_dma_supported
245 },
246 .phys_to_dma = octeon_unity_phys_to_dma,
247 .dma_to_phys = octeon_unity_dma_to_phys
248};
249
250char *octeon_swiotlb;
251
252void __init plat_swiotlb_setup(void)
253{
254 int i;
255 phys_t max_addr;
256 phys_t addr_size;
257 size_t swiotlbsize;
258 unsigned long swiotlb_nslabs;
259
260 max_addr = 0;
261 addr_size = 0;
262
263 for (i = 0 ; i < boot_mem_map.nr_map; i++) {
264 struct boot_mem_map_entry *e = &boot_mem_map.map[i];
265 if (e->type != BOOT_MEM_RAM)
266 continue;
267
268 /* These addresses map low for PCI. */
269 if (e->addr > 0x410000000ull)
270 continue;
271
272 addr_size += e->size;
273
274 if (max_addr < e->addr + e->size)
275 max_addr = e->addr + e->size;
276
David Daneye8635b42009-04-23 17:44:38 -0700277 }
278
David Daneyb93b2ab2010-10-01 13:27:34 -0700279 swiotlbsize = PAGE_SIZE;
David Daneye8635b42009-04-23 17:44:38 -0700280
David Daneyb93b2ab2010-10-01 13:27:34 -0700281#ifdef CONFIG_PCI
282 /*
283 * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
284 * size to a maximum of 64MB
285 */
286 if (OCTEON_IS_MODEL(OCTEON_CN31XX)
287 || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
288 swiotlbsize = addr_size / 4;
289 if (swiotlbsize > 64 * (1<<20))
290 swiotlbsize = 64 * (1<<20);
291 } else if (max_addr > 0xf0000000ul) {
292 /*
293 * Otherwise only allocate a big iotlb if there is
294 * memory past the BAR1 hole.
295 */
296 swiotlbsize = 64 * (1<<20);
297 }
David Daneye8635b42009-04-23 17:44:38 -0700298#endif
David Daneyb93b2ab2010-10-01 13:27:34 -0700299 swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
300 swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
301 swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
302
303 octeon_swiotlb = alloc_bootmem_low_pages(swiotlbsize);
304
305 swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1);
306
307 mips_dma_map_ops = &octeon_linear_dma_map_ops.dma_map_ops;
David Daney5b3b1682009-01-08 16:46:40 -0800308}
David Daneyb93b2ab2010-10-01 13:27:34 -0700309
310#ifdef CONFIG_PCI
311static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = {
312 .dma_map_ops = {
313 .alloc_coherent = octeon_dma_alloc_coherent,
314 .free_coherent = octeon_dma_free_coherent,
315 .map_page = octeon_dma_map_page,
316 .unmap_page = swiotlb_unmap_page,
317 .map_sg = octeon_dma_map_sg,
318 .unmap_sg = swiotlb_unmap_sg_attrs,
319 .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
320 .sync_single_for_device = octeon_dma_sync_single_for_device,
321 .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
322 .sync_sg_for_device = octeon_dma_sync_sg_for_device,
323 .mapping_error = swiotlb_dma_mapping_error,
324 .dma_supported = swiotlb_dma_supported
325 },
326};
327
328struct dma_map_ops *octeon_pci_dma_map_ops;
329
330void __init octeon_pci_dma_init(void)
331{
332 switch (octeon_dma_bar_type) {
333 case OCTEON_DMA_BAR_TYPE_PCIE:
334 _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
335 _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
336 break;
337 case OCTEON_DMA_BAR_TYPE_BIG:
338 _octeon_pci_dma_map_ops.phys_to_dma = octeon_big_phys_to_dma;
339 _octeon_pci_dma_map_ops.dma_to_phys = octeon_big_dma_to_phys;
340 break;
341 case OCTEON_DMA_BAR_TYPE_SMALL:
342 _octeon_pci_dma_map_ops.phys_to_dma = octeon_small_phys_to_dma;
343 _octeon_pci_dma_map_ops.dma_to_phys = octeon_small_dma_to_phys;
344 break;
345 default:
346 BUG();
347 }
348 octeon_pci_dma_map_ops = &_octeon_pci_dma_map_ops.dma_map_ops;
349}
350#endif /* CONFIG_PCI */