Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/sh/drivers/dma/dma-g2.c |
| 3 | * |
| 4 | * G2 bus DMA support |
| 5 | * |
| 6 | * Copyright (C) 2003, 2004 Paul Mundt |
| 7 | * |
| 8 | * This file is subject to the terms and conditions of the GNU General Public |
| 9 | * License. See the file "COPYING" in the main directory of this archive |
| 10 | * for more details. |
| 11 | */ |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/interrupt.h> |
| 16 | |
| 17 | #include <asm/mach/sysasic.h> |
| 18 | #include <asm/mach/dma.h> |
| 19 | #include <asm/dma.h> |
| 20 | |
| 21 | struct g2_channel { |
| 22 | unsigned long g2_addr; /* G2 bus address */ |
| 23 | unsigned long root_addr; /* Root bus (SH-4) address */ |
| 24 | unsigned long size; /* Size (in bytes), 32-byte aligned */ |
| 25 | unsigned long direction; /* Transfer direction */ |
| 26 | unsigned long ctrl; /* Transfer control */ |
| 27 | unsigned long chan_enable; /* Channel enable */ |
| 28 | unsigned long xfer_enable; /* Transfer enable */ |
| 29 | unsigned long xfer_stat; /* Transfer status */ |
| 30 | } __attribute__ ((aligned(32))); |
| 31 | |
| 32 | struct g2_status { |
| 33 | unsigned long g2_addr; |
| 34 | unsigned long root_addr; |
| 35 | unsigned long size; |
| 36 | unsigned long status; |
| 37 | } __attribute__ ((aligned(16))); |
| 38 | |
| 39 | struct g2_dma_info { |
| 40 | struct g2_channel channel[G2_NR_DMA_CHANNELS]; |
| 41 | unsigned long pad1[G2_NR_DMA_CHANNELS]; |
| 42 | unsigned long wait_state; |
| 43 | unsigned long pad2[10]; |
| 44 | unsigned long magic; |
| 45 | struct g2_status status[G2_NR_DMA_CHANNELS]; |
| 46 | } __attribute__ ((aligned(256))); |
| 47 | |
| 48 | static volatile struct g2_dma_info *g2_dma = (volatile struct g2_dma_info *)0xa05f7800; |
| 49 | |
| 50 | static irqreturn_t g2_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
| 51 | { |
| 52 | /* FIXME: Do some meaningful completion work here.. */ |
| 53 | return IRQ_HANDLED; |
| 54 | } |
| 55 | |
| 56 | static struct irqaction g2_dma_irq = { |
| 57 | .name = "g2 DMA handler", |
| 58 | .handler = g2_dma_interrupt, |
| 59 | .flags = SA_INTERRUPT, |
| 60 | }; |
| 61 | |
| 62 | static int g2_enable_dma(struct dma_channel *chan) |
| 63 | { |
| 64 | unsigned int chan_nr = chan->chan; |
| 65 | |
| 66 | g2_dma->channel[chan_nr].chan_enable = 1; |
| 67 | g2_dma->channel[chan_nr].xfer_enable = 1; |
| 68 | |
| 69 | return 0; |
| 70 | } |
| 71 | |
| 72 | static int g2_disable_dma(struct dma_channel *chan) |
| 73 | { |
| 74 | unsigned int chan_nr = chan->chan; |
| 75 | |
| 76 | g2_dma->channel[chan_nr].chan_enable = 0; |
| 77 | g2_dma->channel[chan_nr].xfer_enable = 0; |
| 78 | |
| 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | static int g2_xfer_dma(struct dma_channel *chan) |
| 83 | { |
| 84 | unsigned int chan_nr = chan->chan; |
| 85 | |
| 86 | if (chan->sar & 31) { |
| 87 | printk("g2dma: unaligned source 0x%lx\n", chan->sar); |
| 88 | return -EINVAL; |
| 89 | } |
| 90 | |
| 91 | if (chan->dar & 31) { |
| 92 | printk("g2dma: unaligned dest 0x%lx\n", chan->dar); |
| 93 | return -EINVAL; |
| 94 | } |
| 95 | |
| 96 | /* Align the count */ |
| 97 | if (chan->count & 31) |
| 98 | chan->count = (chan->count + (32 - 1)) & ~(32 - 1); |
| 99 | |
| 100 | /* Fixup destination */ |
| 101 | chan->dar += 0xa0800000; |
| 102 | |
| 103 | /* Fixup direction */ |
| 104 | chan->mode = !chan->mode; |
| 105 | |
| 106 | flush_icache_range((unsigned long)chan->sar, chan->count); |
| 107 | |
| 108 | g2_disable_dma(chan); |
| 109 | |
| 110 | g2_dma->channel[chan_nr].g2_addr = chan->dar & 0x1fffffe0; |
| 111 | g2_dma->channel[chan_nr].root_addr = chan->sar & 0x1fffffe0; |
| 112 | g2_dma->channel[chan_nr].size = (chan->count & ~31) | 0x80000000; |
| 113 | g2_dma->channel[chan_nr].direction = chan->mode; |
| 114 | |
| 115 | /* |
| 116 | * bit 0 - ??? |
| 117 | * bit 1 - if set, generate a hardware event on transfer completion |
| 118 | * bit 2 - ??? something to do with suspend? |
| 119 | */ |
| 120 | g2_dma->channel[chan_nr].ctrl = 5; /* ?? */ |
| 121 | |
| 122 | g2_enable_dma(chan); |
| 123 | |
| 124 | /* debug cruft */ |
| 125 | pr_debug("count, sar, dar, mode, ctrl, chan, xfer: %ld, 0x%08lx, " |
| 126 | "0x%08lx, %ld, %ld, %ld, %ld\n", |
| 127 | g2_dma->channel[chan_nr].size, |
| 128 | g2_dma->channel[chan_nr].root_addr, |
| 129 | g2_dma->channel[chan_nr].g2_addr, |
| 130 | g2_dma->channel[chan_nr].direction, |
| 131 | g2_dma->channel[chan_nr].ctrl, |
| 132 | g2_dma->channel[chan_nr].chan_enable, |
| 133 | g2_dma->channel[chan_nr].xfer_enable); |
| 134 | |
| 135 | return 0; |
| 136 | } |
| 137 | |
| 138 | static struct dma_ops g2_dma_ops = { |
| 139 | .xfer = g2_xfer_dma, |
| 140 | }; |
| 141 | |
| 142 | static struct dma_info g2_dma_info = { |
| 143 | .name = "G2 DMA", |
| 144 | .nr_channels = 4, |
| 145 | .ops = &g2_dma_ops, |
| 146 | .flags = DMAC_CHANNELS_TEI_CAPABLE, |
| 147 | }; |
| 148 | |
| 149 | static int __init g2_dma_init(void) |
| 150 | { |
| 151 | setup_irq(HW_EVENT_G2_DMA, &g2_dma_irq); |
| 152 | |
| 153 | /* Magic */ |
| 154 | g2_dma->wait_state = 27; |
| 155 | g2_dma->magic = 0x4659404f; |
| 156 | |
| 157 | return register_dmac(&g2_dma_info); |
| 158 | } |
| 159 | |
| 160 | static void __exit g2_dma_exit(void) |
| 161 | { |
| 162 | free_irq(HW_EVENT_G2_DMA, 0); |
| 163 | } |
| 164 | |
| 165 | subsys_initcall(g2_dma_init); |
| 166 | module_exit(g2_dma_exit); |
| 167 | |
| 168 | MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>"); |
| 169 | MODULE_DESCRIPTION("G2 bus DMA driver"); |
| 170 | MODULE_LICENSE("GPL"); |
| 171 | |