blob: 9a5f9fb352ce1c7ca97baa3e4269ef54770e2faa [file] [log] [blame]
Linus Walleijbb3cee22009-04-23 10:22:13 +01001/*
2 *
3 * arch/arm/mach-u300/timer.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Timer COH 901 328, runs the OS timer interrupt.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/timex.h>
14#include <linux/clockchips.h>
15#include <linux/clocksource.h>
16#include <linux/types.h>
17#include <linux/io.h>
Linus Walleijb7276b22010-08-05 07:58:58 +010018#include <linux/clk.h>
19#include <linux/err.h>
Linus Walleija4fe2922012-08-13 13:49:45 +020020#include <linux/irq.h>
Linus Walleij3c96d8e2013-04-05 22:45:11 +020021#include <linux/delay.h>
Linus Walleij5a5056c2013-04-08 10:50:11 +020022#include <linux/of_address.h>
23#include <linux/of_irq.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070024#include <linux/sched_clock.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +010025
Linus Walleijbb3cee22009-04-23 10:22:13 +010026/* Generic stuff */
27#include <asm/mach/map.h>
28#include <asm/mach/time.h>
Linus Walleijbb3cee22009-04-23 10:22:13 +010029
Linus Walleijbb3cee22009-04-23 10:22:13 +010030/*
31 * APP side special timer registers
32 * This timer contains four timers which can fire an interrupt each.
33 * OS (operating system) timer @ 32768 Hz
34 * DD (device driver) timer @ 1 kHz
35 * GP1 (general purpose 1) timer @ 1MHz
36 * GP2 (general purpose 2) timer @ 1MHz
37 */
38
39/* Reset OS Timer 32bit (-/W) */
40#define U300_TIMER_APP_ROST (0x0000)
41#define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000)
42/* Enable OS Timer 32bit (-/W) */
43#define U300_TIMER_APP_EOST (0x0004)
44#define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000)
45/* Disable OS Timer 32bit (-/W) */
46#define U300_TIMER_APP_DOST (0x0008)
47#define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000)
48/* OS Timer Mode Register 32bit (-/W) */
49#define U300_TIMER_APP_SOSTM (0x000c)
50#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000)
51#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001)
52/* OS Timer Status Register 32bit (R/-) */
53#define U300_TIMER_APP_OSTS (0x0010)
54#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F)
55#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001)
56#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002)
57#define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010)
58#define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020)
59#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000)
60#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020)
61#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040)
62#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080)
63/* OS Timer Current Count Register 32bit (R/-) */
64#define U300_TIMER_APP_OSTCC (0x0014)
65/* OS Timer Terminal Count Register 32bit (R/W) */
66#define U300_TIMER_APP_OSTTC (0x0018)
67/* OS Timer Interrupt Enable Register 32bit (-/W) */
68#define U300_TIMER_APP_OSTIE (0x001c)
69#define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000)
70#define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001)
71/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
72#define U300_TIMER_APP_OSTIA (0x0020)
73#define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080)
74
75/* Reset DD Timer 32bit (-/W) */
76#define U300_TIMER_APP_RDDT (0x0040)
77#define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000)
78/* Enable DD Timer 32bit (-/W) */
79#define U300_TIMER_APP_EDDT (0x0044)
80#define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000)
81/* Disable DD Timer 32bit (-/W) */
82#define U300_TIMER_APP_DDDT (0x0048)
83#define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000)
84/* DD Timer Mode Register 32bit (-/W) */
85#define U300_TIMER_APP_SDDTM (0x004c)
86#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000)
87#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001)
88/* DD Timer Status Register 32bit (R/-) */
89#define U300_TIMER_APP_DDTS (0x0050)
90#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F)
91#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001)
92#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002)
93#define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010)
94#define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020)
95#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000)
96#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020)
97#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040)
98#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080)
99/* DD Timer Current Count Register 32bit (R/-) */
100#define U300_TIMER_APP_DDTCC (0x0054)
101/* DD Timer Terminal Count Register 32bit (R/W) */
102#define U300_TIMER_APP_DDTTC (0x0058)
103/* DD Timer Interrupt Enable Register 32bit (-/W) */
104#define U300_TIMER_APP_DDTIE (0x005c)
105#define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000)
106#define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001)
107/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
108#define U300_TIMER_APP_DDTIA (0x0060)
109#define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080)
110
111/* Reset GP1 Timer 32bit (-/W) */
112#define U300_TIMER_APP_RGPT1 (0x0080)
113#define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000)
114/* Enable GP1 Timer 32bit (-/W) */
115#define U300_TIMER_APP_EGPT1 (0x0084)
116#define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000)
117/* Disable GP1 Timer 32bit (-/W) */
118#define U300_TIMER_APP_DGPT1 (0x0088)
119#define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000)
120/* GP1 Timer Mode Register 32bit (-/W) */
121#define U300_TIMER_APP_SGPT1M (0x008c)
122#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000)
123#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001)
124/* GP1 Timer Status Register 32bit (R/-) */
125#define U300_TIMER_APP_GPT1S (0x0090)
126#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F)
127#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001)
128#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002)
129#define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010)
130#define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020)
131#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000)
132#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020)
133#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040)
134#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080)
135/* GP1 Timer Current Count Register 32bit (R/-) */
136#define U300_TIMER_APP_GPT1CC (0x0094)
137/* GP1 Timer Terminal Count Register 32bit (R/W) */
138#define U300_TIMER_APP_GPT1TC (0x0098)
139/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
140#define U300_TIMER_APP_GPT1IE (0x009c)
141#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000)
142#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001)
143/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
144#define U300_TIMER_APP_GPT1IA (0x00a0)
145#define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080)
146
147/* Reset GP2 Timer 32bit (-/W) */
148#define U300_TIMER_APP_RGPT2 (0x00c0)
149#define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000)
150/* Enable GP2 Timer 32bit (-/W) */
151#define U300_TIMER_APP_EGPT2 (0x00c4)
152#define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000)
153/* Disable GP2 Timer 32bit (-/W) */
154#define U300_TIMER_APP_DGPT2 (0x00c8)
155#define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000)
156/* GP2 Timer Mode Register 32bit (-/W) */
157#define U300_TIMER_APP_SGPT2M (0x00cc)
158#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000)
159#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001)
160/* GP2 Timer Status Register 32bit (R/-) */
161#define U300_TIMER_APP_GPT2S (0x00d0)
162#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F)
163#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001)
164#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002)
165#define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010)
166#define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020)
167#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000)
168#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020)
169#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040)
170#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080)
171/* GP2 Timer Current Count Register 32bit (R/-) */
172#define U300_TIMER_APP_GPT2CC (0x00d4)
173/* GP2 Timer Terminal Count Register 32bit (R/W) */
174#define U300_TIMER_APP_GPT2TC (0x00d8)
175/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
176#define U300_TIMER_APP_GPT2IE (0x00dc)
177#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000)
178#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001)
179/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
180#define U300_TIMER_APP_GPT2IA (0x00e0)
181#define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080)
182
183/* Clock request control register - all four timers */
184#define U300_TIMER_APP_CRC (0x100)
185#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001)
186
187#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
188#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
189
Linus Walleij5a5056c2013-04-08 10:50:11 +0200190static void __iomem *u300_timer_base;
191
Linus Walleijbb3cee22009-04-23 10:22:13 +0100192/*
193 * The u300_set_mode() function is always called first, if we
194 * have oneshot timer active, the oneshot scheduling function
195 * u300_set_next_event() is called immediately after.
196 */
197static void u300_set_mode(enum clock_event_mode mode,
198 struct clock_event_device *evt)
199{
200 switch (mode) {
201 case CLOCK_EVT_MODE_PERIODIC:
202 /* Disable interrupts on GPT1 */
203 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200204 u300_timer_base + U300_TIMER_APP_GPT1IE);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100205 /* Disable GP1 while we're reprogramming it. */
206 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200207 u300_timer_base + U300_TIMER_APP_DGPT1);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100208 /*
209 * Set the periodic mode to a certain number of ticks per
210 * jiffy.
211 */
212 writel(TICKS_PER_JIFFY,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200213 u300_timer_base + U300_TIMER_APP_GPT1TC);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100214 /*
215 * Set continuous mode, so the timer keeps triggering
216 * interrupts.
217 */
218 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200219 u300_timer_base + U300_TIMER_APP_SGPT1M);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100220 /* Enable timer interrupts */
221 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200222 u300_timer_base + U300_TIMER_APP_GPT1IE);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100223 /* Then enable the OS timer again */
224 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200225 u300_timer_base + U300_TIMER_APP_EGPT1);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100226 break;
227 case CLOCK_EVT_MODE_ONESHOT:
228 /* Just break; here? */
229 /*
230 * The actual event will be programmed by the next event hook,
231 * so we just set a dummy value somewhere at the end of the
232 * universe here.
233 */
234 /* Disable interrupts on GPT1 */
235 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200236 u300_timer_base + U300_TIMER_APP_GPT1IE);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100237 /* Disable GP1 while we're reprogramming it. */
238 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200239 u300_timer_base + U300_TIMER_APP_DGPT1);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100240 /*
241 * Expire far in the future, u300_set_next_event() will be
242 * called soon...
243 */
Linus Walleij5a5056c2013-04-08 10:50:11 +0200244 writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100245 /* We run one shot per tick here! */
246 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200247 u300_timer_base + U300_TIMER_APP_SGPT1M);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100248 /* Enable interrupts for this timer */
249 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200250 u300_timer_base + U300_TIMER_APP_GPT1IE);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100251 /* Enable timer */
252 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200253 u300_timer_base + U300_TIMER_APP_EGPT1);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100254 break;
255 case CLOCK_EVT_MODE_UNUSED:
256 case CLOCK_EVT_MODE_SHUTDOWN:
257 /* Disable interrupts on GP1 */
258 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200259 u300_timer_base + U300_TIMER_APP_GPT1IE);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100260 /* Disable GP1 */
261 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200262 u300_timer_base + U300_TIMER_APP_DGPT1);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100263 break;
264 case CLOCK_EVT_MODE_RESUME:
265 /* Ignore this call */
266 break;
267 }
268}
269
270/*
271 * The app timer in one shot mode obviously has to be reprogrammed
272 * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
273 * the interrupt disable + timer disable commands with a reset command,
274 * it will fail miserably. Apparently (and I found this the hard way)
275 * the timer is very sensitive to the instruction order, though you don't
276 * get that impression from the data sheet.
277 */
278static int u300_set_next_event(unsigned long cycles,
279 struct clock_event_device *evt)
280
281{
282 /* Disable interrupts on GPT1 */
283 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200284 u300_timer_base + U300_TIMER_APP_GPT1IE);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100285 /* Disable GP1 while we're reprogramming it. */
286 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200287 u300_timer_base + U300_TIMER_APP_DGPT1);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100288 /* Reset the General Purpose timer 1. */
289 writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200290 u300_timer_base + U300_TIMER_APP_RGPT1);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100291 /* IRQ in n * cycles */
Linus Walleij5a5056c2013-04-08 10:50:11 +0200292 writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100293 /*
294 * We run one shot per tick here! (This is necessary to reconfigure,
295 * the timer will tilt if you don't!)
296 */
297 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200298 u300_timer_base + U300_TIMER_APP_SGPT1M);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100299 /* Enable timer interrupts */
300 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200301 u300_timer_base + U300_TIMER_APP_GPT1IE);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100302 /* Then enable the OS timer again */
303 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200304 u300_timer_base + U300_TIMER_APP_EGPT1);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100305 return 0;
306}
307
308
309/* Use general purpose timer 1 as clock event */
310static struct clock_event_device clockevent_u300_1mhz = {
Linus Walleijcde21de2011-05-30 15:51:47 +0200311 .name = "GPT1",
312 .rating = 300, /* Reasonably fast and accurate clock event */
313 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
314 .set_next_event = u300_set_next_event,
315 .set_mode = u300_set_mode,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100316};
317
318/* Clock event timer interrupt handler */
319static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
320{
321 struct clock_event_device *evt = &clockevent_u300_1mhz;
322 /* ACK/Clear timer IRQ for the APP GPT1 Timer */
Linus Walleij5a5056c2013-04-08 10:50:11 +0200323
Linus Walleijbb3cee22009-04-23 10:22:13 +0100324 writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200325 u300_timer_base + U300_TIMER_APP_GPT1IA);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100326 evt->event_handler(evt);
327 return IRQ_HANDLED;
328}
329
330static struct irqaction u300_timer_irq = {
Linus Walleijcde21de2011-05-30 15:51:47 +0200331 .name = "U300 Timer Tick",
332 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
333 .handler = u300_timer_interrupt,
Linus Walleijbb3cee22009-04-23 10:22:13 +0100334};
335
Linus Walleija2ca00e2009-09-17 13:10:50 +0100336/*
337 * Override the global weak sched_clock symbol with this
338 * local implementation which uses the clocksource to get some
339 * better resolution when scheduling the kernel. We accept that
340 * this wraps around for now, since it is just a relative time
341 * stamp. (Inspired by OMAP implementation.)
342 */
Russell King5c21b7c2010-12-15 21:50:14 +0000343
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100344static u32 notrace u300_read_sched_clock(void)
Linus Walleija2ca00e2009-09-17 13:10:50 +0100345{
Linus Walleij5a5056c2013-04-08 10:50:11 +0200346 return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
Linus Walleija2ca00e2009-09-17 13:10:50 +0100347}
348
Linus Walleij3c96d8e2013-04-05 22:45:11 +0200349static unsigned long u300_read_current_timer(void)
350{
Linus Walleij5a5056c2013-04-08 10:50:11 +0200351 return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
Linus Walleij3c96d8e2013-04-05 22:45:11 +0200352}
353
354static struct delay_timer u300_delay_timer;
Linus Walleijbb3cee22009-04-23 10:22:13 +0100355
356/*
357 * This sets up the system timers, clock source and clock event.
358 */
Linus Walleij75a7f3f2013-04-22 11:29:30 +0200359static void __init u300_timer_init_of(struct device_node *np)
Linus Walleijbb3cee22009-04-23 10:22:13 +0100360{
Thierry Redingf7578492013-09-18 15:24:44 +0200361 unsigned int irq;
Linus Walleijb7276b22010-08-05 07:58:58 +0100362 struct clk *clk;
Linus Walleij3af8a8d2010-08-05 07:59:54 +0100363 unsigned long rate;
Linus Walleijb7276b22010-08-05 07:58:58 +0100364
Linus Walleij75a7f3f2013-04-22 11:29:30 +0200365 u300_timer_base = of_iomap(np, 0);
366 if (!u300_timer_base)
367 panic("could not ioremap system timer\n");
368
369 /* Get the IRQ for the GP1 timer */
Thierry Redingf7578492013-09-18 15:24:44 +0200370 irq = irq_of_parse_and_map(np, 2);
371 if (!irq)
Linus Walleij75a7f3f2013-04-22 11:29:30 +0200372 panic("no IRQ for system timer\n");
373
Thierry Redingf7578492013-09-18 15:24:44 +0200374 pr_info("U300 GP1 timer @ base: %p, IRQ: %u\n", u300_timer_base, irq);
Linus Walleij5a5056c2013-04-08 10:50:11 +0200375
Linus Walleijb7276b22010-08-05 07:58:58 +0100376 /* Clock the interrupt controller */
Linus Walleijbba5f2c2013-05-23 15:42:33 +0200377 clk = of_clk_get(np, 0);
Linus Walleijb7276b22010-08-05 07:58:58 +0100378 BUG_ON(IS_ERR(clk));
Linus Walleij50667d62012-06-19 23:44:25 +0200379 clk_prepare_enable(clk);
Linus Walleij3af8a8d2010-08-05 07:59:54 +0100380 rate = clk_get_rate(clk);
Linus Walleijb7276b22010-08-05 07:58:58 +0100381
Marc Zyngier2f0778af2011-12-15 12:19:23 +0100382 setup_sched_clock(u300_read_sched_clock, 32, rate);
Russell King5c21b7c2010-12-15 21:50:14 +0000383
Linus Walleij3c96d8e2013-04-05 22:45:11 +0200384 u300_delay_timer.read_current_timer = &u300_read_current_timer;
385 u300_delay_timer.freq = rate;
386 register_current_timer_delay(&u300_delay_timer);
387
Linus Walleijbb3cee22009-04-23 10:22:13 +0100388 /*
389 * Disable the "OS" and "DD" timers - these are designed for Symbian!
390 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
391 */
392 writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200393 u300_timer_base + U300_TIMER_APP_CRC);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100394 writel(U300_TIMER_APP_ROST_TIMER_RESET,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200395 u300_timer_base + U300_TIMER_APP_ROST);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100396 writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200397 u300_timer_base + U300_TIMER_APP_DOST);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100398 writel(U300_TIMER_APP_RDDT_TIMER_RESET,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200399 u300_timer_base + U300_TIMER_APP_RDDT);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100400 writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200401 u300_timer_base + U300_TIMER_APP_DDDT);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100402
403 /* Reset the General Purpose timer 1. */
404 writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200405 u300_timer_base + U300_TIMER_APP_RGPT1);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100406
407 /* Set up the IRQ handler */
Linus Walleij5a5056c2013-04-08 10:50:11 +0200408 setup_irq(irq, &u300_timer_irq);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100409
410 /* Reset the General Purpose timer 2 */
411 writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200412 u300_timer_base + U300_TIMER_APP_RGPT2);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100413 /* Set this timer to run around forever */
Linus Walleij5a5056c2013-04-08 10:50:11 +0200414 writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100415 /* Set continuous mode so it wraps around */
416 writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200417 u300_timer_base + U300_TIMER_APP_SGPT2M);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100418 /* Disable timer interrupts */
419 writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200420 u300_timer_base + U300_TIMER_APP_GPT2IE);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100421 /* Then enable the GP2 timer to use as a free running us counter */
422 writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
Linus Walleij5a5056c2013-04-08 10:50:11 +0200423 u300_timer_base + U300_TIMER_APP_EGPT2);
Linus Walleijbb3cee22009-04-23 10:22:13 +0100424
Russell King234b6ced2011-05-08 14:09:47 +0100425 /* Use general purpose timer 2 as clock source */
Linus Walleij5a5056c2013-04-08 10:50:11 +0200426 if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
Russell King234b6ced2011-05-08 14:09:47 +0100427 "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
Linus Walleij94250322011-05-31 22:10:03 +0100428 pr_err("timer: failed to initialize U300 clock source\n");
Linus Walleijbb3cee22009-04-23 10:22:13 +0100429
Linus Walleijcde21de2011-05-30 15:51:47 +0200430 /* Configure and register the clockevent */
431 clockevents_config_and_register(&clockevent_u300_1mhz, rate,
432 1, 0xffffffff);
433
Linus Walleijbb3cee22009-04-23 10:22:13 +0100434 /*
435 * TODO: init and register the rest of the timers too, they can be
436 * used by hrtimers!
437 */
438}
Linus Walleij5a5056c2013-04-08 10:50:11 +0200439
Linus Walleij5a5056c2013-04-08 10:50:11 +0200440CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
441 u300_timer_init_of);