Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Hardware modules present on the OMAP44xx chips |
| 3 | * |
| 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009-2010 Nokia Corporation |
| 6 | * |
| 7 | * Paul Walmsley |
| 8 | * Benoit Cousson |
| 9 | * |
| 10 | * This file is automatically generated from the OMAP hardware databases. |
| 11 | * We respectfully ask that any modifications to this file be coordinated |
| 12 | * with the public linux-omap@vger.kernel.org mailing list and the |
| 13 | * authors above to ensure that the autogeneration scripts are kept |
| 14 | * up-to-date with the file contents. |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License version 2 as |
| 18 | * published by the Free Software Foundation. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/io.h> |
| 22 | |
| 23 | #include <plat/omap_hwmod.h> |
| 24 | #include <plat/cpu.h> |
| 25 | |
| 26 | #include "omap_hwmod_common_data.h" |
| 27 | |
| 28 | #include "cm.h" |
| 29 | #include "prm-regbits-44xx.h" |
| 30 | |
| 31 | /* Base offset for all OMAP4 interrupts external to MPUSS */ |
| 32 | #define OMAP44XX_IRQ_GIC_START 32 |
| 33 | |
| 34 | /* Base offset for all OMAP4 dma requests */ |
| 35 | #define OMAP44XX_DMA_REQ_START 1 |
| 36 | |
| 37 | /* Backward references (IPs with Bus Master capability) */ |
| 38 | static struct omap_hwmod omap44xx_dmm_hwmod; |
| 39 | static struct omap_hwmod omap44xx_emif_fw_hwmod; |
| 40 | static struct omap_hwmod omap44xx_l3_instr_hwmod; |
| 41 | static struct omap_hwmod omap44xx_l3_main_1_hwmod; |
| 42 | static struct omap_hwmod omap44xx_l3_main_2_hwmod; |
| 43 | static struct omap_hwmod omap44xx_l3_main_3_hwmod; |
| 44 | static struct omap_hwmod omap44xx_l4_abe_hwmod; |
| 45 | static struct omap_hwmod omap44xx_l4_cfg_hwmod; |
| 46 | static struct omap_hwmod omap44xx_l4_per_hwmod; |
| 47 | static struct omap_hwmod omap44xx_l4_wkup_hwmod; |
| 48 | static struct omap_hwmod omap44xx_mpu_hwmod; |
| 49 | static struct omap_hwmod omap44xx_mpu_private_hwmod; |
| 50 | |
| 51 | /* |
| 52 | * Interconnects omap_hwmod structures |
| 53 | * hwmods that compose the global OMAP interconnect |
| 54 | */ |
| 55 | |
| 56 | /* |
| 57 | * 'dmm' class |
| 58 | * instance(s): dmm |
| 59 | */ |
| 60 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { |
| 61 | .name = "dmm", |
| 62 | }; |
| 63 | |
| 64 | /* dmm interface data */ |
| 65 | /* l3_main_1 -> dmm */ |
| 66 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { |
| 67 | .master = &omap44xx_l3_main_1_hwmod, |
| 68 | .slave = &omap44xx_dmm_hwmod, |
| 69 | .clk = "l3_div_ck", |
| 70 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 71 | }; |
| 72 | |
| 73 | /* mpu -> dmm */ |
| 74 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { |
| 75 | .master = &omap44xx_mpu_hwmod, |
| 76 | .slave = &omap44xx_dmm_hwmod, |
| 77 | .clk = "l3_div_ck", |
| 78 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 79 | }; |
| 80 | |
| 81 | /* dmm slave ports */ |
| 82 | static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { |
| 83 | &omap44xx_l3_main_1__dmm, |
| 84 | &omap44xx_mpu__dmm, |
| 85 | }; |
| 86 | |
| 87 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { |
| 88 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, |
| 89 | }; |
| 90 | |
| 91 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
| 92 | .name = "dmm", |
| 93 | .class = &omap44xx_dmm_hwmod_class, |
| 94 | .slaves = omap44xx_dmm_slaves, |
| 95 | .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), |
| 96 | .mpu_irqs = omap44xx_dmm_irqs, |
| 97 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs), |
| 98 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 99 | }; |
| 100 | |
| 101 | /* |
| 102 | * 'emif_fw' class |
| 103 | * instance(s): emif_fw |
| 104 | */ |
| 105 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { |
| 106 | .name = "emif_fw", |
| 107 | }; |
| 108 | |
| 109 | /* emif_fw interface data */ |
| 110 | /* dmm -> emif_fw */ |
| 111 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { |
| 112 | .master = &omap44xx_dmm_hwmod, |
| 113 | .slave = &omap44xx_emif_fw_hwmod, |
| 114 | .clk = "l3_div_ck", |
| 115 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 116 | }; |
| 117 | |
| 118 | /* l4_cfg -> emif_fw */ |
| 119 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { |
| 120 | .master = &omap44xx_l4_cfg_hwmod, |
| 121 | .slave = &omap44xx_emif_fw_hwmod, |
| 122 | .clk = "l4_div_ck", |
| 123 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 124 | }; |
| 125 | |
| 126 | /* emif_fw slave ports */ |
| 127 | static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { |
| 128 | &omap44xx_dmm__emif_fw, |
| 129 | &omap44xx_l4_cfg__emif_fw, |
| 130 | }; |
| 131 | |
| 132 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { |
| 133 | .name = "emif_fw", |
| 134 | .class = &omap44xx_emif_fw_hwmod_class, |
| 135 | .slaves = omap44xx_emif_fw_slaves, |
| 136 | .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), |
| 137 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 138 | }; |
| 139 | |
| 140 | /* |
| 141 | * 'l3' class |
| 142 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 |
| 143 | */ |
| 144 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { |
| 145 | .name = "l3", |
| 146 | }; |
| 147 | |
| 148 | /* l3_instr interface data */ |
| 149 | /* l3_main_3 -> l3_instr */ |
| 150 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { |
| 151 | .master = &omap44xx_l3_main_3_hwmod, |
| 152 | .slave = &omap44xx_l3_instr_hwmod, |
| 153 | .clk = "l3_div_ck", |
| 154 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 155 | }; |
| 156 | |
| 157 | /* l3_instr slave ports */ |
| 158 | static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { |
| 159 | &omap44xx_l3_main_3__l3_instr, |
| 160 | }; |
| 161 | |
| 162 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
| 163 | .name = "l3_instr", |
| 164 | .class = &omap44xx_l3_hwmod_class, |
| 165 | .slaves = omap44xx_l3_instr_slaves, |
| 166 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), |
| 167 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 168 | }; |
| 169 | |
| 170 | /* l3_main_2 -> l3_main_1 */ |
| 171 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { |
| 172 | .master = &omap44xx_l3_main_2_hwmod, |
| 173 | .slave = &omap44xx_l3_main_1_hwmod, |
| 174 | .clk = "l3_div_ck", |
| 175 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 176 | }; |
| 177 | |
| 178 | /* l4_cfg -> l3_main_1 */ |
| 179 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { |
| 180 | .master = &omap44xx_l4_cfg_hwmod, |
| 181 | .slave = &omap44xx_l3_main_1_hwmod, |
| 182 | .clk = "l4_div_ck", |
| 183 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 184 | }; |
| 185 | |
| 186 | /* mpu -> l3_main_1 */ |
| 187 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { |
| 188 | .master = &omap44xx_mpu_hwmod, |
| 189 | .slave = &omap44xx_l3_main_1_hwmod, |
| 190 | .clk = "l3_div_ck", |
| 191 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 192 | }; |
| 193 | |
| 194 | /* l3_main_1 slave ports */ |
| 195 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { |
| 196 | &omap44xx_l3_main_2__l3_main_1, |
| 197 | &omap44xx_l4_cfg__l3_main_1, |
| 198 | &omap44xx_mpu__l3_main_1, |
| 199 | }; |
| 200 | |
| 201 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
| 202 | .name = "l3_main_1", |
| 203 | .class = &omap44xx_l3_hwmod_class, |
| 204 | .slaves = omap44xx_l3_main_1_slaves, |
| 205 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), |
| 206 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 207 | }; |
| 208 | |
| 209 | /* l3_main_2 interface data */ |
| 210 | /* l3_main_1 -> l3_main_2 */ |
| 211 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { |
| 212 | .master = &omap44xx_l3_main_1_hwmod, |
| 213 | .slave = &omap44xx_l3_main_2_hwmod, |
| 214 | .clk = "l3_div_ck", |
| 215 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 216 | }; |
| 217 | |
| 218 | /* l4_cfg -> l3_main_2 */ |
| 219 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { |
| 220 | .master = &omap44xx_l4_cfg_hwmod, |
| 221 | .slave = &omap44xx_l3_main_2_hwmod, |
| 222 | .clk = "l4_div_ck", |
| 223 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 224 | }; |
| 225 | |
| 226 | /* l3_main_2 slave ports */ |
| 227 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { |
| 228 | &omap44xx_l3_main_1__l3_main_2, |
| 229 | &omap44xx_l4_cfg__l3_main_2, |
| 230 | }; |
| 231 | |
| 232 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
| 233 | .name = "l3_main_2", |
| 234 | .class = &omap44xx_l3_hwmod_class, |
| 235 | .slaves = omap44xx_l3_main_2_slaves, |
| 236 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), |
| 237 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 238 | }; |
| 239 | |
| 240 | /* l3_main_3 interface data */ |
| 241 | /* l3_main_1 -> l3_main_3 */ |
| 242 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { |
| 243 | .master = &omap44xx_l3_main_1_hwmod, |
| 244 | .slave = &omap44xx_l3_main_3_hwmod, |
| 245 | .clk = "l3_div_ck", |
| 246 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 247 | }; |
| 248 | |
| 249 | /* l3_main_2 -> l3_main_3 */ |
| 250 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { |
| 251 | .master = &omap44xx_l3_main_2_hwmod, |
| 252 | .slave = &omap44xx_l3_main_3_hwmod, |
| 253 | .clk = "l3_div_ck", |
| 254 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 255 | }; |
| 256 | |
| 257 | /* l4_cfg -> l3_main_3 */ |
| 258 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { |
| 259 | .master = &omap44xx_l4_cfg_hwmod, |
| 260 | .slave = &omap44xx_l3_main_3_hwmod, |
| 261 | .clk = "l4_div_ck", |
| 262 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 263 | }; |
| 264 | |
| 265 | /* l3_main_3 slave ports */ |
| 266 | static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { |
| 267 | &omap44xx_l3_main_1__l3_main_3, |
| 268 | &omap44xx_l3_main_2__l3_main_3, |
| 269 | &omap44xx_l4_cfg__l3_main_3, |
| 270 | }; |
| 271 | |
| 272 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
| 273 | .name = "l3_main_3", |
| 274 | .class = &omap44xx_l3_hwmod_class, |
| 275 | .slaves = omap44xx_l3_main_3_slaves, |
| 276 | .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), |
| 277 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 278 | }; |
| 279 | |
| 280 | /* |
| 281 | * 'l4' class |
| 282 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup |
| 283 | */ |
| 284 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { |
| 285 | .name = "l4", |
| 286 | }; |
| 287 | |
| 288 | /* l4_abe interface data */ |
| 289 | /* l3_main_1 -> l4_abe */ |
| 290 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { |
| 291 | .master = &omap44xx_l3_main_1_hwmod, |
| 292 | .slave = &omap44xx_l4_abe_hwmod, |
| 293 | .clk = "l3_div_ck", |
| 294 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 295 | }; |
| 296 | |
| 297 | /* mpu -> l4_abe */ |
| 298 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { |
| 299 | .master = &omap44xx_mpu_hwmod, |
| 300 | .slave = &omap44xx_l4_abe_hwmod, |
| 301 | .clk = "ocp_abe_iclk", |
| 302 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 303 | }; |
| 304 | |
| 305 | /* l4_abe slave ports */ |
| 306 | static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { |
| 307 | &omap44xx_l3_main_1__l4_abe, |
| 308 | &omap44xx_mpu__l4_abe, |
| 309 | }; |
| 310 | |
| 311 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
| 312 | .name = "l4_abe", |
| 313 | .class = &omap44xx_l4_hwmod_class, |
| 314 | .slaves = omap44xx_l4_abe_slaves, |
| 315 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), |
| 316 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 317 | }; |
| 318 | |
| 319 | /* l4_cfg interface data */ |
| 320 | /* l3_main_1 -> l4_cfg */ |
| 321 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { |
| 322 | .master = &omap44xx_l3_main_1_hwmod, |
| 323 | .slave = &omap44xx_l4_cfg_hwmod, |
| 324 | .clk = "l3_div_ck", |
| 325 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 326 | }; |
| 327 | |
| 328 | /* l4_cfg slave ports */ |
| 329 | static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { |
| 330 | &omap44xx_l3_main_1__l4_cfg, |
| 331 | }; |
| 332 | |
| 333 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
| 334 | .name = "l4_cfg", |
| 335 | .class = &omap44xx_l4_hwmod_class, |
| 336 | .slaves = omap44xx_l4_cfg_slaves, |
| 337 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), |
| 338 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 339 | }; |
| 340 | |
| 341 | /* l4_per interface data */ |
| 342 | /* l3_main_2 -> l4_per */ |
| 343 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { |
| 344 | .master = &omap44xx_l3_main_2_hwmod, |
| 345 | .slave = &omap44xx_l4_per_hwmod, |
| 346 | .clk = "l3_div_ck", |
| 347 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 348 | }; |
| 349 | |
| 350 | /* l4_per slave ports */ |
| 351 | static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { |
| 352 | &omap44xx_l3_main_2__l4_per, |
| 353 | }; |
| 354 | |
| 355 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
| 356 | .name = "l4_per", |
| 357 | .class = &omap44xx_l4_hwmod_class, |
| 358 | .slaves = omap44xx_l4_per_slaves, |
| 359 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), |
| 360 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 361 | }; |
| 362 | |
| 363 | /* l4_wkup interface data */ |
| 364 | /* l4_cfg -> l4_wkup */ |
| 365 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { |
| 366 | .master = &omap44xx_l4_cfg_hwmod, |
| 367 | .slave = &omap44xx_l4_wkup_hwmod, |
| 368 | .clk = "l4_div_ck", |
| 369 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 370 | }; |
| 371 | |
| 372 | /* l4_wkup slave ports */ |
| 373 | static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { |
| 374 | &omap44xx_l4_cfg__l4_wkup, |
| 375 | }; |
| 376 | |
| 377 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
| 378 | .name = "l4_wkup", |
| 379 | .class = &omap44xx_l4_hwmod_class, |
| 380 | .slaves = omap44xx_l4_wkup_slaves, |
| 381 | .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), |
| 382 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 383 | }; |
| 384 | |
| 385 | /* |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame^] | 386 | * 'i2c' class |
| 387 | * multimaster high-speed i2c controller |
| 388 | */ |
| 389 | |
| 390 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
| 391 | .sysc_offs = 0x0010, |
| 392 | .syss_offs = 0x0090, |
| 393 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 394 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET | |
| 395 | SYSC_HAS_AUTOIDLE), |
| 396 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 397 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 398 | }; |
| 399 | |
| 400 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
| 401 | .name = "i2c", |
| 402 | .sysc = &omap44xx_i2c_sysc, |
| 403 | }; |
| 404 | |
| 405 | /* i2c1 */ |
| 406 | static struct omap_hwmod omap44xx_i2c1_hwmod; |
| 407 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { |
| 408 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, |
| 409 | }; |
| 410 | |
| 411 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
| 412 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, |
| 413 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, |
| 414 | }; |
| 415 | |
| 416 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { |
| 417 | { |
| 418 | .pa_start = 0x48070000, |
| 419 | .pa_end = 0x480700ff, |
| 420 | .flags = ADDR_TYPE_RT |
| 421 | }, |
| 422 | }; |
| 423 | |
| 424 | /* l4_per -> i2c1 */ |
| 425 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { |
| 426 | .master = &omap44xx_l4_per_hwmod, |
| 427 | .slave = &omap44xx_i2c1_hwmod, |
| 428 | .clk = "l4_div_ck", |
| 429 | .addr = omap44xx_i2c1_addrs, |
| 430 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), |
| 431 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 432 | }; |
| 433 | |
| 434 | /* i2c1 slave ports */ |
| 435 | static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { |
| 436 | &omap44xx_l4_per__i2c1, |
| 437 | }; |
| 438 | |
| 439 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
| 440 | .name = "i2c1", |
| 441 | .class = &omap44xx_i2c_hwmod_class, |
| 442 | .flags = HWMOD_INIT_NO_RESET, |
| 443 | .mpu_irqs = omap44xx_i2c1_irqs, |
| 444 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), |
| 445 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
| 446 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), |
| 447 | .main_clk = "i2c1_fck", |
| 448 | .prcm = { |
| 449 | .omap4 = { |
| 450 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, |
| 451 | }, |
| 452 | }, |
| 453 | .slaves = omap44xx_i2c1_slaves, |
| 454 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), |
| 455 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 456 | }; |
| 457 | |
| 458 | /* i2c2 */ |
| 459 | static struct omap_hwmod omap44xx_i2c2_hwmod; |
| 460 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { |
| 461 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, |
| 462 | }; |
| 463 | |
| 464 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
| 465 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, |
| 466 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, |
| 467 | }; |
| 468 | |
| 469 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { |
| 470 | { |
| 471 | .pa_start = 0x48072000, |
| 472 | .pa_end = 0x480720ff, |
| 473 | .flags = ADDR_TYPE_RT |
| 474 | }, |
| 475 | }; |
| 476 | |
| 477 | /* l4_per -> i2c2 */ |
| 478 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { |
| 479 | .master = &omap44xx_l4_per_hwmod, |
| 480 | .slave = &omap44xx_i2c2_hwmod, |
| 481 | .clk = "l4_div_ck", |
| 482 | .addr = omap44xx_i2c2_addrs, |
| 483 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), |
| 484 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 485 | }; |
| 486 | |
| 487 | /* i2c2 slave ports */ |
| 488 | static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { |
| 489 | &omap44xx_l4_per__i2c2, |
| 490 | }; |
| 491 | |
| 492 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
| 493 | .name = "i2c2", |
| 494 | .class = &omap44xx_i2c_hwmod_class, |
| 495 | .flags = HWMOD_INIT_NO_RESET, |
| 496 | .mpu_irqs = omap44xx_i2c2_irqs, |
| 497 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), |
| 498 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
| 499 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), |
| 500 | .main_clk = "i2c2_fck", |
| 501 | .prcm = { |
| 502 | .omap4 = { |
| 503 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, |
| 504 | }, |
| 505 | }, |
| 506 | .slaves = omap44xx_i2c2_slaves, |
| 507 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), |
| 508 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 509 | }; |
| 510 | |
| 511 | /* i2c3 */ |
| 512 | static struct omap_hwmod omap44xx_i2c3_hwmod; |
| 513 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { |
| 514 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, |
| 515 | }; |
| 516 | |
| 517 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
| 518 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, |
| 519 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, |
| 520 | }; |
| 521 | |
| 522 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { |
| 523 | { |
| 524 | .pa_start = 0x48060000, |
| 525 | .pa_end = 0x480600ff, |
| 526 | .flags = ADDR_TYPE_RT |
| 527 | }, |
| 528 | }; |
| 529 | |
| 530 | /* l4_per -> i2c3 */ |
| 531 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { |
| 532 | .master = &omap44xx_l4_per_hwmod, |
| 533 | .slave = &omap44xx_i2c3_hwmod, |
| 534 | .clk = "l4_div_ck", |
| 535 | .addr = omap44xx_i2c3_addrs, |
| 536 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), |
| 537 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 538 | }; |
| 539 | |
| 540 | /* i2c3 slave ports */ |
| 541 | static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { |
| 542 | &omap44xx_l4_per__i2c3, |
| 543 | }; |
| 544 | |
| 545 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
| 546 | .name = "i2c3", |
| 547 | .class = &omap44xx_i2c_hwmod_class, |
| 548 | .flags = HWMOD_INIT_NO_RESET, |
| 549 | .mpu_irqs = omap44xx_i2c3_irqs, |
| 550 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), |
| 551 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
| 552 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), |
| 553 | .main_clk = "i2c3_fck", |
| 554 | .prcm = { |
| 555 | .omap4 = { |
| 556 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, |
| 557 | }, |
| 558 | }, |
| 559 | .slaves = omap44xx_i2c3_slaves, |
| 560 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), |
| 561 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 562 | }; |
| 563 | |
| 564 | /* i2c4 */ |
| 565 | static struct omap_hwmod omap44xx_i2c4_hwmod; |
| 566 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { |
| 567 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, |
| 568 | }; |
| 569 | |
| 570 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
| 571 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, |
| 572 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, |
| 573 | }; |
| 574 | |
| 575 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { |
| 576 | { |
| 577 | .pa_start = 0x48350000, |
| 578 | .pa_end = 0x483500ff, |
| 579 | .flags = ADDR_TYPE_RT |
| 580 | }, |
| 581 | }; |
| 582 | |
| 583 | /* l4_per -> i2c4 */ |
| 584 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { |
| 585 | .master = &omap44xx_l4_per_hwmod, |
| 586 | .slave = &omap44xx_i2c4_hwmod, |
| 587 | .clk = "l4_div_ck", |
| 588 | .addr = omap44xx_i2c4_addrs, |
| 589 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), |
| 590 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 591 | }; |
| 592 | |
| 593 | /* i2c4 slave ports */ |
| 594 | static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { |
| 595 | &omap44xx_l4_per__i2c4, |
| 596 | }; |
| 597 | |
| 598 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
| 599 | .name = "i2c4", |
| 600 | .class = &omap44xx_i2c_hwmod_class, |
| 601 | .flags = HWMOD_INIT_NO_RESET, |
| 602 | .mpu_irqs = omap44xx_i2c4_irqs, |
| 603 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), |
| 604 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
| 605 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), |
| 606 | .main_clk = "i2c4_fck", |
| 607 | .prcm = { |
| 608 | .omap4 = { |
| 609 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, |
| 610 | }, |
| 611 | }, |
| 612 | .slaves = omap44xx_i2c4_slaves, |
| 613 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), |
| 614 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 615 | }; |
| 616 | |
| 617 | /* |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 618 | * 'mpu_bus' class |
| 619 | * instance(s): mpu_private |
| 620 | */ |
| 621 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
| 622 | .name = "mpu_bus", |
| 623 | }; |
| 624 | |
| 625 | /* mpu_private interface data */ |
| 626 | /* mpu -> mpu_private */ |
| 627 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { |
| 628 | .master = &omap44xx_mpu_hwmod, |
| 629 | .slave = &omap44xx_mpu_private_hwmod, |
| 630 | .clk = "l3_div_ck", |
| 631 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 632 | }; |
| 633 | |
| 634 | /* mpu_private slave ports */ |
| 635 | static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { |
| 636 | &omap44xx_mpu__mpu_private, |
| 637 | }; |
| 638 | |
| 639 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
| 640 | .name = "mpu_private", |
| 641 | .class = &omap44xx_mpu_bus_hwmod_class, |
| 642 | .slaves = omap44xx_mpu_private_slaves, |
| 643 | .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), |
| 644 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 645 | }; |
| 646 | |
| 647 | /* |
| 648 | * 'mpu' class |
| 649 | * mpu sub-system |
| 650 | */ |
| 651 | |
| 652 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { |
| 653 | .name = "mpu", |
| 654 | }; |
| 655 | |
| 656 | /* mpu */ |
| 657 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { |
| 658 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, |
| 659 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, |
| 660 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, |
| 661 | }; |
| 662 | |
| 663 | /* mpu master ports */ |
| 664 | static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { |
| 665 | &omap44xx_mpu__l3_main_1, |
| 666 | &omap44xx_mpu__l4_abe, |
| 667 | &omap44xx_mpu__dmm, |
| 668 | }; |
| 669 | |
| 670 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
| 671 | .name = "mpu", |
| 672 | .class = &omap44xx_mpu_hwmod_class, |
| 673 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 674 | .mpu_irqs = omap44xx_mpu_irqs, |
| 675 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), |
| 676 | .main_clk = "dpll_mpu_m2_ck", |
| 677 | .prcm = { |
| 678 | .omap4 = { |
| 679 | .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, |
| 680 | }, |
| 681 | }, |
| 682 | .masters = omap44xx_mpu_masters, |
| 683 | .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), |
| 684 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 685 | }; |
| 686 | |
Benoit Cousson | 92b18d1 | 2010-09-23 20:02:41 +0530 | [diff] [blame] | 687 | /* |
| 688 | * 'wd_timer' class |
| 689 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
| 690 | * overflow condition |
| 691 | */ |
| 692 | |
| 693 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { |
| 694 | .rev_offs = 0x0000, |
| 695 | .sysc_offs = 0x0010, |
| 696 | .syss_offs = 0x0014, |
| 697 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | |
| 698 | SYSC_HAS_SOFTRESET), |
| 699 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 700 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 701 | }; |
| 702 | |
Kevin Hilman | 69758ab | 2010-10-01 13:24:10 -0700 | [diff] [blame] | 703 | /* |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 704 | * 'uart' class |
| 705 | * universal asynchronous receiver/transmitter (uart) |
| 706 | */ |
| 707 | |
| 708 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
| 709 | .rev_offs = 0x0050, |
| 710 | .sysc_offs = 0x0054, |
| 711 | .syss_offs = 0x0058, |
| 712 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 713 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 714 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 715 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 716 | }; |
| 717 | |
Benoit Cousson | 92b18d1 | 2010-09-23 20:02:41 +0530 | [diff] [blame] | 718 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
| 719 | .name = "wd_timer", |
| 720 | .sysc = &omap44xx_wd_timer_sysc, |
| 721 | }; |
| 722 | |
| 723 | /* wd_timer2 */ |
| 724 | static struct omap_hwmod omap44xx_wd_timer2_hwmod; |
| 725 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
| 726 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, |
| 727 | }; |
| 728 | |
| 729 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
| 730 | { |
| 731 | .pa_start = 0x4a314000, |
| 732 | .pa_end = 0x4a31407f, |
| 733 | .flags = ADDR_TYPE_RT |
| 734 | }, |
| 735 | }; |
| 736 | |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 737 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
| 738 | .name = "uart", |
| 739 | .sysc = &omap44xx_uart_sysc, |
| 740 | }; |
| 741 | |
| 742 | /* uart1 */ |
| 743 | static struct omap_hwmod omap44xx_uart1_hwmod; |
| 744 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
| 745 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, |
| 746 | }; |
| 747 | |
| 748 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
| 749 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, |
| 750 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, |
| 751 | }; |
| 752 | |
| 753 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
| 754 | { |
| 755 | .pa_start = 0x4806a000, |
| 756 | .pa_end = 0x4806a0ff, |
| 757 | .flags = ADDR_TYPE_RT |
| 758 | }, |
| 759 | }; |
| 760 | |
| 761 | /* l4_per -> uart1 */ |
| 762 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { |
| 763 | .master = &omap44xx_l4_per_hwmod, |
| 764 | .slave = &omap44xx_uart1_hwmod, |
| 765 | .clk = "l4_div_ck", |
| 766 | .addr = omap44xx_uart1_addrs, |
| 767 | .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs), |
| 768 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 769 | }; |
| 770 | |
| 771 | /* uart1 slave ports */ |
| 772 | static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { |
| 773 | &omap44xx_l4_per__uart1, |
| 774 | }; |
| 775 | |
| 776 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
| 777 | .name = "uart1", |
| 778 | .class = &omap44xx_uart_hwmod_class, |
| 779 | .mpu_irqs = omap44xx_uart1_irqs, |
| 780 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), |
| 781 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
| 782 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), |
| 783 | .main_clk = "uart1_fck", |
| 784 | .prcm = { |
| 785 | .omap4 = { |
| 786 | .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, |
| 787 | }, |
| 788 | }, |
| 789 | .slaves = omap44xx_uart1_slaves, |
| 790 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), |
| 791 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 792 | }; |
| 793 | |
| 794 | /* uart2 */ |
| 795 | static struct omap_hwmod omap44xx_uart2_hwmod; |
| 796 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
| 797 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, |
| 798 | }; |
| 799 | |
| 800 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
| 801 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, |
| 802 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, |
| 803 | }; |
| 804 | |
| 805 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { |
| 806 | { |
| 807 | .pa_start = 0x4806c000, |
| 808 | .pa_end = 0x4806c0ff, |
| 809 | .flags = ADDR_TYPE_RT |
| 810 | }, |
| 811 | }; |
| 812 | |
Benoit Cousson | 92b18d1 | 2010-09-23 20:02:41 +0530 | [diff] [blame] | 813 | /* l4_wkup -> wd_timer2 */ |
| 814 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { |
| 815 | .master = &omap44xx_l4_wkup_hwmod, |
| 816 | .slave = &omap44xx_wd_timer2_hwmod, |
| 817 | .clk = "l4_wkup_clk_mux_ck", |
| 818 | .addr = omap44xx_wd_timer2_addrs, |
| 819 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), |
| 820 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 821 | }; |
| 822 | |
| 823 | /* wd_timer2 slave ports */ |
| 824 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { |
| 825 | &omap44xx_l4_wkup__wd_timer2, |
| 826 | }; |
| 827 | |
| 828 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
| 829 | .name = "wd_timer2", |
| 830 | .class = &omap44xx_wd_timer_hwmod_class, |
| 831 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
| 832 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), |
| 833 | .main_clk = "wd_timer2_fck", |
| 834 | .prcm = { |
| 835 | .omap4 = { |
| 836 | .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, |
| 837 | }, |
| 838 | }, |
| 839 | .slaves = omap44xx_wd_timer2_slaves, |
| 840 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), |
| 841 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 842 | }; |
| 843 | |
| 844 | /* wd_timer3 */ |
| 845 | static struct omap_hwmod omap44xx_wd_timer3_hwmod; |
| 846 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
| 847 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, |
| 848 | }; |
| 849 | |
| 850 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { |
| 851 | { |
| 852 | .pa_start = 0x40130000, |
| 853 | .pa_end = 0x4013007f, |
| 854 | .flags = ADDR_TYPE_RT |
| 855 | }, |
| 856 | }; |
| 857 | |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 858 | /* l4_per -> uart2 */ |
| 859 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { |
| 860 | .master = &omap44xx_l4_per_hwmod, |
| 861 | .slave = &omap44xx_uart2_hwmod, |
| 862 | .clk = "l4_div_ck", |
| 863 | .addr = omap44xx_uart2_addrs, |
| 864 | .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs), |
| 865 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 866 | }; |
| 867 | |
| 868 | /* uart2 slave ports */ |
| 869 | static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { |
| 870 | &omap44xx_l4_per__uart2, |
| 871 | }; |
| 872 | |
| 873 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
| 874 | .name = "uart2", |
| 875 | .class = &omap44xx_uart_hwmod_class, |
| 876 | .mpu_irqs = omap44xx_uart2_irqs, |
| 877 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), |
| 878 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
| 879 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), |
| 880 | .main_clk = "uart2_fck", |
| 881 | .prcm = { |
| 882 | .omap4 = { |
| 883 | .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, |
| 884 | }, |
| 885 | }, |
| 886 | .slaves = omap44xx_uart2_slaves, |
| 887 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), |
| 888 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 889 | }; |
| 890 | |
| 891 | /* uart3 */ |
| 892 | static struct omap_hwmod omap44xx_uart3_hwmod; |
| 893 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
| 894 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, |
| 895 | }; |
| 896 | |
| 897 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
| 898 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, |
| 899 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, |
| 900 | }; |
| 901 | |
| 902 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { |
| 903 | { |
| 904 | .pa_start = 0x48020000, |
| 905 | .pa_end = 0x480200ff, |
| 906 | .flags = ADDR_TYPE_RT |
| 907 | }, |
| 908 | }; |
| 909 | |
Benoit Cousson | 92b18d1 | 2010-09-23 20:02:41 +0530 | [diff] [blame] | 910 | /* l4_abe -> wd_timer3 */ |
| 911 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { |
| 912 | .master = &omap44xx_l4_abe_hwmod, |
| 913 | .slave = &omap44xx_wd_timer3_hwmod, |
| 914 | .clk = "ocp_abe_iclk", |
| 915 | .addr = omap44xx_wd_timer3_addrs, |
| 916 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), |
| 917 | .user = OCP_USER_MPU, |
| 918 | }; |
| 919 | |
| 920 | /* l4_abe -> wd_timer3 (dma) */ |
| 921 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { |
| 922 | { |
| 923 | .pa_start = 0x49030000, |
| 924 | .pa_end = 0x4903007f, |
| 925 | .flags = ADDR_TYPE_RT |
| 926 | }, |
| 927 | }; |
| 928 | |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 929 | /* l4_per -> uart3 */ |
| 930 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { |
| 931 | .master = &omap44xx_l4_per_hwmod, |
| 932 | .slave = &omap44xx_uart3_hwmod, |
| 933 | .clk = "l4_div_ck", |
| 934 | .addr = omap44xx_uart3_addrs, |
| 935 | .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs), |
| 936 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 937 | }; |
| 938 | |
| 939 | /* uart3 slave ports */ |
| 940 | static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { |
| 941 | &omap44xx_l4_per__uart3, |
| 942 | }; |
| 943 | |
| 944 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
| 945 | .name = "uart3", |
| 946 | .class = &omap44xx_uart_hwmod_class, |
| 947 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 948 | .mpu_irqs = omap44xx_uart3_irqs, |
| 949 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), |
| 950 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
| 951 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), |
| 952 | .main_clk = "uart3_fck", |
| 953 | .prcm = { |
| 954 | .omap4 = { |
| 955 | .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, |
| 956 | }, |
| 957 | }, |
| 958 | .slaves = omap44xx_uart3_slaves, |
| 959 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), |
| 960 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 961 | }; |
| 962 | |
| 963 | /* uart4 */ |
| 964 | static struct omap_hwmod omap44xx_uart4_hwmod; |
| 965 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
| 966 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, |
| 967 | }; |
| 968 | |
| 969 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
| 970 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, |
| 971 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, |
| 972 | }; |
| 973 | |
| 974 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { |
| 975 | { |
| 976 | .pa_start = 0x4806e000, |
| 977 | .pa_end = 0x4806e0ff, |
| 978 | .flags = ADDR_TYPE_RT |
| 979 | }, |
| 980 | }; |
| 981 | |
Benoit Cousson | 92b18d1 | 2010-09-23 20:02:41 +0530 | [diff] [blame] | 982 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { |
| 983 | .master = &omap44xx_l4_abe_hwmod, |
| 984 | .slave = &omap44xx_wd_timer3_hwmod, |
| 985 | .clk = "ocp_abe_iclk", |
| 986 | .addr = omap44xx_wd_timer3_dma_addrs, |
| 987 | .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), |
| 988 | .user = OCP_USER_SDMA, |
| 989 | }; |
| 990 | |
| 991 | /* wd_timer3 slave ports */ |
| 992 | static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { |
| 993 | &omap44xx_l4_abe__wd_timer3, |
| 994 | &omap44xx_l4_abe__wd_timer3_dma, |
| 995 | }; |
| 996 | |
| 997 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
| 998 | .name = "wd_timer3", |
| 999 | .class = &omap44xx_wd_timer_hwmod_class, |
| 1000 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
| 1001 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), |
| 1002 | .main_clk = "wd_timer3_fck", |
| 1003 | .prcm = { |
| 1004 | .omap4 = { |
| 1005 | .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, |
| 1006 | }, |
| 1007 | }, |
| 1008 | .slaves = omap44xx_wd_timer3_slaves, |
| 1009 | .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), |
| 1010 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 1011 | }; |
| 1012 | |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 1013 | /* l4_per -> uart4 */ |
| 1014 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { |
| 1015 | .master = &omap44xx_l4_per_hwmod, |
| 1016 | .slave = &omap44xx_uart4_hwmod, |
| 1017 | .clk = "l4_div_ck", |
| 1018 | .addr = omap44xx_uart4_addrs, |
| 1019 | .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs), |
| 1020 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1021 | }; |
| 1022 | |
| 1023 | /* uart4 slave ports */ |
| 1024 | static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { |
| 1025 | &omap44xx_l4_per__uart4, |
| 1026 | }; |
| 1027 | |
| 1028 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
| 1029 | .name = "uart4", |
| 1030 | .class = &omap44xx_uart_hwmod_class, |
| 1031 | .mpu_irqs = omap44xx_uart4_irqs, |
| 1032 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), |
| 1033 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
| 1034 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), |
| 1035 | .main_clk = "uart4_fck", |
| 1036 | .prcm = { |
| 1037 | .omap4 = { |
| 1038 | .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, |
| 1039 | }, |
| 1040 | }, |
| 1041 | .slaves = omap44xx_uart4_slaves, |
| 1042 | .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), |
| 1043 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
| 1044 | }; |
| 1045 | |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 1046 | static __initdata struct omap_hwmod *omap44xx_hwmods[] = { |
| 1047 | /* dmm class */ |
| 1048 | &omap44xx_dmm_hwmod, |
| 1049 | /* emif_fw class */ |
| 1050 | &omap44xx_emif_fw_hwmod, |
| 1051 | /* l3 class */ |
| 1052 | &omap44xx_l3_instr_hwmod, |
| 1053 | &omap44xx_l3_main_1_hwmod, |
| 1054 | &omap44xx_l3_main_2_hwmod, |
| 1055 | &omap44xx_l3_main_3_hwmod, |
| 1056 | /* l4 class */ |
| 1057 | &omap44xx_l4_abe_hwmod, |
| 1058 | &omap44xx_l4_cfg_hwmod, |
| 1059 | &omap44xx_l4_per_hwmod, |
| 1060 | &omap44xx_l4_wkup_hwmod, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame^] | 1061 | /* i2c class */ |
| 1062 | &omap44xx_i2c1_hwmod, |
| 1063 | &omap44xx_i2c2_hwmod, |
| 1064 | &omap44xx_i2c3_hwmod, |
| 1065 | &omap44xx_i2c4_hwmod, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 1066 | /* mpu_bus class */ |
| 1067 | &omap44xx_mpu_private_hwmod, |
| 1068 | |
| 1069 | /* mpu class */ |
| 1070 | &omap44xx_mpu_hwmod, |
Benoit Cousson | 92b18d1 | 2010-09-23 20:02:41 +0530 | [diff] [blame] | 1071 | /* wd_timer class */ |
| 1072 | &omap44xx_wd_timer2_hwmod, |
| 1073 | &omap44xx_wd_timer3_hwmod, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 1074 | |
| 1075 | /* uart class */ |
| 1076 | &omap44xx_uart1_hwmod, |
| 1077 | &omap44xx_uart2_hwmod, |
| 1078 | &omap44xx_uart3_hwmod, |
| 1079 | &omap44xx_uart4_hwmod, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 1080 | NULL, |
| 1081 | }; |
| 1082 | |
| 1083 | int __init omap44xx_hwmod_init(void) |
| 1084 | { |
| 1085 | return omap_hwmod_init(omap44xx_hwmods); |
| 1086 | } |
| 1087 | |