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gerrit-public.fairphone.software / kernel / msm-4.9 / f777fdeceadc3c13f01854249fcd0ec92b515c92 / . / arch / arm64 / boot / dts / qcom / sdm845-pinctrl.dtsi
blob: 6d6f7758ca00d0f8ca2758c29939f3af33c4427e [file] [log] [blame]
Banajit Goswamib016de92017-02-15 21:02:30 -0800[diff] [blame]1/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Kyle Yan679cbee2016-07-27 16:55:20 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
Channagoud Kadabif777fde2017-03-07 14:21:25 -0800[diff] [blame^]14 tlmm: pinctrl@03800000 {
Kyle Yan6a20fae2017-02-14 13:34:41 -0800[diff] [blame]15 compatible = "qcom,sdm845-pinctrl";
Kyle Yan679cbee2016-07-27 16:55:20 -0700[diff] [blame]16 reg = <0x03800000 0xc00000>;
17 interrupts = <0 208 0>;
18 gpio-controller;
19 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
Banajit Goswamib016de92017-02-15 21:02:30 -0800[diff] [blame]22
23 wcd9xxx_intr {
24 wcd_intr_default: wcd_intr_default{
25 mux {
26 pins = "gpio54";
27 function = "gpio";
28 };
29
30 config {
31 pins = "gpio54";
32 drive-strength = <2>; /* 2 mA */
33 bias-pull-down; /* pull down */
34 input-enable;
35 };
36 };
37 };
38
39 cdc_reset_ctrl {
40 cdc_reset_sleep: cdc_reset_sleep {
41 mux {
42 pins = "gpio64";
43 function = "gpio";
44 };
45 config {
46 pins = "gpio64";
47 drive-strength = <2>;
48 bias-disable;
49 output-low;
50 };
51 };
52
53 cdc_reset_active:cdc_reset_active {
54 mux {
55 pins = "gpio64";
56 function = "gpio";
57 };
58 config {
59 pins = "gpio64";
60 drive-strength = <8>;
61 bias-pull-down;
62 output-high;
63 };
64 };
65 };
66
67 spkr_i2s_clk_pin {
68 spkr_i2s_clk_sleep: spkr_i2s_clk_sleep {
69 mux {
70 pins = "gpio69";
71 function = "spkr_i2s";
72 };
73
74 config {
75 pins = "gpio69";
76 drive-strength = <2>; /* 2 mA */
77 bias-pull-down; /* PULL DOWN */
78 };
79 };
80
81 spkr_i2s_clk_active: spkr_i2s_clk_active {
82 mux {
83 pins = "gpio69";
84 function = "spkr_i2s";
85 };
86
87 config {
88 pins = "gpio69";
89 drive-strength = <8>; /* 8 mA */
90 bias-disable; /* NO PULL */
91 };
92 };
93 };
94
95 wcd_gnd_mic_swap {
96 wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle {
97 mux {
98 pins = "gpio51";
99 function = "gpio";
100 };
101 config {
102 pins = "gpio51";
103 drive-strength = <2>;
104 bias-pull-down;
105 output-low;
106 };
107 };
108
109 wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active {
110 mux {
111 pins = "gpio51";
112 function = "gpio";
113 };
114 config {
115 pins = "gpio51";
116 drive-strength = <2>;
117 bias-disable;
118 output-high;
119 };
120 };
121 };
122
123 pri_aux_pcm_clk {
124 pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {
125 mux {
126 pins = "gpio65";
127 function = "gpio";
128 };
129
130 config {
131 pins = "gpio65";
132 drive-strength = <2>; /* 2 mA */
133 bias-pull-down; /* PULL DOWN */
134 input-enable;
135 };
136 };
137
138 pri_aux_pcm_clk_active: pri_aux_pcm_clk_active {
139 mux {
140 pins = "gpio65";
141 function = "pri_mi2s";
142 };
143
144 config {
145 pins = "gpio65";
146 drive-strength = <8>; /* 8 mA */
147 bias-disable; /* NO PULL */
148 output-high;
149 };
150 };
151 };
152
153 pri_aux_pcm_sync {
154 pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep {
155 mux {
156 pins = "gpio66";
157 function = "gpio";
158 };
159
160 config {
161 pins = "gpio66";
162 drive-strength = <2>; /* 2 mA */
163 bias-pull-down; /* PULL DOWN */
164 input-enable;
165 };
166 };
167
168 pri_aux_pcm_sync_active: pri_aux_pcm_sync_active {
169 mux {
170 pins = "gpio66";
171 function = "pri_mi2s_ws";
172 };
173
174 config {
175 pins = "gpio66";
176 drive-strength = <8>; /* 8 mA */
177 bias-disable; /* NO PULL */
178 output-high;
179 };
180 };
181 };
182
183 pri_aux_pcm_din {
184 pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep {
185 mux {
186 pins = "gpio67";
187 function = "gpio";
188 };
189
190 config {
191 pins = "gpio67";
192 drive-strength = <2>; /* 2 mA */
193 bias-pull-down; /* PULL DOWN */
194 input-enable;
195 };
196 };
197
198 pri_aux_pcm_din_active: pri_aux_pcm_din_active {
199 mux {
200 pins = "gpio67";
201 function = "pri_mi2s";
202 };
203
204 config {
205 pins = "gpio67";
206 drive-strength = <8>; /* 8 mA */
207 bias-disable; /* NO PULL */
208 };
209 };
210 };
211
212 pri_aux_pcm_dout {
213 pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
214 mux {
215 pins = "gpio68";
216 function = "gpio";
217 };
218
219 config {
220 pins = "gpio68";
221 drive-strength = <2>; /* 2 mA */
222 bias-pull-down; /* PULL DOWN */
223 input-enable;
224 };
225 };
226
227 pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
228 mux {
229 pins = "gpio68";
230 function = "pri_mi2s";
231 };
232
233 config {
234 pins = "gpio68";
235 drive-strength = <8>; /* 8 mA */
236 bias-disable; /* NO PULL */
237 };
238 };
239 };
240
241 sec_aux_pcm {
242 sec_aux_pcm_sleep: sec_aux_pcm_sleep {
243 mux {
244 pins = "gpio80", "gpio81";
245 function = "gpio";
246 };
247
248 config {
249 pins = "gpio80", "gpio81";
250 drive-strength = <2>; /* 2 mA */
251 bias-pull-down; /* PULL DOWN */
252 input-enable;
253 };
254 };
255
256 sec_aux_pcm_active: sec_aux_pcm_active {
257 mux {
258 pins = "gpio80", "gpio81";
259 function = "sec_mi2s";
260 };
261
262 config {
263 pins = "gpio80", "gpio81";
264 drive-strength = <8>; /* 8 mA */
265 bias-disable; /* NO PULL */
266 };
267 };
268 };
269
270 sec_aux_pcm_din {
271 sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep {
272 mux {
273 pins = "gpio82";
274 function = "gpio";
275 };
276
277 config {
278 pins = "gpio82";
279 drive-strength = <2>; /* 2 mA */
280 bias-pull-down; /* PULL DOWN */
281 input-enable;
282 };
283 };
284
285 sec_aux_pcm_din_active: sec_aux_pcm_din_active {
286 mux {
287 pins = "gpio82";
288 function = "sec_mi2s";
289 };
290
291 config {
292 pins = "gpio82";
293 drive-strength = <8>; /* 8 mA */
294 bias-disable; /* NO PULL */
295 };
296 };
297 };
298
299 sec_aux_pcm_dout {
300 sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep {
301 mux {
302 pins = "gpio83";
303 function = "gpio";
304 };
305
306 config {
307 pins = "gpio83";
308 drive-strength = <2>; /* 2 mA */
309 bias-pull-down; /* PULL DOWN */
310 input-enable;
311 };
312 };
313
314 sec_aux_pcm_dout_active: sec_aux_pcm_dout_active {
315 mux {
316 pins = "gpio83";
317 function = "sec_mi2s";
318 };
319
320 config {
321 pins = "gpio83";
322 drive-strength = <8>; /* 8 mA */
323 bias-disable; /* NO PULL */
324 };
325 };
326 };
327
328 tert_aux_pcm {
329 tert_aux_pcm_sleep: tert_aux_pcm_sleep {
330 mux {
331 pins = "gpio75", "gpio76";
332 function = "gpio";
333 };
334
335 config {
336 pins = "gpio75", "gpio76";
337 drive-strength = <2>; /* 2 mA */
338 bias-pull-down; /* PULL DOWN */
339 input-enable;
340 };
341 };
342
343 tert_aux_pcm_active: tert_aux_pcm_active {
344 mux {
345 pins = "gpio75", "gpio76";
346 function = "ter_mi2s";
347 };
348
349 config {
350 pins = "gpio75", "gpio76";
351 drive-strength = <8>; /* 8 mA */
352 bias-disable; /* NO PULL */
353 output-high;
354 };
355 };
356 };
357
358 tert_aux_pcm_din {
359 tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
360 mux {
361 pins = "gpio77";
362 function = "gpio";
363 };
364
365 config {
366 pins = "gpio77";
367 drive-strength = <2>; /* 2 mA */
368 bias-pull-down; /* PULL DOWN */
369 input-enable;
370 };
371 };
372
373 tert_aux_pcm_din_active: tert_aux_pcm_din_active {
374 mux {
375 pins = "gpio77";
376 function = "ter_mi2s";
377 };
378
379 config {
380 pins = "gpio77";
381 drive-strength = <8>; /* 8 mA */
382 bias-disable; /* NO PULL */
383 };
384 };
385 };
386
387 tert_aux_pcm_dout {
388 tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep {
389 mux {
390 pins = "gpio78";
391 function = "gpio";
392 };
393
394 config {
395 pins = "gpio78";
396 drive-strength = <2>; /* 2 mA */
397 bias-pull-down; /* PULL DOWN */
398 input-enable;
399 };
400 };
401
402 tert_aux_pcm_dout_active: tert_aux_pcm_dout_active {
403 mux {
404 pins = "gpio78";
405 function = "ter_mi2s";
406 };
407
408 config {
409 pins = "gpio78";
410 drive-strength = <8>; /* 8 mA */
411 bias-disable; /* NO PULL */
412 };
413 };
414 };
415
416 quat_aux_pcm {
417 quat_aux_pcm_sleep: quat_aux_pcm_sleep {
418 mux {
419 pins = "gpio58", "gpio59";
420 function = "gpio";
421 };
422
423 config {
424 pins = "gpio58", "gpio59";
425 drive-strength = <2>; /* 2 mA */
426 bias-pull-down; /* PULL DOWN */
427 input-enable;
428 };
429 };
430
431 quat_aux_pcm_active: quat_aux_pcm_active {
432 mux {
433 pins = "gpio58", "gpio59";
434 function = "qua_mi2s";
435 };
436
437 config {
438 pins = "gpio58", "gpio59";
439 drive-strength = <8>; /* 8 mA */
440 bias-disable; /* NO PULL */
441 output-high;
442 };
443 };
444 };
445
446 quat_aux_pcm_din {
447 quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep {
448 mux {
449 pins = "gpio60";
450 function = "gpio";
451 };
452
453 config {
454 pins = "gpio60";
455 drive-strength = <2>; /* 2 mA */
456 bias-pull-down; /* PULL DOWN */
457 input-enable;
458 };
459 };
460
461 quat_aux_pcm_din_active: quat_aux_pcm_din_active {
462 mux {
463 pins = "gpio60";
464 function = "qua_mi2s";
465 };
466
467 config {
468 pins = "gpio60";
469 drive-strength = <8>; /* 8 mA */
470 bias-disable; /* NO PULL */
471 };
472 };
473 };
474
475 quat_aux_pcm_dout {
476 quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep {
477 mux {
478 pins = "gpio61";
479 function = "gpio";
480 };
481
482 config {
483 pins = "gpio61";
484 drive-strength = <2>; /* 2 mA */
485 bias-pull-down; /* PULL DOWN */
486 input-enable;
487 };
488 };
489
490 quat_aux_pcm_dout_active: quat_aux_pcm_dout_active {
491 mux {
492 pins = "gpio61";
493 function = "qua_mi2s";
494 };
495
496 config {
497 pins = "gpio61";
498 drive-strength = <8>; /* 8 mA */
499 bias-disable; /* NO PULL */
500 };
501 };
502 };
503
504 pri_mi2s_mclk {
505 pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep {
506 mux {
507 pins = "gpio64";
508 function = "gpio";
509 };
510
511 config {
512 pins = "gpio64";
513 drive-strength = <2>; /* 2 mA */
514 bias-pull-down; /* PULL DOWN */
515 input-enable;
516 };
517 };
518
519 pri_mi2s_mclk_active: pri_mi2s_mclk_active {
520 mux {
521 pins = "gpio64";
522 function = "pri_mi2s";
523 };
524
525 config {
526 pins = "gpio64";
527 drive-strength = <8>; /* 8 mA */
528 bias-disable; /* NO PULL */
529 output-high;
530 };
531 };
532 };
533
534 pri_mi2s_sck {
535 pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
536 mux {
537 pins = "gpio65";
538 function = "gpio";
539 };
540
541 config {
542 pins = "gpio65";
543 drive-strength = <2>; /* 2 mA */
544 bias-pull-down; /* PULL DOWN */
545 input-enable;
546 };
547 };
548
549 pri_mi2s_sck_active: pri_mi2s_sck_active {
550 mux {
551 pins = "gpio65";
552 function = "pri_mi2s";
553 };
554
555 config {
556 pins = "gpio65";
557 drive-strength = <8>; /* 8 mA */
558 bias-disable; /* NO PULL */
559 output-high;
560 };
561 };
562 };
563
564 pri_mi2s_ws {
565 pri_mi2s_ws_sleep: pri_mi2s_ws_sleep {
566 mux {
567 pins = "gpio66";
568 function = "gpio";
569 };
570
571 config {
572 pins = "gpio66";
573 drive-strength = <2>; /* 2 mA */
574 bias-pull-down; /* PULL DOWN */
575 input-enable;
576 };
577 };
578
579 pri_mi2s_ws_active: pri_mi2s_ws_active {
580 mux {
581 pins = "gpio66";
582 function = "pri_mi2s_ws";
583 };
584
585 config {
586 pins = "gpio66";
587 drive-strength = <8>; /* 8 mA */
588 bias-disable; /* NO PULL */
589 output-high;
590 };
591 };
592 };
593
594 pri_mi2s_sd0 {
595 pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
596 mux {
597 pins = "gpio67";
598 function = "gpio";
599 };
600
601 config {
602 pins = "gpio67";
603 drive-strength = <2>; /* 2 mA */
604 bias-pull-down; /* PULL DOWN */
605 input-enable;
606 };
607 };
608
609 pri_mi2s_sd0_active: pri_mi2s_sd0_active {
610 mux {
611 pins = "gpio67";
612 function = "pri_mi2s";
613 };
614
615 config {
616 pins = "gpio67";
617 drive-strength = <8>; /* 8 mA */
618 bias-disable; /* NO PULL */
619 };
620 };
621 };
622
623 pri_mi2s_sd1 {
624 pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
625 mux {
626 pins = "gpio68";
627 function = "gpio";
628 };
629
630 config {
631 pins = "gpio68";
632 drive-strength = <2>; /* 2 mA */
633 bias-pull-down; /* PULL DOWN */
634 input-enable;
635 };
636 };
637
638 pri_mi2s_sd1_active: pri_mi2s_sd1_active {
639 mux {
640 pins = "gpio68";
641 function = "pri_mi2s";
642 };
643
644 config {
645 pins = "gpio68";
646 drive-strength = <8>; /* 8 mA */
647 bias-disable; /* NO PULL */
648 };
649 };
650 };
651
652 sec_mi2s_mclk {
653 sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep {
654 mux {
655 pins = "gpio79";
656 function = "gpio";
657 };
658
659 config {
660 pins = "gpio79";
661 drive-strength = <2>; /* 2 mA */
662 bias-pull-down; /* PULL DOWN */
663 input-enable;
664 };
665 };
666
667 sec_mi2s_mclk_active: sec_mi2s_mclk_active {
668 mux {
669 pins = "gpio79";
670 function = "sec_mi2s";
671 };
672
673 config {
674 pins = "gpio79";
675 drive-strength = <8>; /* 8 mA */
676 bias-disable; /* NO PULL */
677 };
678 };
679 };
680
681 sec_mi2s {
682 sec_mi2s_sleep: sec_mi2s_sleep {
683 mux {
684 pins = "gpio80", "gpio81";
685 function = "gpio";
686 };
687
688 config {
689 pins = "gpio80", "gpio81";
690 drive-strength = <2>; /* 2 mA */
691 bias-disable; /* NO PULL */
692 input-enable;
693 };
694 };
695
696 sec_mi2s_active: sec_mi2s_active {
697 mux {
698 pins = "gpio80", "gpio81";
699 function = "sec_mi2s";
700 };
701
702 config {
703 pins = "gpio80", "gpio81";
704 drive-strength = <8>; /* 8 mA */
705 bias-disable; /* NO PULL */
706 };
707 };
708 };
709
710 sec_mi2s_sd0 {
711 sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep {
712 mux {
713 pins = "gpio82";
714 function = "gpio";
715 };
716
717 config {
718 pins = "gpio82";
719 drive-strength = <2>; /* 2 mA */
720 bias-pull-down; /* PULL DOWN */
721 input-enable;
722 };
723 };
724
725 sec_mi2s_sd0_active: sec_mi2s_sd0_active {
726 mux {
727 pins = "gpio82";
728 function = "sec_mi2s";
729 };
730
731 config {
732 pins = "gpio82";
733 drive-strength = <8>; /* 8 mA */
734 bias-disable; /* NO PULL */
735 };
736 };
737 };
738
739 sec_mi2s_sd1 {
740 sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
741 mux {
742 pins = "gpio83";
743 function = "gpio";
744 };
745
746 config {
747 pins = "gpio83";
748 drive-strength = <2>; /* 2 mA */
749 bias-pull-down; /* PULL DOWN */
750 input-enable;
751 };
752 };
753
754 sec_mi2s_sd1_active: sec_mi2s_sd1_active {
755 mux {
756 pins = "gpio83";
757 function = "sec_mi2s";
758 };
759
760 config {
761 pins = "gpio83";
762 drive-strength = <8>; /* 8 mA */
763 bias-disable; /* NO PULL */
764 };
765 };
766 };
767
768 tert_mi2s_mclk {
769 tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep {
770 mux {
771 pins = "gpio74";
772 function = "gpio";
773 };
774
775 config {
776 pins = "gpio74";
777 drive-strength = <2>; /* 2 mA */
778 bias-pull-down; /* PULL DOWN */
779 input-enable;
780 };
781 };
782
783 tert_mi2s_mclk_active: tert_mi2s_mclk_active {
784 mux {
785 pins = "gpio74";
786 function = "ter_mi2s";
787 };
788
789 config {
790 pins = "gpio74";
791 drive-strength = <8>; /* 8 mA */
792 bias-disable; /* NO PULL */
793 };
794 };
795 };
796
797 tert_mi2s {
798 tert_mi2s_sleep: tert_mi2s_sleep {
799 mux {
800 pins = "gpio75", "gpio76";
801 function = "gpio";
802 };
803
804 config {
805 pins = "gpio75", "gpio76";
806 drive-strength = <2>; /* 2 mA */
807 bias-pull-down; /* PULL DOWN */
808 input-enable;
809 };
810 };
811
812 tert_mi2s_active: tert_mi2s_active {
813 mux {
814 pins = "gpio75", "gpio76";
815 function = "ter_mi2s";
816 };
817
818 config {
819 pins = "gpio75", "gpio76";
820 drive-strength = <8>; /* 8 mA */
821 bias-disable; /* NO PULL */
822 output-high;
823 };
824 };
825 };
826
827 tert_mi2s_sd0 {
828 tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
829 mux {
830 pins = "gpio77";
831 function = "gpio";
832 };
833
834 config {
835 pins = "gpio77";
836 drive-strength = <2>; /* 2 mA */
837 bias-pull-down; /* PULL DOWN */
838 input-enable;
839 };
840 };
841
842 tert_mi2s_sd0_active: tert_mi2s_sd0_active {
843 mux {
844 pins = "gpio77";
845 function = "ter_mi2s";
846 };
847
848 config {
849 pins = "gpio77";
850 drive-strength = <8>; /* 8 mA */
851 bias-disable; /* NO PULL */
852 };
853 };
854 };
855
856 tert_mi2s_sd1 {
857 tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep {
858 mux {
859 pins = "gpio78";
860 function = "gpio";
861 };
862
863 config {
864 pins = "gpio78";
865 drive-strength = <2>; /* 2 mA */
866 bias-pull-down; /* PULL DOWN */
867 input-enable;
868 };
869 };
870
871 tert_mi2s_sd1_active: tert_mi2s_sd1_active {
872 mux {
873 pins = "gpio78";
874 function = "ter_mi2s";
875 };
876
877 config {
878 pins = "gpio78";
879 drive-strength = <8>; /* 8 mA */
880 bias-disable; /* NO PULL */
881 };
882 };
883 };
884
885 quat_mi2s_mclk {
886 quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep {
887 mux {
888 pins = "gpio57";
889 function = "gpio";
890 };
891
892 config {
893 pins = "gpio57";
894 drive-strength = <2>; /* 2 mA */
895 bias-pull-down; /* PULL DOWN */
896 input-enable;
897 };
898 };
899
900 quat_mi2s_mclk_active: quat_mi2s_mclk_active {
901 mux {
902 pins = "gpio57";
903 function = "qua_mi2s";
904 };
905
906 config {
907 pins = "gpio57";
908 drive-strength = <8>; /* 8 mA */
909 bias-disable; /* NO PULL */
910 };
911 };
912 };
913
914 quat_mi2s {
915 quat_mi2s_sleep: quat_mi2s_sleep {
916 mux {
917 pins = "gpio58", "gpio59";
918 function = "gpio";
919 };
920
921 config {
922 pins = "gpio58", "gpio59";
923 drive-strength = <2>; /* 2 mA */
924 bias-pull-down; /* PULL DOWN */
925 input-enable;
926 };
927 };
928
929 quat_mi2s_active: quat_mi2s_active {
930 mux {
931 pins = "gpio58", "gpio59";
932 function = "qua_mi2s";
933 };
934
935 config {
936 pins = "gpio58", "gpio59";
937 drive-strength = <8>; /* 8 mA */
938 bias-disable; /* NO PULL */
939 output-high;
940 };
941 };
942 };
943
944 quat_mi2s_sd0 {
945 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
946 mux {
947 pins = "gpio60";
948 function = "gpio";
949 };
950
951 config {
952 pins = "gpio60";
953 drive-strength = <2>; /* 2 mA */
954 bias-pull-down; /* PULL DOWN */
955 input-enable;
956 };
957 };
958
959 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
960 mux {
961 pins = "gpio60";
962 function = "qua_mi2s";
963 };
964
965 config {
966 pins = "gpio60";
967 drive-strength = <8>; /* 8 mA */
968 bias-disable; /* NO PULL */
969 };
970 };
971 };
972
973 quat_mi2s_sd1 {
974 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
975 mux {
976 pins = "gpio61";
977 function = "gpio";
978 };
979
980 config {
981 pins = "gpio61";
982 drive-strength = <2>; /* 2 mA */
983 bias-pull-down; /* PULL DOWN */
984 input-enable;
985 };
986 };
987
988 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
989 mux {
990 pins = "gpio61";
991 function = "qua_mi2s";
992 };
993
994 config {
995 pins = "gpio61";
996 drive-strength = <8>; /* 8 mA */
997 bias-disable; /* NO PULL */
998 };
999 };
1000 };
1001
1002 quat_mi2s_sd2 {
1003 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
1004 mux {
1005 pins = "gpio62";
1006 function = "gpio";
1007 };
1008
1009 config {
1010 pins = "gpio62";
1011 drive-strength = <2>; /* 2 mA */
1012 bias-pull-down; /* PULL DOWN */
1013 input-enable;
1014 };
1015 };
1016
1017 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
1018 mux {
1019 pins = "gpio62";
1020 function = "qua_mi2s";
1021 };
1022
1023 config {
1024 pins = "gpio62";
1025 drive-strength = <8>; /* 8 mA */
1026 bias-disable; /* NO PULL */
1027 };
1028 };
1029 };
1030
1031 quat_mi2s_sd3 {
1032 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
1033 mux {
1034 pins = "gpio63";
1035 function = "gpio";
1036 };
1037
1038 config {
1039 pins = "gpio63";
1040 drive-strength = <2>; /* 2 mA */
1041 bias-pull-down; /* PULL DOWN */
1042 input-enable;
1043 };
1044 };
1045
1046 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
1047 mux {
1048 pins = "gpio63";
1049 function = "qua_mi2s";
1050 };
1051
1052 config {
1053 pins = "gpio63";
1054 drive-strength = <8>; /* 8 mA */
1055 bias-disable; /* NO PULL */
1056 };
1057 };
1058 };
Kyle Yan679cbee2016-07-27 16:55:20 -0700[diff] [blame]1059 };
1060};