Vladimir Barinov | 83f5322 | 2007-07-10 13:10:04 +0100 | [diff] [blame] | 1 | /* |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 2 | * Utility to set the DAVINCI MUX register from a table in mux.h |
Vladimir Barinov | 83f5322 | 2007-07-10 13:10:04 +0100 | [diff] [blame] | 3 | * |
| 4 | * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> |
| 5 | * |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 6 | * Based on linux/arch/arm/plat-omap/mux.c: |
| 7 | * Copyright (C) 2003 - 2005 Nokia Corporation |
| 8 | * |
| 9 | * Written by Tony Lindgren |
| 10 | * |
Vladimir Barinov | 83f5322 | 2007-07-10 13:10:04 +0100 | [diff] [blame] | 11 | * 2007 (c) MontaVista Software, Inc. This file is licensed under |
| 12 | * the terms of the GNU General Public License version 2. This program |
| 13 | * is licensed "as is" without any warranty of any kind, whether express |
| 14 | * or implied. |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 15 | * |
| 16 | * Copyright (C) 2008 Texas Instruments. |
Vladimir Barinov | 83f5322 | 2007-07-10 13:10:04 +0100 | [diff] [blame] | 17 | */ |
| 18 | #include <linux/io.h> |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 19 | #include <linux/module.h> |
Vladimir Barinov | 83f5322 | 2007-07-10 13:10:04 +0100 | [diff] [blame] | 20 | #include <linux/spinlock.h> |
| 21 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 22 | #include <mach/mux.h> |
Mark A. Greer | 0e58595 | 2009-04-15 12:39:48 -0700 | [diff] [blame] | 23 | #include <mach/common.h> |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 24 | |
Cyril Chemparathy | 779b0d5 | 2010-05-07 17:06:38 -0400 | [diff] [blame] | 25 | static void __iomem *pinmux_base; |
| 26 | |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 27 | /* |
| 28 | * Sets the DAVINCI MUX register based on the table |
| 29 | */ |
| 30 | int __init_or_module davinci_cfg_reg(const unsigned long index) |
| 31 | { |
| 32 | static DEFINE_SPINLOCK(mux_spin_lock); |
Mark A. Greer | 0e58595 | 2009-04-15 12:39:48 -0700 | [diff] [blame] | 33 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 34 | unsigned long flags; |
| 35 | const struct mux_config *cfg; |
| 36 | unsigned int reg_orig = 0, reg = 0; |
| 37 | unsigned int mask, warn = 0; |
| 38 | |
Cyril Chemparathy | 779b0d5 | 2010-05-07 17:06:38 -0400 | [diff] [blame] | 39 | if (WARN_ON(!soc_info->pinmux_pins)) |
| 40 | return -ENODEV; |
| 41 | |
| 42 | if (!pinmux_base) { |
| 43 | pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K); |
| 44 | if (WARN_ON(!pinmux_base)) |
| 45 | return -ENOMEM; |
| 46 | } |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 47 | |
Mark A. Greer | 0e58595 | 2009-04-15 12:39:48 -0700 | [diff] [blame] | 48 | if (index >= soc_info->pinmux_pins_num) { |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 49 | printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", |
Mark A. Greer | 0e58595 | 2009-04-15 12:39:48 -0700 | [diff] [blame] | 50 | index, soc_info->pinmux_pins_num); |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 51 | dump_stack(); |
| 52 | return -ENODEV; |
Vladimir Barinov | 83f5322 | 2007-07-10 13:10:04 +0100 | [diff] [blame] | 53 | } |
| 54 | |
Mark A. Greer | 0e58595 | 2009-04-15 12:39:48 -0700 | [diff] [blame] | 55 | cfg = &soc_info->pinmux_pins[index]; |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 56 | |
| 57 | if (cfg->name == NULL) { |
| 58 | printk(KERN_ERR "No entry for the specified index\n"); |
| 59 | return -ENODEV; |
| 60 | } |
| 61 | |
| 62 | /* Update the mux register in question */ |
| 63 | if (cfg->mask) { |
| 64 | unsigned tmp1, tmp2; |
| 65 | |
| 66 | spin_lock_irqsave(&mux_spin_lock, flags); |
Cyril Chemparathy | 779b0d5 | 2010-05-07 17:06:38 -0400 | [diff] [blame] | 67 | reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 68 | |
| 69 | mask = (cfg->mask << cfg->mask_offset); |
| 70 | tmp1 = reg_orig & mask; |
| 71 | reg = reg_orig & ~mask; |
| 72 | |
| 73 | tmp2 = (cfg->mode << cfg->mask_offset); |
| 74 | reg |= tmp2; |
| 75 | |
| 76 | if (tmp1 != tmp2) |
| 77 | warn = 1; |
| 78 | |
Cyril Chemparathy | 779b0d5 | 2010-05-07 17:06:38 -0400 | [diff] [blame] | 79 | __raw_writel(reg, pinmux_base + cfg->mux_reg); |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 80 | spin_unlock_irqrestore(&mux_spin_lock, flags); |
| 81 | } |
| 82 | |
| 83 | if (warn) { |
| 84 | #ifdef CONFIG_DAVINCI_MUX_WARNINGS |
| 85 | printk(KERN_WARNING "MUX: initialized %s\n", cfg->name); |
| 86 | #endif |
| 87 | } |
| 88 | |
| 89 | #ifdef CONFIG_DAVINCI_MUX_DEBUG |
| 90 | if (cfg->debug || warn) { |
| 91 | printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name); |
| 92 | printk(KERN_WARNING " %s (0x%08x) = 0x%08x -> 0x%08x\n", |
| 93 | cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); |
| 94 | } |
| 95 | #endif |
| 96 | |
| 97 | return 0; |
Vladimir Barinov | 83f5322 | 2007-07-10 13:10:04 +0100 | [diff] [blame] | 98 | } |
Kevin Hilman | 5526b3f | 2009-04-14 09:50:37 -0500 | [diff] [blame] | 99 | EXPORT_SYMBOL(davinci_cfg_reg); |
Sudhakar Rajashekhara | c96b56c | 2009-07-16 05:45:32 -0400 | [diff] [blame] | 100 | |
Cyril Chemparathy | 3821d10 | 2010-03-25 17:43:48 -0400 | [diff] [blame] | 101 | int __init_or_module davinci_cfg_reg_list(const short pins[]) |
Sudhakar Rajashekhara | c96b56c | 2009-07-16 05:45:32 -0400 | [diff] [blame] | 102 | { |
| 103 | int i, error = -EINVAL; |
| 104 | |
| 105 | if (pins) |
| 106 | for (i = 0; pins[i] >= 0; i++) { |
| 107 | error = davinci_cfg_reg(pins[i]); |
| 108 | if (error) |
| 109 | break; |
| 110 | } |
| 111 | |
| 112 | return error; |
| 113 | } |