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gerrit-public.fairphone.software / kernel / msm-4.9 / f7c92d2cc2beb3367f244480300eaecdd9502932 / . / drivers / staging / rtl8723au / hal / odm.c
blob: 584a74ed2943e5d080f7831626cdccdaf94f674d [file] [log] [blame]
Larry Fingerf7c92d22014-03-28 21:37:39 -0500[diff] [blame^]1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15
16#include "odm_precomp.h"
17
18static const u16 dB_Invert_Table[8][12] = {
19 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
20 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
21 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
22 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
23 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
24 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
25 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
26 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
27};
28
29static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { /* UL DL */
30 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
31 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */
32 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */
33 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */
34 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */
35 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */
36 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */
37 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */
38 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP => 92U AP */
39 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */
40};
41
42/* EDCA Paramter for AP/ADSL by Mingzhi 2011-11-22 */
43
44/* Global var */
45u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D] = {
46 0x7f8001fe, /* 0, +6.0dB */
47 0x788001e2, /* 1, +5.5dB */
48 0x71c001c7, /* 2, +5.0dB */
49 0x6b8001ae, /* 3, +4.5dB */
50 0x65400195, /* 4, +4.0dB */
51 0x5fc0017f, /* 5, +3.5dB */
52 0x5a400169, /* 6, +3.0dB */
53 0x55400155, /* 7, +2.5dB */
54 0x50800142, /* 8, +2.0dB */
55 0x4c000130, /* 9, +1.5dB */
56 0x47c0011f, /* 10, +1.0dB */
57 0x43c0010f, /* 11, +0.5dB */
58 0x40000100, /* 12, +0dB */
59 0x3c8000f2, /* 13, -0.5dB */
60 0x390000e4, /* 14, -1.0dB */
61 0x35c000d7, /* 15, -1.5dB */
62 0x32c000cb, /* 16, -2.0dB */
63 0x300000c0, /* 17, -2.5dB */
64 0x2d4000b5, /* 18, -3.0dB */
65 0x2ac000ab, /* 19, -3.5dB */
66 0x288000a2, /* 20, -4.0dB */
67 0x26000098, /* 21, -4.5dB */
68 0x24000090, /* 22, -5.0dB */
69 0x22000088, /* 23, -5.5dB */
70 0x20000080, /* 24, -6.0dB */
71 0x1e400079, /* 25, -6.5dB */
72 0x1c800072, /* 26, -7.0dB */
73 0x1b00006c, /* 27. -7.5dB */
74 0x19800066, /* 28, -8.0dB */
75 0x18000060, /* 29, -8.5dB */
76 0x16c0005b, /* 30, -9.0dB */
77 0x15800056, /* 31, -9.5dB */
78 0x14400051, /* 32, -10.0dB */
79 0x1300004c, /* 33, -10.5dB */
80 0x12000048, /* 34, -11.0dB */
81 0x11000044, /* 35, -11.5dB */
82 0x10000040, /* 36, -12.0dB */
83 0x0f00003c,/* 37, -12.5dB */
84 0x0e400039,/* 38, -13.0dB */
85 0x0d800036,/* 39, -13.5dB */
86 0x0cc00033,/* 40, -14.0dB */
87 0x0c000030,/* 41, -14.5dB */
88 0x0b40002d,/* 42, -15.0dB */
89};
90
91u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8] = {
92 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
93 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
94 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
95 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
96 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
97 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
98 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
99 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
100 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
101 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
102 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
103 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
104 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
105 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
106 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
107 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
108 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
109 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
110 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
111 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
112 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
113 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
114 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
115 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
116 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
117 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
118 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
119 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
120 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
121 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
122 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
123 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
124 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
125};
126
127u8 CCKSwingTable_Ch1423A[CCK_TABLE_SIZE][8] = {
128 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
129 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
130 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
131 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
132 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
133 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
134 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
135 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
136 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
137 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
138 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
139 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
140 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
141 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
142 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
143 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
144 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
145 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
146 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
147 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
148 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
149 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
150 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
151 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
152 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
153 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
154 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
155 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
156 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
157 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
158 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
159 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
160 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
161};
162
163/* Local Function predefine. */
164
165/* START------------COMMON INFO RELATED--------------- */
166void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm);
167
168void odm_CommonInfoSelfUpdate23a(struct dm_odm_t *pDM_Odm);
169
170void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm);
171
172void odm_CmnInfoHook_Debug23a(struct dm_odm_t *pDM_Odm);
173
174void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm);
175
176/* START---------------DIG--------------------------- */
177void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm);
178
179void odm_DIG23aInit(struct dm_odm_t *pDM_Odm);
180
181void odm_DIG23a(struct dm_odm_t *pDM_Odm);
182
183void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm);
184/* END---------------DIG--------------------------- */
185
186/* START-------BB POWER SAVE----------------------- */
187void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm);
188
189void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm);
190
191void odm_1R_CCA23a(struct dm_odm_t *pDM_Odm);
192/* END---------BB POWER SAVE----------------------- */
193
194void odm_RefreshRateAdaptiveMask23aMP23a(struct dm_odm_t *pDM_Odm);
195
196void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm);
197
198void odm_RefreshRateAdaptiveMask23aAPADSL23a(struct dm_odm_t *pDM_Odm);
199
200void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm);
201
202void odm_DynamicTxPower23aRestorePowerIndex(struct dm_odm_t *pDM_Odm);
203
204void odm_DynamicTxPower23aSavePowerIndex(struct dm_odm_t *pDM_Odm);
205
206void odm_DynamicTxPower23aWritePowerIndex(struct dm_odm_t *pDM_Odm,
207 u8 Value);
208
209void odm_DynamicTxPower23a_92C(struct dm_odm_t *pDM_Odm);
210
211void odm_DynamicTxPower23a_92D(struct dm_odm_t *pDM_Odm);
212
213void odm_RSSIMonitorInit(struct dm_odm_t *pDM_Odm);
214
215void odm_RSSIMonitorCheck23aMP(struct dm_odm_t *pDM_Odm);
216
217void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm);
218void odm_RSSIMonitorCheck23aAP(struct dm_odm_t *pDM_Odm);
219
220void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm);
221void odm_DynamicTxPower23a(struct dm_odm_t *pDM_Odm);
222
223void odm_SwAntDivInit(struct dm_odm_t *pDM_Odm);
224
225void odm_SwAntDivInit_NIC(struct dm_odm_t *pDM_Odm);
226
227void odm_SwAntDivChkAntSwitch(struct dm_odm_t *pDM_Odm, u8 Step);
228
229void odm_SwAntDivChkAntSwitchNIC(struct dm_odm_t *pDM_Odm,
230 u8 Step
231 );
232
233void odm_SwAntDivChkAntSwitchCallback23a(unsigned long data);
234
235void odm_GlobalAdapterCheck(void);
236
237void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm);
238
239void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm);
240
241void odm_TXPowerTrackingCheckAP(struct dm_odm_t *pDM_Odm);
242
243void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm);
244
245void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm);
246
247void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm);
248
249void odm_TXPowerTrackingCheckMP(struct dm_odm_t *pDM_Odm);
250
251void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm);
252
253void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm);
254void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm);
255
256void odm_EdcaTurboCheck23aCE23a(struct dm_odm_t *pDM_Odm);
257
258#define RxDefaultAnt1 0x65a9
259#define RxDefaultAnt2 0x569a
260
261void odm_InitHybridAntDiv23a(struct dm_odm_t *pDM_Odm);
262
263bool odm_StaDefAntSel(struct dm_odm_t *pDM_Odm,
264 u32 OFDM_Ant1_Cnt,
265 u32 OFDM_Ant2_Cnt,
266 u32 CCK_Ant1_Cnt,
267 u32 CCK_Ant2_Cnt,
268 u8 *pDefAnt
269 );
270
271void odm_SetRxIdleAnt(struct dm_odm_t *pDM_Odm,
272 u8 Ant,
273 bool bDualPath
274);
275
276void odm_HwAntDiv23a(struct dm_odm_t *pDM_Odm);
277
278/* 3 Export Interface */
279
280/* 2011/09/21 MH Add to describe different team necessary resource allocate?? */
281void ODM23a_DMInit(struct dm_odm_t *pDM_Odm)
282{
283 /* For all IC series */
284 odm_CommonInfoSelfInit23a(pDM_Odm);
285 odm_CmnInfoInit_Debug23a(pDM_Odm);
286 odm_DIG23aInit(pDM_Odm);
287 odm_RateAdaptiveMaskInit23a(pDM_Odm);
288
289 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
290 odm23a_DynBBPSInit(pDM_Odm);
291 odm_DynamicTxPower23aInit(pDM_Odm);
292 odm_TXPowerTrackingInit23a(pDM_Odm);
293 ODM_EdcaTurboInit23a(pDM_Odm);
294 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
295 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
296 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
297 odm_InitHybridAntDiv23a(pDM_Odm);
298 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
299 odm_SwAntDivInit(pDM_Odm);
300 }
301}
302
303/* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
304/* You can not add any dummy function here, be care, you can only use DM structure */
305/* to perform any new ODM_DM. */
306void ODM_DMWatchdog23a(struct dm_odm_t *pDM_Odm)
307{
308 /* 2012.05.03 Luke: For all IC series */
309 odm_GlobalAdapterCheck();
310 odm_CmnInfoHook_Debug23a(pDM_Odm);
311 odm_CmnInfoUpdate_Debug23a(pDM_Odm);
312 odm_CommonInfoSelfUpdate23a(pDM_Odm);
313 odm_FalseAlarmCounterStatistics23a(pDM_Odm);
314 odm_RSSIMonitorCheck23a(pDM_Odm);
315
316 /* 8723A or 8189ES platform */
317 /* NeilChen--2012--08--24-- */
318 /* Fix Leave LPS issue */
319 if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */
320 (pDM_Odm->SupportICType & (ODM_RTL8723A))) {
321 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG23a is in LPS mode\n"));
322 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
323 odm_DIG23abyRSSI_LPS(pDM_Odm);
324 } else {
325 odm_DIG23a(pDM_Odm);
326 }
327
328 odm_CCKPacketDetectionThresh23a(pDM_Odm);
329
330 if (*(pDM_Odm->pbPowerSaving))
331 return;
332
333 odm_RefreshRateAdaptiveMask23a(pDM_Odm);
334
335 odm_DynamicBBPowerSaving23a(pDM_Odm);
336 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
337 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
338 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
339 odm_HwAntDiv23a(pDM_Odm);
340 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
341 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
342
343 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
344 ODM_TXPowerTrackingCheck23a(pDM_Odm);
345 odm_EdcaTurboCheck23a(pDM_Odm);
346 odm_DynamicTxPower23a(pDM_Odm);
347 }
348
349 odm_dtc(pDM_Odm);
350}
351
352/* */
353/* Init /.. Fixed HW value. Only init time. */
354/* */
355void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm,
356 enum odm_cmninfo CmnInfo,
357 u32 Value
358 )
359{
360 /* ODM_RT_TRACE(pDM_Odm,); */
361
362 /* */
363 /* This section is used for init value */
364 /* */
365 switch (CmnInfo) {
366 /* Fixed ODM value. */
367 case ODM_CMNINFO_ABILITY:
368 pDM_Odm->SupportAbility = (u32)Value;
369 break;
370 case ODM_CMNINFO_PLATFORM:
371 break;
372 case ODM_CMNINFO_INTERFACE:
373 pDM_Odm->SupportInterface = (u8)Value;
374 break;
375 case ODM_CMNINFO_MP_TEST_CHIP:
376 pDM_Odm->bIsMPChip = (u8)Value;
377 break;
378 case ODM_CMNINFO_IC_TYPE:
379 pDM_Odm->SupportICType = Value;
380 break;
381 case ODM_CMNINFO_CUT_VER:
382 pDM_Odm->CutVersion = (u8)Value;
383 break;
384 case ODM_CMNINFO_FAB_VER:
385 pDM_Odm->FabVersion = (u8)Value;
386 break;
387 case ODM_CMNINFO_RF_TYPE:
388 pDM_Odm->RFType = (u8)Value;
389 break;
390 case ODM_CMNINFO_RF_ANTENNA_TYPE:
391 pDM_Odm->AntDivType = (u8)Value;
392 break;
393 case ODM_CMNINFO_BOARD_TYPE:
394 pDM_Odm->BoardType = (u8)Value;
395 break;
396 case ODM_CMNINFO_EXT_LNA:
397 pDM_Odm->ExtLNA = (u8)Value;
398 break;
399 case ODM_CMNINFO_EXT_PA:
400 pDM_Odm->ExtPA = (u8)Value;
401 break;
402 case ODM_CMNINFO_EXT_TRSW:
403 pDM_Odm->ExtTRSW = (u8)Value;
404 break;
405 case ODM_CMNINFO_PATCH_ID:
406 pDM_Odm->PatchID = (u8)Value;
407 break;
408 case ODM_CMNINFO_BINHCT_TEST:
409 pDM_Odm->bInHctTest = (bool)Value;
410 break;
411 case ODM_CMNINFO_BWIFI_TEST:
412 pDM_Odm->bWIFITest = (bool)Value;
413 break;
414 case ODM_CMNINFO_SMART_CONCURRENT:
415 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
416 break;
417 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
418 default:
419 /* do nothing */
420 break;
421 }
422
423 /* */
424 /* Tx power tracking BB swing table. */
425 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
426 /* */
427 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */
428 pDM_Odm->BbSwingIdxOfdmCurrent = 12;
429 pDM_Odm->BbSwingFlagOfdm = false;
430
431}
432
433void ODM23a_CmnInfoHook(struct dm_odm_t *pDM_Odm,
434 enum odm_cmninfo CmnInfo,
435 void *pValue
436 )
437{
438 /* Hook call by reference pointer. */
439 switch (CmnInfo) {
440 /* Dynamic call by reference pointer. */
441 case ODM_CMNINFO_MAC_PHY_MODE:
442 pDM_Odm->pMacPhyMode = (u8 *)pValue;
443 break;
444 case ODM_CMNINFO_TX_UNI:
445 pDM_Odm->pNumTxBytesUnicast = (u64 *)pValue;
446 break;
447 case ODM_CMNINFO_RX_UNI:
448 pDM_Odm->pNumRxBytesUnicast = (u64 *)pValue;
449 break;
450 case ODM_CMNINFO_WM_MODE:
451 pDM_Odm->pWirelessMode = (u8 *)pValue;
452 break;
453 case ODM_CMNINFO_BAND:
454 pDM_Odm->pBandType = (u8 *)pValue;
455 break;
456 case ODM_CMNINFO_SEC_CHNL_OFFSET:
457 pDM_Odm->pSecChOffset = (u8 *)pValue;
458 break;
459 case ODM_CMNINFO_SEC_MODE:
460 pDM_Odm->pSecurity = (u8 *)pValue;
461 break;
462 case ODM_CMNINFO_BW:
463 pDM_Odm->pBandWidth = (u8 *)pValue;
464 break;
465 case ODM_CMNINFO_CHNL:
466 pDM_Odm->pChannel = (u8 *)pValue;
467 break;
468 case ODM_CMNINFO_DMSP_GET_VALUE:
469 pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue;
470 break;
471 case ODM_CMNINFO_BUDDY_ADAPTOR:
472 pDM_Odm->pBuddyAdapter = (struct rtw_adapter **)pValue;
473 break;
474 case ODM_CMNINFO_DMSP_IS_MASTER:
475 pDM_Odm->pbMasterOfDMSP = (bool *)pValue;
476 break;
477 case ODM_CMNINFO_SCAN:
478 pDM_Odm->pbScanInProcess = (bool *)pValue;
479 break;
480 case ODM_CMNINFO_POWER_SAVING:
481 pDM_Odm->pbPowerSaving = (bool *)pValue;
482 break;
483 case ODM_CMNINFO_ONE_PATH_CCA:
484 pDM_Odm->pOnePathCCA = (u8 *)pValue;
485 break;
486 case ODM_CMNINFO_DRV_STOP:
487 pDM_Odm->pbDriverStopped = (bool *)pValue;
488 break;
489 case ODM_CMNINFO_PNP_IN:
490 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue;
491 break;
492 case ODM_CMNINFO_INIT_ON:
493 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue;
494 break;
495 case ODM_CMNINFO_ANT_TEST:
496 pDM_Odm->pAntennaTest = (u8 *)pValue;
497 break;
498 case ODM_CMNINFO_NET_CLOSED:
499 pDM_Odm->pbNet_closed = (bool *)pValue;
500 break;
501 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
502 default:
503 /* do nothing */
504 break;
505 }
506}
507
508void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo,
509 u16 Index, void *pValue)
510{
511 /* Hook call by reference pointer. */
512 switch (CmnInfo) {
513 /* Dynamic call by reference pointer. */
514 case ODM_CMNINFO_STA_STATUS:
515 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
516 break;
517 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
518 default:
519 /* do nothing */
520 break;
521 }
522}
523
524/* Update Band/CHannel/.. The values are dynamic but non-per-packet. */
525void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value)
526{
527 /* This init variable may be changed in run time. */
528 switch (CmnInfo) {
529 case ODM_CMNINFO_ABILITY:
530 pDM_Odm->SupportAbility = (u32)Value;
531 break;
532 case ODM_CMNINFO_RF_TYPE:
533 pDM_Odm->RFType = (u8)Value;
534 break;
535 case ODM_CMNINFO_WIFI_DIRECT:
536 pDM_Odm->bWIFI_Direct = (bool)Value;
537 break;
538 case ODM_CMNINFO_WIFI_DISPLAY:
539 pDM_Odm->bWIFI_Display = (bool)Value;
540 break;
541 case ODM_CMNINFO_LINK:
542 pDM_Odm->bLinked = (bool)Value;
543 break;
544 case ODM_CMNINFO_RSSI_MIN:
545 pDM_Odm->RSSI_Min = (u8)Value;
546 break;
547 case ODM_CMNINFO_DBG_COMP:
548 pDM_Odm->DebugComponents = Value;
549 break;
550 case ODM_CMNINFO_DBG_LEVEL:
551 pDM_Odm->DebugLevel = (u32)Value;
552 break;
553 case ODM_CMNINFO_RA_THRESHOLD_HIGH:
554 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
555 break;
556 case ODM_CMNINFO_RA_THRESHOLD_LOW:
557 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
558 break;
559 }
560
561}
562
563void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm
564 )
565{
566 pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT9);
567 pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
568 if (pDM_Odm->SupportICType & (ODM_RTL8723A))
569 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
570
571 ODM_InitDebugSetting23a(pDM_Odm);
572}
573
574void odm_CommonInfoSelfUpdate23a(struct dm_odm_t *pDM_Odm)
575{
576 u8 EntryCnt = 0;
577 u8 i;
578 struct sta_info *pEntry;
579
580 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) {
581 if (*(pDM_Odm->pSecChOffset) == 1)
582 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2;
583 else if (*(pDM_Odm->pSecChOffset) == 2)
584 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2;
585 } else {
586 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
587 }
588
589 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
590 pEntry = pDM_Odm->pODM_StaInfo[i];
591 if (IS_STA_VALID(pEntry))
592 EntryCnt++;
593 }
594 if (EntryCnt == 1)
595 pDM_Odm->bOneEntryOnly = true;
596 else
597 pDM_Odm->bOneEntryOnly = false;
598}
599
600void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm)
601{
602 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug23a ==>\n"));
603 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility = 0x%x\n", pDM_Odm->SupportAbility));
604 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface =%d\n", pDM_Odm->SupportInterface));
605 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType = 0x%x\n", pDM_Odm->SupportICType));
606 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion =%d\n", pDM_Odm->CutVersion));
607 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion =%d\n", pDM_Odm->FabVersion));
608 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType =%d\n", pDM_Odm->RFType));
609 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType =%d\n", pDM_Odm->BoardType));
610 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA =%d\n", pDM_Odm->ExtLNA));
611 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA =%d\n", pDM_Odm->ExtPA));
612 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW =%d\n", pDM_Odm->ExtTRSW));
613 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID =%d\n", pDM_Odm->PatchID));
614 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest =%d\n", pDM_Odm->bInHctTest));
615 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest =%d\n", pDM_Odm->bWIFITest));
616 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent =%d\n", pDM_Odm->bDualMacSmartConcurrent));
617
618}
619
620void odm_CmnInfoHook_Debug23a(struct dm_odm_t *pDM_Odm)
621{
622 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug23a ==>\n"));
623 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast =%llu\n", *(pDM_Odm->pNumTxBytesUnicast)));
624 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast =%llu\n", *(pDM_Odm->pNumRxBytesUnicast)));
625 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode = 0x%x\n", *(pDM_Odm->pWirelessMode)));
626 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset =%d\n", *(pDM_Odm->pSecChOffset)));
627 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity =%d\n", *(pDM_Odm->pSecurity)));
628 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth =%d\n", *(pDM_Odm->pBandWidth)));
629 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel =%d\n", *(pDM_Odm->pChannel)));
630
631 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess =%d\n", *(pDM_Odm->pbScanInProcess)));
632 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving =%d\n", *(pDM_Odm->pbPowerSaving)));
633}
634
635void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm)
636{
637 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug23a ==>\n"));
638 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct =%d\n", pDM_Odm->bWIFI_Direct));
639 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display =%d\n", pDM_Odm->bWIFI_Display));
640 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked =%d\n", pDM_Odm->bLinked));
641 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min =%d\n", pDM_Odm->RSSI_Min));
642}
643
644void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm,
645 u8 CurrentIGI
646 )
647{
648 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
649
650 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A, pDM_Odm) = 0x%x, ODM_BIT(IGI, pDM_Odm) = 0x%x \n",
651 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)));
652
653 if (pDM_DigTable->CurIGValue != CurrentIGI) {
654 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
655 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n", CurrentIGI));
656 pDM_DigTable->CurIGValue = CurrentIGI;
657 }
658 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
659 ("ODM_Write_DIG23a():CurrentIGI = 0x%x \n", CurrentIGI));
660}
661
662/* Need LPS mode for CE platform --2012--08--24--- */
663/* 8723AS/8189ES */
664void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm)
665{
666 struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
667 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
668 u8 RSSI_Lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */
669 u8 bFwCurrentInPSMode = false;
670 u8 CurrentIGI = pDM_Odm->RSSI_Min;
671
672 if (!(pDM_Odm->SupportICType & (ODM_RTL8723A)))
673 return;
674
675 CurrentIGI = CurrentIGI+RSSI_OFFSET_DIG;
676 bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
677
678 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n")); */
679
680 /* Using FW PS mode to make IGI */
681 if (bFwCurrentInPSMode) {
682 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG23a is in LPS mode\n"));
683 /* Adjust by FA in LPS MODE */
684 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
685 CurrentIGI = CurrentIGI+2;
686 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
687 CurrentIGI = CurrentIGI+1;
688 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
689 CurrentIGI = CurrentIGI-1;
690 } else {
691 CurrentIGI = RSSI_Lower;
692 }
693
694 /* Lower bound checking */
695
696 /* RSSI Lower bound check */
697 if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
698 RSSI_Lower = (pDM_Odm->RSSI_Min-10);
699 else
700 RSSI_Lower = DM_DIG_MIN_NIC;
701
702 /* Upper and Lower Bound checking */
703 if (CurrentIGI > DM_DIG_MAX_NIC)
704 CurrentIGI = DM_DIG_MAX_NIC;
705 else if (CurrentIGI < RSSI_Lower)
706 CurrentIGI = RSSI_Lower;
707
708 ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
709
710}
711
712void odm_DIG23aInit(struct dm_odm_t *pDM_Odm)
713{
714 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
715
716 pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
717 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW;
718 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH;
719 pDM_DigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW;
720 pDM_DigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH;
721 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
722 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
723 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
724 } else {
725 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
726 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
727 }
728 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
729 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
730 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
731 pDM_DigTable->PreCCK_CCAThres = 0xFF;
732 pDM_DigTable->CurCCK_CCAThres = 0x83;
733 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
734 pDM_DigTable->LargeFAHit = 0;
735 pDM_DigTable->Recover_cnt = 0;
736 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
737 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
738 pDM_DigTable->bMediaConnect_0 = false;
739 pDM_DigTable->bMediaConnect_1 = false;
740
741 /* To Initialize pDM_Odm->bDMInitialGainEnable == false to avoid DIG error */
742 pDM_Odm->bDMInitialGainEnable = true;
743
744}
745
746void odm_DIG23a(struct dm_odm_t *pDM_Odm)
747{
748
749 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
750 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
751 u8 DIG_Dynamic_MIN;
752 u8 DIG_MaxOfMin;
753 bool FirstConnect, FirstDisConnect;
754 u8 dm_dig_max, dm_dig_min;
755 u8 CurrentIGI = pDM_DigTable->CurIGValue;
756
757 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n"));
758 /* if (!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) */
759 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) {
760 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
761 ("odm_DIG23a() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
762 return;
763 }
764
765 if (*(pDM_Odm->pbScanInProcess)) {
766 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() Return: In Scan Progress \n"));
767 return;
768 }
769
770 /* add by Neil Chen to avoid PSD is processing */
771 if (!pDM_Odm->bDMInitialGainEnable) {
772 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() Return: PSD is Processing \n"));
773 return;
774 }
775
776 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
777 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
778 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
779
780 /* 1 Boundary Decision */
781 if ((pDM_Odm->SupportICType & (ODM_RTL8723A)) &&
782 ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
783 dm_dig_max = DM_DIG_MAX_NIC_HP;
784 dm_dig_min = DM_DIG_MIN_NIC_HP;
785 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
786 } else {
787 dm_dig_max = DM_DIG_MAX_NIC;
788 dm_dig_min = DM_DIG_MIN_NIC;
789 DIG_MaxOfMin = DM_DIG_MAX_AP;
790 }
791
792 if (pDM_Odm->bLinked) {
793 /* 2 8723A Series, offset need to be 10 */
794 if (pDM_Odm->SupportICType == (ODM_RTL8723A)) {
795 /* 2 Upper Bound */
796 if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
797 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
798 else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
799 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
800 else
801 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
802
803 /* 2 If BT is Concurrent, need to set Lower Bound */
804 DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
805 } else {
806 /* 2 Modify DIG upper bound */
807 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
808 pDM_DigTable->rx_gain_range_max = dm_dig_max;
809 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
810 pDM_DigTable->rx_gain_range_max = dm_dig_min;
811 else
812 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
813
814 /* 2 Modify DIG lower bound */
815 if (pDM_Odm->bOneEntryOnly) {
816 if (pDM_Odm->RSSI_Min < dm_dig_min)
817 DIG_Dynamic_MIN = dm_dig_min;
818 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
819 DIG_Dynamic_MIN = DIG_MaxOfMin;
820 else
821 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
822 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
823 ("odm_DIG23a() : bOneEntryOnly = true, DIG_Dynamic_MIN = 0x%x\n",
824 DIG_Dynamic_MIN));
825 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
826 ("odm_DIG23a() : pDM_Odm->RSSI_Min =%d\n",
827 pDM_Odm->RSSI_Min));
828 } else {
829 DIG_Dynamic_MIN = dm_dig_min;
830 }
831 }
832 } else {
833 pDM_DigTable->rx_gain_range_max = dm_dig_max;
834 DIG_Dynamic_MIN = dm_dig_min;
835 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() : No Link\n"));
836 }
837
838 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
839 if (pFalseAlmCnt->Cnt_all > 10000) {
840 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
841 ("dm_DIG(): Abnornally false alarm case. \n"));
842
843 if (pDM_DigTable->LargeFAHit != 3)
844 pDM_DigTable->LargeFAHit++;
845 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
846 pDM_DigTable->ForbiddenIGI = CurrentIGI;
847 pDM_DigTable->LargeFAHit = 1;
848 }
849
850 if (pDM_DigTable->LargeFAHit >= 3) {
851 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
852 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
853 else
854 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
855 pDM_DigTable->Recover_cnt = 3600; /* 3600 = 2hr */
856 }
857 } else {
858 /* Recovery mechanism for IGI lower bound */
859 if (pDM_DigTable->Recover_cnt != 0) {
860 pDM_DigTable->Recover_cnt--;
861 } else {
862 if (pDM_DigTable->LargeFAHit < 3) {
863 if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) {
864 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
865 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
866 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
867 ("odm_DIG23a(): Normal Case: At Lower Bound\n"));
868 } else {
869 pDM_DigTable->ForbiddenIGI--;
870 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
871 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
872 ("odm_DIG23a(): Normal Case: Approach Lower Bound\n"));
873 }
874 } else {
875 pDM_DigTable->LargeFAHit = 0;
876 }
877 }
878 }
879 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): pDM_DigTable->LargeFAHit =%d\n", pDM_DigTable->LargeFAHit));
880
881 /* 1 Adjust initial gain by false alarm */
882 if (pDM_Odm->bLinked) {
883 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG AfterLink\n"));
884 if (FirstConnect) {
885 CurrentIGI = pDM_Odm->RSSI_Min;
886 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
887 } else {
888 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
889 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
890 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
891 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
892 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
893 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
894 }
895 } else {
896 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG BeforeLink\n"));
897 if (FirstDisConnect) {
898 CurrentIGI = pDM_DigTable->rx_gain_range_min;
899 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): First DisConnect \n"));
900 } else {
901 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
902 if (pFalseAlmCnt->Cnt_all > 10000)
903 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
904 else if (pFalseAlmCnt->Cnt_all > 8000)
905 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
906 else if (pFalseAlmCnt->Cnt_all < 500)
907 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
908 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): England DIG \n"));
909 }
910 }
911 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG End Adjust IGI\n"));
912 /* 1 Check initial gain by upper/lower bound */
913 if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
914 CurrentIGI = pDM_DigTable->rx_gain_range_max;
915 if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
916 CurrentIGI = pDM_DigTable->rx_gain_range_min;
917
918 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): rx_gain_range_max = 0x%x, rx_gain_range_min = 0x%x\n",
919 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
920 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): TotalFA =%d\n", pFalseAlmCnt->Cnt_all));
921 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): CurIGValue = 0x%x\n", CurrentIGI));
922
923 /* 2 High power RSSI threshold */
924
925 ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
926 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
927 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
928}
929
930/* 3 ============================================================ */
931/* 3 FASLE ALARM CHECK */
932/* 3 ============================================================ */
933
934void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm)
935{
936 u32 ret_value;
937 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
938
939 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
940 return;
941
942 if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
943 /* hold ofdm counter */
944 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */
945 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */
946
947 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
948 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
949 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
950 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
951 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
952 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
953 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
954 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
955 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
956 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
957 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
958
959 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail +
960 FalseAlmCnt->Cnt_Rate_Illegal +
961 FalseAlmCnt->Cnt_Crc8_fail +
962 FalseAlmCnt->Cnt_Mcs_fail +
963 FalseAlmCnt->Cnt_Fast_Fsync +
964 FalseAlmCnt->Cnt_SB_Search_fail;
965 /* hold cck counter */
966 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
967 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1);
968
969 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
970 FalseAlmCnt->Cnt_Cck_fail = ret_value;
971 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
972 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff) << 8;
973
974 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
975 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
976
977 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
978 FalseAlmCnt->Cnt_SB_Search_fail +
979 FalseAlmCnt->Cnt_Parity_Fail +
980 FalseAlmCnt->Cnt_Rate_Illegal +
981 FalseAlmCnt->Cnt_Crc8_fail +
982 FalseAlmCnt->Cnt_Mcs_fail +
983 FalseAlmCnt->Cnt_Cck_fail);
984
985 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
986
987 if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
988 /* reset false alarm counter registers */
989 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1);
990 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0);
991 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1);
992 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0);
993 /* update ofdm counter */
994 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); /* update page C counter */
995 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); /* update page D counter */
996
997 /* reset CCK CCA counter */
998 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0);
999 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2);
1000 /* reset CCK FA counter */
1001 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0);
1002 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2);
1003 }
1004
1005 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics23a\n"));
1006 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Fast_Fsync =%d, Cnt_SB_Search_fail =%d\n",
1007 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail));
1008 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Parity_Fail =%d, Cnt_Rate_Illegal =%d\n",
1009 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal));
1010 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Crc8_fail =%d, Cnt_Mcs_fail =%d\n",
1011 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
1012 } else { /* FOR ODM_IC_11AC_SERIES */
1013 /* read OFDM FA counter */
1014 FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord);
1015 FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord);
1016 FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail;
1017
1018 /* reset OFDM FA coutner */
1019 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1);
1020 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0);
1021 /* reset CCK FA counter */
1022 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0);
1023 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1);
1024 }
1025 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail =%d\n", FalseAlmCnt->Cnt_Cck_fail));
1026 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail =%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
1027 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm =%d\n", FalseAlmCnt->Cnt_all));
1028}
1029
1030/* 3 ============================================================ */
1031/* 3 CCK Packet Detect Threshold */
1032/* 3 ============================================================ */
1033
1034void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm)
1035{
1036 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
1037 u8 CurCCK_CCAThres;
1038
1039 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
1040 return;
1041
1042 if (pDM_Odm->ExtLNA)
1043 return;
1044
1045 if (pDM_Odm->bLinked) {
1046 if (pDM_Odm->RSSI_Min > 25) {
1047 CurCCK_CCAThres = 0xcd;
1048 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
1049 CurCCK_CCAThres = 0x83;
1050 } else {
1051 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
1052 CurCCK_CCAThres = 0x83;
1053 else
1054 CurCCK_CCAThres = 0x40;
1055 }
1056 } else {
1057 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
1058 CurCCK_CCAThres = 0x83;
1059 else
1060 CurCCK_CCAThres = 0x40;
1061 }
1062
1063 ODM_Write_CCK_CCA_Thres23a(pDM_Odm, CurCCK_CCAThres);
1064}
1065
1066void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres)
1067{
1068 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
1069
1070 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres)
1071 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
1072 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
1073 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
1074
1075}
1076
1077/* 3 ============================================================ */
1078/* 3 BB Power Save */
1079/* 3 ============================================================ */
1080void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm)
1081{
1082 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
1083
1084 pDM_PSTable->PreCCAState = CCA_MAX;
1085 pDM_PSTable->CurCCAState = CCA_MAX;
1086 pDM_PSTable->PreRFState = RF_MAX;
1087 pDM_PSTable->CurRFState = RF_MAX;
1088 pDM_PSTable->Rssi_val_min = 0;
1089 pDM_PSTable->initialize = 0;
1090}
1091
1092void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm)
1093{
1094 return;
1095}
1096
1097void odm_1R_CCA23a(struct dm_odm_t *pDM_Odm)
1098{
1099 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
1100
1101 if (pDM_Odm->RSSI_Min != 0xFF) {
1102 if (pDM_PSTable->PreCCAState == CCA_2R) {
1103 if (pDM_Odm->RSSI_Min >= 35)
1104 pDM_PSTable->CurCCAState = CCA_1R;
1105 else
1106 pDM_PSTable->CurCCAState = CCA_2R;
1107 } else {
1108 if (pDM_Odm->RSSI_Min <= 30)
1109 pDM_PSTable->CurCCAState = CCA_2R;
1110 else
1111 pDM_PSTable->CurCCAState = CCA_1R;
1112 }
1113 } else {
1114 pDM_PSTable->CurCCAState = CCA_MAX;
1115 }
1116
1117 if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) {
1118 if (pDM_PSTable->CurCCAState == CCA_1R) {
1119 if (pDM_Odm->RFType == ODM_2T2R)
1120 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x13);
1121 else
1122 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x23);
1123 } else {
1124 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x33);
1125 /* PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x63); */
1126 }
1127 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
1128 }
1129}
1130
1131void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal)
1132{
1133 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
1134 u8 Rssi_Up_bound = 30 ;
1135 u8 Rssi_Low_bound = 25;
1136 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
1137 Rssi_Up_bound = 50 ;
1138 Rssi_Low_bound = 45;
1139 }
1140 if (pDM_PSTable->initialize == 0) {
1141
1142 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
1143 pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
1144 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
1145 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
1146 /* Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); */
1147 pDM_PSTable->initialize = 1;
1148 }
1149
1150 if (!bForceInNormal) {
1151 if (pDM_Odm->RSSI_Min != 0xFF) {
1152 if (pDM_PSTable->PreRFState == RF_Normal) {
1153 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
1154 pDM_PSTable->CurRFState = RF_Save;
1155 else
1156 pDM_PSTable->CurRFState = RF_Normal;
1157 } else {
1158 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
1159 pDM_PSTable->CurRFState = RF_Normal;
1160 else
1161 pDM_PSTable->CurRFState = RF_Save;
1162 }
1163 } else {
1164 pDM_PSTable->CurRFState = RF_MAX;
1165 }
1166 } else {
1167 pDM_PSTable->CurRFState = RF_Normal;
1168 }
1169
1170 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
1171 if (pDM_PSTable->CurRFState == RF_Save) {
1172 /* <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]= 1 when enter BB power saving mode. */
1173 /* Suggested by SD3 Yu-Nan. 2011.01.20. */
1174 if (pDM_Odm->SupportICType == ODM_RTL8723A)
1175 ODM_SetBBReg(pDM_Odm, 0x874, BIT5, 0x1); /* Reg874[5]= 1b'1 */
1176 ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]= 3'b010 */
1177 ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); /* RegC70[3]= 1'b0 */
1178 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]= 0x63 */
1179 ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]= 2'b10 */
1180 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]= 0x3 */
1181 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); /* Reg818[28]= 1'b0 */
1182 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); /* Reg818[28]= 1'b1 */
1183 } else {
1184 ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->Reg874);
1185 ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
1186 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
1187 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
1188 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);
1189
1190 if (pDM_Odm->SupportICType == ODM_RTL8723A)
1191 ODM_SetBBReg(pDM_Odm, 0x874, BIT5, 0x0); /* Reg874[5]= 1b'0 */
1192 }
1193 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
1194 }
1195}
1196
1197/* 3 ============================================================ */
1198/* 3 RATR MASK */
1199/* 3 ============================================================ */
1200/* 3 ============================================================ */
1201/* 3 Rate Adaptive */
1202/* 3 ============================================================ */
1203
1204void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm)
1205{
1206 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
1207
1208 pOdmRA->Type = DM_Type_ByDriver;
1209 if (pOdmRA->Type == DM_Type_ByDriver)
1210 pDM_Odm->bUseRAMask = true;
1211 else
1212 pDM_Odm->bUseRAMask = false;
1213
1214 pOdmRA->RATRState = DM_RATR_STA_INIT;
1215 pOdmRA->HighRSSIThresh = 50;
1216 pOdmRA->LowRSSIThresh = 20;
1217}
1218
1219u32 ODM_Get_Rate_Bitmap23a(struct dm_odm_t *pDM_Odm,
1220 u32 macid,
1221 u32 ra_mask,
1222 u8 rssi_level)
1223{
1224 struct sta_info *pEntry;
1225 u32 rate_bitmap = 0x0fffffff;
1226 u8 WirelessMode;
1227 /* u8 WirelessMode =*(pDM_Odm->pWirelessMode); */
1228
1229 pEntry = pDM_Odm->pODM_StaInfo[macid];
1230 if (!IS_STA_VALID(pEntry))
1231 return ra_mask;
1232
1233 WirelessMode = pEntry->wireless_mode;
1234
1235 switch (WirelessMode) {
1236 case ODM_WM_B:
1237 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */
1238 rate_bitmap = 0x0000000d;
1239 else
1240 rate_bitmap = 0x0000000f;
1241 break;
1242 case (ODM_WM_A|ODM_WM_G):
1243 if (rssi_level == DM_RATR_STA_HIGH)
1244 rate_bitmap = 0x00000f00;
1245 else
1246 rate_bitmap = 0x00000ff0;
1247 break;
1248 case (ODM_WM_B|ODM_WM_G):
1249 if (rssi_level == DM_RATR_STA_HIGH)
1250 rate_bitmap = 0x00000f00;
1251 else if (rssi_level == DM_RATR_STA_MIDDLE)
1252 rate_bitmap = 0x00000ff0;
1253 else
1254 rate_bitmap = 0x00000ff5;
1255 break;
1256 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1257 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1258 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) {
1259 if (rssi_level == DM_RATR_STA_HIGH) {
1260 rate_bitmap = 0x000f0000;
1261 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1262 rate_bitmap = 0x000ff000;
1263 } else {
1264 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
1265 rate_bitmap = 0x000ff015;
1266 else
1267 rate_bitmap = 0x000ff005;
1268 }
1269 } else {
1270 if (rssi_level == DM_RATR_STA_HIGH) {
1271 rate_bitmap = 0x0f8f0000;
1272 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1273 rate_bitmap = 0x0f8ff000;
1274 } else {
1275 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
1276 rate_bitmap = 0x0f8ff015;
1277 else
1278 rate_bitmap = 0x0f8ff005;
1279 }
1280 }
1281 break;
1282 default:
1283 /* case WIRELESS_11_24N: */
1284 /* case WIRELESS_11_5N: */
1285 if (pDM_Odm->RFType == RF_1T2R)
1286 rate_bitmap = 0x000fffff;
1287 else
1288 rate_bitmap = 0x0fffffff;
1289 break;
1290 }
1291
1292 /* printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", __FUNCTION__, rssi_level, WirelessMode, rate_bitmap); */
1293 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", rssi_level, WirelessMode, rate_bitmap));
1294
1295 return rate_bitmap;
1296
1297}
1298
1299/*-----------------------------------------------------------------------------
1300 * Function: odm_RefreshRateAdaptiveMask23a()
1301 *
1302 * Overview: Update rate table mask according to rssi
1303 *
1304 * Input: NONE
1305 *
1306 * Output: NONE
1307 *
1308 * Return: NONE
1309 *
1310 * Revised History:
1311 *When Who Remark
1312 *05/27/2009 hpfan Create Version 0.
1313 *
1314 *---------------------------------------------------------------------------*/
1315void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm)
1316{
1317 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
1318 return;
1319 /* */
1320 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1321 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1322 /* HW dynamic mechanism. */
1323 /* */
1324 odm_RefreshRateAdaptiveMask23aCE23a(pDM_Odm);
1325}
1326
1327void odm_RefreshRateAdaptiveMask23aMP23a(struct dm_odm_t *pDM_Odm)
1328{
1329}
1330
1331void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm)
1332{
1333 u8 i;
1334 struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
1335
1336 if (pAdapter->bDriverStopped) {
1337 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE,
1338 ("<---- odm_RefreshRateAdaptiveMask23a(): driver is going to unload\n"));
1339 return;
1340 }
1341
1342 if (!pDM_Odm->bUseRAMask) {
1343 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1344 ("<---- odm_RefreshRateAdaptiveMask23a(): driver does not control rate adaptive mask\n"));
1345 return;
1346 }
1347
1348 /* printk("==> %s \n", __FUNCTION__); */
1349
1350 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1351 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1352 if (IS_STA_VALID(pstat)) {
1353 if (ODM_RAStateCheck23a(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
1354 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1355 ("RSSI:%d, RSSI_LEVEL:%d\n",
1356 pstat->rssi_stat.UndecoratedSmoothedPWDB,
1357 pstat->rssi_level));
1358 rtw_hal_update_ra_mask23a(pstat, pstat->rssi_level);
1359 }
1360
1361 }
1362 }
1363
1364}
1365
1366void odm_RefreshRateAdaptiveMask23aAPADSL23a(struct dm_odm_t *pDM_Odm)
1367{
1368}
1369
1370/* Return Value: bool */
1371/* - true: RATRState is changed. */
1372bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate,
1373 u8 *pRATRState)
1374{
1375 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1376 const u8 GoUpGap = 5;
1377 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1378 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1379 u8 RATRState;
1380
1381 /* Threshold Adjustment: */
1382 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1383 /* Here GoUpGap is added to solve the boundary's level alternation issue. */
1384 switch (*pRATRState) {
1385 case DM_RATR_STA_INIT:
1386 case DM_RATR_STA_HIGH:
1387 break;
1388 case DM_RATR_STA_MIDDLE:
1389 HighRSSIThreshForRA += GoUpGap;
1390 break;
1391 case DM_RATR_STA_LOW:
1392 HighRSSIThreshForRA += GoUpGap;
1393 LowRSSIThreshForRA += GoUpGap;
1394 break;
1395 default:
1396 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
1397 break;
1398 }
1399
1400 /* Decide RATRState by RSSI. */
1401 if (RSSI > HighRSSIThreshForRA)
1402 RATRState = DM_RATR_STA_HIGH;
1403 else if (RSSI > LowRSSIThreshForRA)
1404 RATRState = DM_RATR_STA_MIDDLE;
1405 else
1406 RATRState = DM_RATR_STA_LOW;
1407
1408 if (*pRATRState != RATRState || bForceUpdate) {
1409 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1410 ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
1411 *pRATRState = RATRState;
1412 return true;
1413 }
1414 return false;
1415}
1416
1417/* 3 ============================================================ */
1418/* 3 Dynamic Tx Power */
1419/* 3 ============================================================ */
1420
1421void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm)
1422{
1423 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1424 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1425 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1426
1427 pdmpriv->bDynamicTxPowerEnable = false;
1428
1429 pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
1430 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1431}
1432
1433void odm_DynamicTxPower23aSavePowerIndex(struct dm_odm_t *pDM_Odm)
1434{
1435 u8 index;
1436 u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
1437
1438 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1439 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1440 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1441 for (index = 0; index < 6; index++)
1442 pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]);
1443}
1444
1445void odm_DynamicTxPower23aRestorePowerIndex(struct dm_odm_t *pDM_Odm)
1446{
1447 u8 index;
1448 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1449
1450 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1451 u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
1452 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1453 for (index = 0; index < 6; index++)
1454 rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
1455}
1456
1457void odm_DynamicTxPower23aWritePowerIndex(struct dm_odm_t *pDM_Odm,
1458 u8 Value)
1459{
1460
1461 u8 index;
1462 u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
1463
1464 for (index = 0; index < 6; index++)
1465 ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
1466
1467}
1468
1469void odm_DynamicTxPower23a(struct dm_odm_t *pDM_Odm)
1470{
1471}
1472
1473void odm_DynamicTxPower23a_92C(struct dm_odm_t *pDM_Odm)
1474{
1475}
1476
1477void odm_DynamicTxPower23a_92D(struct dm_odm_t *pDM_Odm)
1478{
1479}
1480
1481/* 3 ============================================================ */
1482/* 3 RSSI Monitor */
1483/* 3 ============================================================ */
1484
1485void odm_RSSIMonitorInit(struct dm_odm_t *pDM_Odm)
1486{
1487}
1488
1489void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm)
1490{
1491 /* For AP/ADSL use struct rtl8723a_priv * */
1492 /* For CE/NIC use struct rtw_adapter * */
1493
1494 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
1495 return;
1496
1497 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1498 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1499 /* HW dynamic mechanism. */
1500 odm_RSSIMonitorCheck23aCE(pDM_Odm);
1501} /* odm_RSSIMonitorCheck23a */
1502
1503void odm_RSSIMonitorCheck23aMP(struct dm_odm_t *pDM_Odm)
1504{
1505}
1506
1507static void
1508FindMinimumRSSI(
1509 struct rtw_adapter *pAdapter
1510 )
1511{
1512 struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1513 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1514 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1515
1516 /* 1 1.Determine the minimum RSSI */
1517
1518 if ((!pDM_Odm->bLinked) &&
1519 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
1520 pdmpriv->MinUndecoratedPWDBForDM = 0;
1521 else
1522 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1523}
1524
1525void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm)
1526{
1527 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1528 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1529 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1530 int i;
1531 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1532 u8 sta_cnt = 0;
1533 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1534 struct sta_info *psta;
1535
1536 if (!pDM_Odm->bLinked)
1537 return;
1538
1539 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1540 psta = pDM_Odm->pODM_StaInfo[i];
1541 if (IS_STA_VALID(psta)) {
1542 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1543 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1544
1545 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1546 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1547
1548 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1549 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
1550 }
1551 }
1552
1553 for (i = 0; i < sta_cnt; i++) {
1554 if (PWDB_rssi[i] != (0)) {
1555 if (pHalData->fw_ractrl) /* Report every sta's RSSI to FW */
1556 rtl8723a_set_rssi_cmd(Adapter, (u8 *)&PWDB_rssi[i]);
1557 }
1558 }
1559
1560 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */
1561 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1562 else
1563 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1564
1565 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */
1566 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1567 else
1568 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1569
1570 FindMinimumRSSI(Adapter);/* get pdmpriv->MinUndecoratedPWDBForDM */
1571
1572 ODM_CmnInfoUpdate23a(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1573}
1574
1575void odm_RSSIMonitorCheck23aAP(struct dm_odm_t *pDM_Odm)
1576{
1577}
1578
1579void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm)
1580{
1581 setup_timer(&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer,
1582 odm_SwAntDivChkAntSwitchCallback23a, (unsigned long)pDM_Odm);
1583}
1584
1585void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm)
1586{
1587 del_timer_sync(&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
1588}
1589
1590void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm)
1591{
1592 ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
1593}
1594
1595/* endif */
1596/* 3 ============================================================ */
1597/* 3 Tx Power Tracking */
1598/* 3 ============================================================ */
1599
1600void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm)
1601{
1602 odm_TXPowerTrackingThermalMeterInit23a(pDM_Odm);
1603}
1604
1605void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm)
1606{
1607 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1608 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1609 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1610
1611 pdmpriv->bTXPowerTracking = true;
1612 pdmpriv->TXPowercount = 0;
1613 pdmpriv->bTXPowerTrackingInit = false;
1614 pdmpriv->TxPowerTrackControl = true;
1615 MSG_8723A("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
1616
1617 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1618}
1619
1620void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm)
1621{
1622 /* For AP/ADSL use struct rtl8723a_priv * */
1623 /* For CE/NIC use struct rtw_adapter * */
1624
1625 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1626 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1627 /* HW dynamic mechanism. */
1628 odm_TXPowerTrackingCheckCE23a(pDM_Odm);
1629}
1630
1631void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm)
1632{
1633}
1634
1635void odm_TXPowerTrackingCheckMP(struct dm_odm_t *pDM_Odm)
1636{
1637}
1638
1639void odm_TXPowerTrackingCheckAP(struct dm_odm_t *pDM_Odm)
1640{
1641}
1642
1643/* antenna mapping info */
1644/* 1: right-side antenna */
1645/* 2/0: left-side antenna */
1646/* PpDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */
1647/* PpDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */
1648/* We select left antenna as default antenna in initial process, modify it as needed */
1649/* */
1650
1651/* 3 ============================================================ */
1652/* 3 SW Antenna Diversity */
1653/* 3 ============================================================ */
1654void odm_SwAntDivInit(struct dm_odm_t *pDM_Odm)
1655{
1656}
1657
1658void ODM_SwAntDivChkPerPktRssi(struct dm_odm_t *pDM_Odm, u8 StationID, struct odm_phy_info *pPhyInfo)
1659{
1660}
1661
1662void odm_SwAntDivChkAntSwitch(struct dm_odm_t *pDM_Odm, u8 Step)
1663{
1664}
1665
1666void ODM_SwAntDivRestAfterLink(struct dm_odm_t *pDM_Odm)
1667{
1668}
1669
1670void odm_SwAntDivChkAntSwitchCallback23a(unsigned long data)
1671{
1672}
1673
1674/* 3 ============================================================ */
1675/* 3 SW Antenna Diversity */
1676/* 3 ============================================================ */
1677
1678void odm_InitHybridAntDiv23a(struct dm_odm_t *pDM_Odm)
1679{
1680}
1681
1682void odm_HwAntDiv23a(struct dm_odm_t *pDM_Odm)
1683{
1684}
1685
1686/* EDCA Turbo */
1687void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm)
1688{
1689
1690 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1691 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1692 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1693 Adapter->recvpriv.bIsAnyNonBEPkts = false;
1694
1695 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM)));
1696 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM)));
1697 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)));
1698 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM)));
1699
1700} /* ODM_InitEdcaTurbo */
1701
1702void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm)
1703{
1704 /* For AP/ADSL use struct rtl8723a_priv * */
1705 /* For CE/NIC use struct rtw_adapter * */
1706
1707 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1708 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1709 /* HW dynamic mechanism. */
1710 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("odm_EdcaTurboCheck23a ========================>\n"));
1711
1712 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1713 return;
1714
1715 odm_EdcaTurboCheck23aCE23a(pDM_Odm);
1716 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("<======================== odm_EdcaTurboCheck23a\n"));
1717
1718} /* odm_CheckEdcaTurbo */
1719
1720void odm_EdcaTurboCheck23aCE23a(struct dm_odm_t *pDM_Odm)
1721{
1722 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1723
1724 u32 trafficIndex;
1725 u32 edca_param;
1726 u64 cur_tx_bytes = 0;
1727 u64 cur_rx_bytes = 0;
1728 u8 bbtchange = false;
1729 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1730 struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
1731 struct recv_priv *precvpriv = &Adapter->recvpriv;
1732 struct registry_priv *pregpriv = &Adapter->registrypriv;
1733 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1734 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1735
1736 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */
1737 goto dm_CheckEdcaTurbo_EXIT;
1738
1739 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX)
1740 goto dm_CheckEdcaTurbo_EXIT;
1741
1742#ifdef CONFIG_8723AU_BT_COEXIST
1743 if (BT_DisableEDCATurbo(Adapter))
1744 goto dm_CheckEdcaTurbo_EXIT;
1745#endif
1746
1747 /* Check if the status needs to be changed. */
1748 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1749 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1750 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1751
1752 /* traffic, TX or RX */
1753 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1754 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1755 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1756 /* Uplink TP is present. */
1757 trafficIndex = UP_LINK;
1758 } else { /* Balance TP is present. */
1759 trafficIndex = DOWN_LINK;
1760 }
1761 } else {
1762 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1763 /* Downlink TP is present. */
1764 trafficIndex = DOWN_LINK;
1765 } else { /* Balance TP is present. */
1766 trafficIndex = UP_LINK;
1767 }
1768 }
1769
1770 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) ||
1771 (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1772 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) &&
1773 (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1774 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1775 else
1776 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1777 rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
1778
1779 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1780 }
1781
1782 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1783 } else {
1784 /* Turn Off EDCA turbo here. */
1785 /* Restore original EDCA according to the declaration of AP. */
1786 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1787 rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
1788 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1789 }
1790 }
1791
1792dm_CheckEdcaTurbo_EXIT:
1793 /* Set variables for next time. */
1794 precvpriv->bIsAnyNonBEPkts = false;
1795 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1796 precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1797}
1798
1799u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1800{
1801 u32 psd_report;
1802
1803 /* Set DCO frequency index, offset = (40MHz/SamplePts)*point */
1804 ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1805
1806 /* Start PSD calculation, Reg808[22]= 0->1 */
1807 ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1);
1808 /* Need to wait for HW PSD report */
1809 udelay(30);
1810 ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);
1811 /* Read PSD report, Reg8B4[15:0] */
1812 psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1813
1814 psd_report = (u32)(ConvertTo_dB23a(psd_report))+(u32)(initial_gain_psd-0x1c);
1815
1816 return psd_report;
1817}
1818
1819u32
1820ConvertTo_dB23a(
1821 u32 Value)
1822{
1823 u8 i;
1824 u8 j;
1825 u32 dB;
1826
1827 Value = Value & 0xFFFF;
1828
1829 for (i = 0; i < 8; i++) {
1830 if (Value <= dB_Invert_Table[i][11])
1831 break;
1832 }
1833
1834 if (i >= 8)
1835 return 96; /* maximum 96 dB */
1836
1837 for (j = 0; j < 12; j++) {
1838 if (Value <= dB_Invert_Table[i][j])
1839 break;
1840 }
1841
1842 dB = i*12 + j + 1;
1843
1844 return dB;
1845}
1846
1847/* */
1848/* 2011/09/22 MH Add for 92D global spin lock utilization. */
1849/* */
1850void
1851odm_GlobalAdapterCheck(
1852 void
1853 )
1854{
1855} /* odm_GlobalAdapterCheck */
1856
1857/* */
1858/* Description: */
1859/*Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1860/* */
1861/* Added by Joseph, 2012.03.22 */
1862/* */
1863void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm)
1864{
1865 struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1866 pDM_SWAT_Table->ANTA_ON = true;
1867 pDM_SWAT_Table->ANTB_ON = true;
1868}
1869
1870/* 2 8723A ANT DETECT */
1871
1872static void odm_PHY_SaveAFERegisters(
1873 struct dm_odm_t *pDM_Odm,
1874 u32 *AFEReg,
1875 u32 *AFEBackup,
1876 u32 RegisterNum
1877 )
1878{
1879 u32 i;
1880
1881 /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
1882 for (i = 0 ; i < RegisterNum ; i++)
1883 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1884}
1885
1886static void odm_PHY_ReloadAFERegisters(struct dm_odm_t *pDM_Odm, u32 *AFEReg,
1887 u32 *AFEBackup, u32 RegiesterNum)
1888{
1889 u32 i;
1890
1891 for (i = 0 ; i < RegiesterNum; i++)
1892 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1893}
1894
1895/* 2 8723A ANT DETECT */
1896/* Description: */
1897/* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1898/* This function is cooperated with BB team Neil. */
1899bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode)
1900{
1901 struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1902 u32 CurrentChannel, RfLoopReg;
1903 u8 n;
1904 u32 Reg88c, Regc08, Reg874, Regc50;
1905 u8 initial_gain = 0x5a;
1906 u32 PSD_report_tmp;
1907 u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1908 bool bResult = true;
1909 u32 AFE_Backup[16];
1910 u32 AFE_REG_8723A[16] = {
1911 rRx_Wait_CCA, rTx_CCK_RFON,
1912 rTx_CCK_BBON, rTx_OFDM_RFON,
1913 rTx_OFDM_BBON, rTx_To_Rx,
1914 rTx_To_Tx, rRx_CCK,
1915 rRx_OFDM, rRx_Wait_RIFS,
1916 rRx_TO_Rx, rStandby,
1917 rSleep, rPMPD_ANAEN,
1918 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1919
1920 if (!(pDM_Odm->SupportICType & (ODM_RTL8723A)))
1921 return bResult;
1922
1923 if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
1924 return bResult;
1925 /* 1 Backup Current RF/BB Settings */
1926
1927 CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1928 RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1929 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); /* change to Antenna A */
1930 /* Step 1: USE IQK to transmitter single tone */
1931
1932 udelay(10);
1933
1934 /* Store A Path Register 88c, c08, 874, c50 */
1935 Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1936 Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1937 Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1938 Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1939
1940 /* Store AFE Registers */
1941 odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1942
1943 /* Set PSD 128 pts */
1944 ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); /* 128 pts */
1945
1946 /* To SET CH1 to do */
1947 ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); /* Channel 1 */
1948
1949 /* AFE all on step */
1950 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1951 ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1952 ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1953 ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1954 ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1955 ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1956 ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1957 ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1958 ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1959 ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1960 ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1961 ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1962 ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
1963 ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
1964 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
1965 ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
1966
1967 /* 3 wire Disable */
1968 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
1969
1970 /* BB IQK Setting */
1971 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
1972 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
1973
1974 /* IQK setting tone@ 4.34Mhz */
1975 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
1976 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1977
1978 /* Page B init */
1979 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
1980 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1981 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1982 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
1983 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
1984 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
1985 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
1986
1987 /* RF loop Setting */
1988 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
1989
1990 /* IQK Single tone start */
1991 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
1992 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1993 udelay(1000);
1994 PSD_report_tmp = 0x0;
1995
1996 for (n = 0; n < 2; n++) {
1997 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1998 if (PSD_report_tmp > AntA_report)
1999 AntA_report = PSD_report_tmp;
2000 }
2001
2002 PSD_report_tmp = 0x0;
2003
2004 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); /* change to Antenna B */
2005 udelay(10);
2006
2007 for (n = 0; n < 2; n++) {
2008 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
2009 if (PSD_report_tmp > AntB_report)
2010 AntB_report = PSD_report_tmp;
2011 }
2012
2013 /* change to open case */
2014 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0); /* change to Ant A and B all open case */
2015 udelay(10);
2016
2017 for (n = 0; n < 2; n++) {
2018 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
2019 if (PSD_report_tmp > AntO_report)
2020 AntO_report = PSD_report_tmp;
2021 }
2022
2023 /* Close IQK Single Tone function */
2024 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
2025 PSD_report_tmp = 0x0;
2026
2027 /* 1 Return to antanna A */
2028 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
2029 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
2030 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
2031 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
2032 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
2033 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
2034 ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
2035 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
2036
2037 /* Reload AFE Registers */
2038 odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
2039
2040 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
2041 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
2042 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
2043
2044 /* 2 Test Ant B based on Ant A is ON */
2045 if (mode == ANTTESTB) {
2046 if (AntA_report >= 100) {
2047 if (AntB_report > (AntA_report+1)) {
2048 pDM_SWAT_Table->ANTB_ON = false;
2049 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
2050 } else {
2051 pDM_SWAT_Table->ANTB_ON = true;
2052 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
2053 }
2054 } else {
2055 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
2056 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
2057 bResult = false;
2058 }
2059 } else if (mode == ANTTESTALL) {
2060 /* 2 Test Ant A and B based on DPDT Open */
2061 if ((AntO_report >= 100) & (AntO_report < 118)) {
2062 if (AntA_report > (AntO_report+1)) {
2063 pDM_SWAT_Table->ANTA_ON = false;
2064 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF"));
2065 } else {
2066 pDM_SWAT_Table->ANTA_ON = true;
2067 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON"));
2068 }
2069
2070 if (AntB_report > (AntO_report+2)) {
2071 pDM_SWAT_Table->ANTB_ON = false;
2072 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF"));
2073 } else {
2074 pDM_SWAT_Table->ANTB_ON = true;
2075 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON"));
2076 }
2077 }
2078 } else {
2079 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
2080 pDM_SWAT_Table->ANTA_ON = true; /* Set Antenna A on as default */
2081 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
2082 bResult = false;
2083 }
2084 return bResult;
2085}
2086
2087/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
2088void odm_dtc(struct dm_odm_t *pDM_Odm)
2089{
2090}