blob: 9a9ab82a8ed3611e505828073237f188e62425df [file] [log] [blame]
navin patidar053ab2a2014-09-07 16:38:03 +05301#include <odm.h>
2
3#define IQK_DELAY_TIME_88E 10
4#define index_mapping_NUM_88E 15
5#define AVG_THERMAL_NUM_88E 4
6#define ODM_TARGET_CHNL_NUM_2G_5G 59
7
Stephen Rothwell90d88de2014-08-18 08:40:48 +10008bool rtl88eu_phy_mac_config(struct adapter *adapt);
9bool rtl88eu_phy_rf_config(struct adapter *adapt);
10bool rtl88eu_phy_bb_config(struct adapter *adapt);
navin patidarecd1f9b2014-08-31 12:14:17 +053011
12u32 phy_query_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask);
navin patidar9c6db652014-08-31 12:14:19 +053013void phy_set_bb_reg(struct adapter *adapt, u32 regaddr, u32 bitmask, u32 data);
navin patidar41b77d22014-08-31 12:14:22 +053014u32 phy_query_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path,
15 u32 reg_addr, u32 bit_mask);
navin patidar7b984852014-08-31 12:14:23 +053016void phy_set_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path,
17 u32 reg_addr, u32 bit_mask, u32 data);
navin patidar01c5f832014-08-31 12:14:28 +053018
19void phy_set_tx_power_level(struct adapter *adapt, u8 channel);
navin patidar5f6a5cd2014-08-31 12:14:29 +053020
21void phy_set_bw_mode(struct adapter *adapt, enum ht_channel_width bandwidth,
22 unsigned char offset);
navin patidarba50fbc2014-08-31 12:14:30 +053023void phy_sw_chnl(struct adapter *adapt, u8 channel);
navin patidar053ab2a2014-09-07 16:38:03 +053024
25void rtl88eu_dm_txpower_track_adjust(struct odm_dm_struct *dm_odm,
26 u8 type, u8 *dir, u32 *out_write);
27
28void rtl88eu_dm_txpower_tracking_callback_thermalmeter(struct adapter *adapt);
29void rtl88eu_phy_iq_calibrate(struct adapter *adapter, bool recovery);
30void rtl88eu_phy_lc_calibrate(struct adapter *adapter);