Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/m68k/mm/memory.c |
| 3 | * |
| 4 | * Copyright (C) 1995 Hamish Macdonald |
| 5 | */ |
| 6 | |
| 7 | #include <linux/config.h> |
| 8 | #include <linux/mm.h> |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/string.h> |
| 11 | #include <linux/types.h> |
| 12 | #include <linux/slab.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/pagemap.h> |
| 15 | |
| 16 | #include <asm/setup.h> |
| 17 | #include <asm/segment.h> |
| 18 | #include <asm/page.h> |
| 19 | #include <asm/pgalloc.h> |
| 20 | #include <asm/system.h> |
| 21 | #include <asm/traps.h> |
| 22 | #include <asm/machdep.h> |
| 23 | |
| 24 | |
| 25 | /* ++andreas: {get,free}_pointer_table rewritten to use unused fields from |
| 26 | struct page instead of separately kmalloced struct. Stolen from |
| 27 | arch/sparc/mm/srmmu.c ... */ |
| 28 | |
| 29 | typedef struct list_head ptable_desc; |
| 30 | static LIST_HEAD(ptable_list); |
| 31 | |
| 32 | #define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page(page)->lru)) |
| 33 | #define PD_PAGE(ptable) (list_entry(ptable, struct page, lru)) |
| 34 | #define PD_MARKBITS(dp) (*(unsigned char *)&PD_PAGE(dp)->index) |
| 35 | |
| 36 | #define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t)) |
| 37 | |
| 38 | void __init init_pointer_table(unsigned long ptable) |
| 39 | { |
| 40 | ptable_desc *dp; |
| 41 | unsigned long page = ptable & PAGE_MASK; |
| 42 | unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE); |
| 43 | |
| 44 | dp = PD_PTABLE(page); |
| 45 | if (!(PD_MARKBITS(dp) & mask)) { |
| 46 | PD_MARKBITS(dp) = 0xff; |
| 47 | list_add(dp, &ptable_list); |
| 48 | } |
| 49 | |
| 50 | PD_MARKBITS(dp) &= ~mask; |
| 51 | #ifdef DEBUG |
| 52 | printk("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp)); |
| 53 | #endif |
| 54 | |
| 55 | /* unreserve the page so it's possible to free that page */ |
| 56 | PD_PAGE(dp)->flags &= ~(1 << PG_reserved); |
Nick Piggin | 7835e98 | 2006-03-22 00:08:40 -0800 | [diff] [blame] | 57 | init_page_count(PD_PAGE(dp)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | |
| 59 | return; |
| 60 | } |
| 61 | |
| 62 | pmd_t *get_pointer_table (void) |
| 63 | { |
| 64 | ptable_desc *dp = ptable_list.next; |
| 65 | unsigned char mask = PD_MARKBITS (dp); |
| 66 | unsigned char tmp; |
| 67 | unsigned int off; |
| 68 | |
| 69 | /* |
| 70 | * For a pointer table for a user process address space, a |
| 71 | * table is taken from a page allocated for the purpose. Each |
| 72 | * page can hold 8 pointer tables. The page is remapped in |
| 73 | * virtual address space to be noncacheable. |
| 74 | */ |
| 75 | if (mask == 0) { |
| 76 | void *page; |
| 77 | ptable_desc *new; |
| 78 | |
| 79 | if (!(page = (void *)get_zeroed_page(GFP_KERNEL))) |
| 80 | return NULL; |
| 81 | |
| 82 | flush_tlb_kernel_page(page); |
| 83 | nocache_page(page); |
| 84 | |
| 85 | new = PD_PTABLE(page); |
| 86 | PD_MARKBITS(new) = 0xfe; |
| 87 | list_add_tail(new, dp); |
| 88 | |
| 89 | return (pmd_t *)page; |
| 90 | } |
| 91 | |
| 92 | for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE) |
| 93 | ; |
| 94 | PD_MARKBITS(dp) = mask & ~tmp; |
| 95 | if (!PD_MARKBITS(dp)) { |
| 96 | /* move to end of list */ |
Akinobu Mita | a7addce | 2006-06-26 00:24:39 -0700 | [diff] [blame] | 97 | list_move_tail(dp, &ptable_list); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | } |
| 99 | return (pmd_t *) (page_address(PD_PAGE(dp)) + off); |
| 100 | } |
| 101 | |
| 102 | int free_pointer_table (pmd_t *ptable) |
| 103 | { |
| 104 | ptable_desc *dp; |
| 105 | unsigned long page = (unsigned long)ptable & PAGE_MASK; |
| 106 | unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE); |
| 107 | |
| 108 | dp = PD_PTABLE(page); |
| 109 | if (PD_MARKBITS (dp) & mask) |
| 110 | panic ("table already free!"); |
| 111 | |
| 112 | PD_MARKBITS (dp) |= mask; |
| 113 | |
| 114 | if (PD_MARKBITS(dp) == 0xff) { |
| 115 | /* all tables in page are free, free page */ |
| 116 | list_del(dp); |
| 117 | cache_page((void *)page); |
| 118 | free_page (page); |
| 119 | return 1; |
| 120 | } else if (ptable_list.next != dp) { |
| 121 | /* |
| 122 | * move this descriptor to the front of the list, since |
| 123 | * it has one or more free tables. |
| 124 | */ |
Akinobu Mita | a7addce | 2006-06-26 00:24:39 -0700 | [diff] [blame] | 125 | list_move(dp, &ptable_list); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | } |
| 127 | return 0; |
| 128 | } |
| 129 | |
| 130 | #ifdef DEBUG_INVALID_PTOV |
| 131 | int mm_inv_cnt = 5; |
| 132 | #endif |
| 133 | |
| 134 | #ifndef CONFIG_SINGLE_MEMORY_CHUNK |
| 135 | /* |
| 136 | * The following two routines map from a physical address to a kernel |
| 137 | * virtual address and vice versa. |
| 138 | */ |
| 139 | unsigned long mm_vtop(unsigned long vaddr) |
| 140 | { |
| 141 | int i=0; |
| 142 | unsigned long voff = (unsigned long)vaddr - PAGE_OFFSET; |
| 143 | |
| 144 | do { |
| 145 | if (voff < m68k_memory[i].size) { |
| 146 | #ifdef DEBUGPV |
| 147 | printk ("VTOP(%p)=%lx\n", vaddr, |
| 148 | m68k_memory[i].addr + voff); |
| 149 | #endif |
| 150 | return m68k_memory[i].addr + voff; |
| 151 | } |
| 152 | voff -= m68k_memory[i].size; |
| 153 | } while (++i < m68k_num_memory); |
| 154 | |
| 155 | /* As a special case allow `__pa(high_memory)'. */ |
| 156 | if (voff == 0) |
| 157 | return m68k_memory[i-1].addr + m68k_memory[i-1].size; |
| 158 | |
| 159 | return -1; |
| 160 | } |
| 161 | #endif |
| 162 | |
| 163 | #ifndef CONFIG_SINGLE_MEMORY_CHUNK |
| 164 | unsigned long mm_ptov (unsigned long paddr) |
| 165 | { |
| 166 | int i = 0; |
| 167 | unsigned long poff, voff = PAGE_OFFSET; |
| 168 | |
| 169 | do { |
| 170 | poff = paddr - m68k_memory[i].addr; |
| 171 | if (poff < m68k_memory[i].size) { |
| 172 | #ifdef DEBUGPV |
| 173 | printk ("PTOV(%lx)=%lx\n", paddr, poff + voff); |
| 174 | #endif |
| 175 | return poff + voff; |
| 176 | } |
| 177 | voff += m68k_memory[i].size; |
| 178 | } while (++i < m68k_num_memory); |
| 179 | |
| 180 | #ifdef DEBUG_INVALID_PTOV |
| 181 | if (mm_inv_cnt > 0) { |
| 182 | mm_inv_cnt--; |
| 183 | printk("Invalid use of phys_to_virt(0x%lx) at 0x%p!\n", |
| 184 | paddr, __builtin_return_address(0)); |
| 185 | } |
| 186 | #endif |
| 187 | return -1; |
| 188 | } |
| 189 | #endif |
| 190 | |
| 191 | /* invalidate page in both caches */ |
| 192 | static inline void clear040(unsigned long paddr) |
| 193 | { |
| 194 | asm volatile ( |
| 195 | "nop\n\t" |
| 196 | ".chip 68040\n\t" |
| 197 | "cinvp %%bc,(%0)\n\t" |
| 198 | ".chip 68k" |
| 199 | : : "a" (paddr)); |
| 200 | } |
| 201 | |
| 202 | /* invalidate page in i-cache */ |
| 203 | static inline void cleari040(unsigned long paddr) |
| 204 | { |
| 205 | asm volatile ( |
| 206 | "nop\n\t" |
| 207 | ".chip 68040\n\t" |
| 208 | "cinvp %%ic,(%0)\n\t" |
| 209 | ".chip 68k" |
| 210 | : : "a" (paddr)); |
| 211 | } |
| 212 | |
| 213 | /* push page in both caches */ |
| 214 | /* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */ |
| 215 | static inline void push040(unsigned long paddr) |
| 216 | { |
| 217 | asm volatile ( |
| 218 | "nop\n\t" |
| 219 | ".chip 68040\n\t" |
| 220 | "cpushp %%bc,(%0)\n\t" |
| 221 | ".chip 68k" |
| 222 | : : "a" (paddr)); |
| 223 | } |
| 224 | |
| 225 | /* push and invalidate page in both caches, must disable ints |
| 226 | * to avoid invalidating valid data */ |
| 227 | static inline void pushcl040(unsigned long paddr) |
| 228 | { |
| 229 | unsigned long flags; |
| 230 | |
| 231 | local_irq_save(flags); |
| 232 | push040(paddr); |
| 233 | if (CPU_IS_060) |
| 234 | clear040(paddr); |
| 235 | local_irq_restore(flags); |
| 236 | } |
| 237 | |
| 238 | /* |
| 239 | * 040: Hit every page containing an address in the range paddr..paddr+len-1. |
| 240 | * (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s). |
| 241 | * Hit every page until there is a page or less to go. Hit the next page, |
| 242 | * and the one after that if the range hits it. |
| 243 | */ |
| 244 | /* ++roman: A little bit more care is required here: The CINVP instruction |
| 245 | * invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning |
| 246 | * and the end of the region must be treated differently if they are not |
| 247 | * exactly at the beginning or end of a page boundary. Else, maybe too much |
| 248 | * data becomes invalidated and thus lost forever. CPUSHP does what we need: |
| 249 | * it invalidates the page after pushing dirty data to memory. (Thanks to Jes |
| 250 | * for discovering the problem!) |
| 251 | */ |
| 252 | /* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set |
| 253 | * the DPI bit in the CACR; would it cause problems with temporarily changing |
| 254 | * this?). So we have to push first and then additionally to invalidate. |
| 255 | */ |
| 256 | |
| 257 | |
| 258 | /* |
| 259 | * cache_clear() semantics: Clear any cache entries for the area in question, |
| 260 | * without writing back dirty entries first. This is useful if the data will |
| 261 | * be overwritten anyway, e.g. by DMA to memory. The range is defined by a |
| 262 | * _physical_ address. |
| 263 | */ |
| 264 | |
| 265 | void cache_clear (unsigned long paddr, int len) |
| 266 | { |
| 267 | if (CPU_IS_040_OR_060) { |
| 268 | int tmp; |
| 269 | |
| 270 | /* |
| 271 | * We need special treatment for the first page, in case it |
| 272 | * is not page-aligned. Page align the addresses to work |
| 273 | * around bug I17 in the 68060. |
| 274 | */ |
| 275 | if ((tmp = -paddr & (PAGE_SIZE - 1))) { |
| 276 | pushcl040(paddr & PAGE_MASK); |
| 277 | if ((len -= tmp) <= 0) |
| 278 | return; |
| 279 | paddr += tmp; |
| 280 | } |
| 281 | tmp = PAGE_SIZE; |
| 282 | paddr &= PAGE_MASK; |
| 283 | while ((len -= tmp) >= 0) { |
| 284 | clear040(paddr); |
| 285 | paddr += tmp; |
| 286 | } |
| 287 | if ((len += tmp)) |
| 288 | /* a page boundary gets crossed at the end */ |
| 289 | pushcl040(paddr); |
| 290 | } |
| 291 | else /* 68030 or 68020 */ |
| 292 | asm volatile ("movec %/cacr,%/d0\n\t" |
| 293 | "oriw %0,%/d0\n\t" |
| 294 | "movec %/d0,%/cacr" |
| 295 | : : "i" (FLUSH_I_AND_D) |
| 296 | : "d0"); |
| 297 | #ifdef CONFIG_M68K_L2_CACHE |
| 298 | if(mach_l2_flush) |
| 299 | mach_l2_flush(0); |
| 300 | #endif |
| 301 | } |
| 302 | |
| 303 | |
| 304 | /* |
| 305 | * cache_push() semantics: Write back any dirty cache data in the given area, |
| 306 | * and invalidate the range in the instruction cache. It needs not (but may) |
| 307 | * invalidate those entries also in the data cache. The range is defined by a |
| 308 | * _physical_ address. |
| 309 | */ |
| 310 | |
| 311 | void cache_push (unsigned long paddr, int len) |
| 312 | { |
| 313 | if (CPU_IS_040_OR_060) { |
| 314 | int tmp = PAGE_SIZE; |
| 315 | |
| 316 | /* |
| 317 | * on 68040 or 68060, push cache lines for pages in the range; |
| 318 | * on the '040 this also invalidates the pushed lines, but not on |
| 319 | * the '060! |
| 320 | */ |
| 321 | len += paddr & (PAGE_SIZE - 1); |
| 322 | |
| 323 | /* |
| 324 | * Work around bug I17 in the 68060 affecting some instruction |
| 325 | * lines not being invalidated properly. |
| 326 | */ |
| 327 | paddr &= PAGE_MASK; |
| 328 | |
| 329 | do { |
| 330 | push040(paddr); |
| 331 | paddr += tmp; |
| 332 | } while ((len -= tmp) > 0); |
| 333 | } |
| 334 | /* |
| 335 | * 68030/68020 have no writeback cache. On the other hand, |
| 336 | * cache_push is actually a superset of cache_clear (the lines |
| 337 | * get written back and invalidated), so we should make sure |
| 338 | * to perform the corresponding actions. After all, this is getting |
| 339 | * called in places where we've just loaded code, or whatever, so |
| 340 | * flushing the icache is appropriate; flushing the dcache shouldn't |
| 341 | * be required. |
| 342 | */ |
| 343 | else /* 68030 or 68020 */ |
| 344 | asm volatile ("movec %/cacr,%/d0\n\t" |
| 345 | "oriw %0,%/d0\n\t" |
| 346 | "movec %/d0,%/cacr" |
| 347 | : : "i" (FLUSH_I) |
| 348 | : "d0"); |
| 349 | #ifdef CONFIG_M68K_L2_CACHE |
| 350 | if(mach_l2_flush) |
| 351 | mach_l2_flush(1); |
| 352 | #endif |
| 353 | } |
| 354 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 355 | #ifndef CONFIG_SINGLE_MEMORY_CHUNK |
| 356 | int mm_end_of_chunk (unsigned long addr, int len) |
| 357 | { |
| 358 | int i; |
| 359 | |
| 360 | for (i = 0; i < m68k_num_memory; i++) |
| 361 | if (m68k_memory[i].addr + m68k_memory[i].size == addr + len) |
| 362 | return 1; |
| 363 | return 0; |
| 364 | } |
| 365 | #endif |