blob: dd6fe942acf9d3159248501853d28900c827388c [file] [log] [blame]
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001/*
2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
Thomas Petazzonic5aff182012-08-17 14:04:28 +030015#include <linux/netdevice.h>
16#include <linux/etherdevice.h>
17#include <linux/platform_device.h>
18#include <linux/skbuff.h>
19#include <linux/inetdevice.h>
20#include <linux/mbus.h>
21#include <linux/module.h>
22#include <linux/interrupt.h>
David S. Miller2d39d122014-08-25 20:21:55 -070023#include <linux/if_vlan.h>
Thomas Petazzonic5aff182012-08-17 14:04:28 +030024#include <net/ip.h>
25#include <net/ipv6.h>
Thomas Petazzonic3f0dd32014-03-27 11:39:29 +010026#include <linux/io.h>
Ezequiel Garcia2adb7192014-05-19 13:59:55 -030027#include <net/tso.h>
Thomas Petazzonic5aff182012-08-17 14:04:28 +030028#include <linux/of.h>
29#include <linux/of_irq.h>
30#include <linux/of_mdio.h>
31#include <linux/of_net.h>
32#include <linux/of_address.h>
33#include <linux/phy.h>
Thomas Petazzoni189dd622012-11-19 14:15:25 +010034#include <linux/clk.h>
Maxime Ripardf8642882015-09-25 18:09:38 +020035#include <linux/cpu.h>
Thomas Petazzonic5aff182012-08-17 14:04:28 +030036
37/* Registers */
38#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
39#define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
40#define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
41#define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
42#define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
43#define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
44#define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
45#define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
46#define MVNETA_RXQ_BUF_SIZE_SHIFT 19
47#define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
48#define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
49#define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
50#define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
51#define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
52#define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
53#define MVNETA_PORT_RX_RESET 0x1cc0
54#define MVNETA_PORT_RX_DMA_RESET BIT(0)
55#define MVNETA_PHY_ADDR 0x2000
56#define MVNETA_PHY_ADDR_MASK 0x1f
57#define MVNETA_MBUS_RETRY 0x2010
58#define MVNETA_UNIT_INTR_CAUSE 0x2080
59#define MVNETA_UNIT_CONTROL 0x20B0
60#define MVNETA_PHY_POLLING_ENABLE BIT(1)
61#define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
62#define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
63#define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
64#define MVNETA_BASE_ADDR_ENABLE 0x2290
65#define MVNETA_PORT_CONFIG 0x2400
66#define MVNETA_UNI_PROMISC_MODE BIT(0)
67#define MVNETA_DEF_RXQ(q) ((q) << 1)
68#define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
69#define MVNETA_TX_UNSET_ERR_SUM BIT(12)
70#define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
71#define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
72#define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
73#define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
74#define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
75 MVNETA_DEF_RXQ_ARP(q) | \
76 MVNETA_DEF_RXQ_TCP(q) | \
77 MVNETA_DEF_RXQ_UDP(q) | \
78 MVNETA_DEF_RXQ_BPDU(q) | \
79 MVNETA_TX_UNSET_ERR_SUM | \
80 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
81#define MVNETA_PORT_CONFIG_EXTEND 0x2404
82#define MVNETA_MAC_ADDR_LOW 0x2414
83#define MVNETA_MAC_ADDR_HIGH 0x2418
84#define MVNETA_SDMA_CONFIG 0x241c
85#define MVNETA_SDMA_BRST_SIZE_16 4
Thomas Petazzonic5aff182012-08-17 14:04:28 +030086#define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
87#define MVNETA_RX_NO_DATA_SWAP BIT(4)
88#define MVNETA_TX_NO_DATA_SWAP BIT(5)
Thomas Petazzoni9ad8fef2013-07-29 15:21:28 +020089#define MVNETA_DESC_SWAP BIT(6)
Thomas Petazzonic5aff182012-08-17 14:04:28 +030090#define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
91#define MVNETA_PORT_STATUS 0x2444
92#define MVNETA_TX_IN_PRGRS BIT(1)
93#define MVNETA_TX_FIFO_EMPTY BIT(8)
94#define MVNETA_RX_MIN_FRAME_SIZE 0x247c
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +020095#define MVNETA_SERDES_CFG 0x24A0
Arnaud Patard \(Rtp\)5445eaf2013-07-29 21:56:48 +020096#define MVNETA_SGMII_SERDES_PROTO 0x0cc7
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +020097#define MVNETA_QSGMII_SERDES_PROTO 0x0667
Thomas Petazzonic5aff182012-08-17 14:04:28 +030098#define MVNETA_TYPE_PRIO 0x24bc
99#define MVNETA_FORCE_UNI BIT(21)
100#define MVNETA_TXQ_CMD_1 0x24e4
101#define MVNETA_TXQ_CMD 0x2448
102#define MVNETA_TXQ_DISABLE_SHIFT 8
103#define MVNETA_TXQ_ENABLE_MASK 0x000000ff
Stas Sergeev898b2972015-04-01 20:32:49 +0300104#define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
105#define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300106#define MVNETA_ACC_MODE 0x2500
107#define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
108#define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
109#define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
110#define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
willy tarreau40ba35e2014-01-16 08:20:10 +0100111
112/* Exception Interrupt Port/Queue Cause register */
113
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300114#define MVNETA_INTR_NEW_CAUSE 0x25a0
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300115#define MVNETA_INTR_NEW_MASK 0x25a4
willy tarreau40ba35e2014-01-16 08:20:10 +0100116
117/* bits 0..7 = TXQ SENT, one bit per queue.
118 * bits 8..15 = RXQ OCCUP, one bit per queue.
119 * bits 16..23 = RXQ FREE, one bit per queue.
120 * bit 29 = OLD_REG_SUM, see old reg ?
121 * bit 30 = TX_ERR_SUM, one bit for 4 ports
122 * bit 31 = MISC_SUM, one bit for 4 ports
123 */
124#define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
125#define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
126#define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
127#define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
Stas Sergeev898b2972015-04-01 20:32:49 +0300128#define MVNETA_MISCINTR_INTR_MASK BIT(31)
willy tarreau40ba35e2014-01-16 08:20:10 +0100129
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300130#define MVNETA_INTR_OLD_CAUSE 0x25a8
131#define MVNETA_INTR_OLD_MASK 0x25ac
willy tarreau40ba35e2014-01-16 08:20:10 +0100132
133/* Data Path Port/Queue Cause Register */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300134#define MVNETA_INTR_MISC_CAUSE 0x25b0
135#define MVNETA_INTR_MISC_MASK 0x25b4
willy tarreau40ba35e2014-01-16 08:20:10 +0100136
137#define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
138#define MVNETA_CAUSE_LINK_CHANGE BIT(1)
139#define MVNETA_CAUSE_PTP BIT(4)
140
141#define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
142#define MVNETA_CAUSE_RX_OVERRUN BIT(8)
143#define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
144#define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
145#define MVNETA_CAUSE_TX_UNDERUN BIT(11)
146#define MVNETA_CAUSE_PRBS_ERR BIT(12)
147#define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
148#define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
149
150#define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
151#define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
152#define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
153
154#define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
155#define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
156#define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
157
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300158#define MVNETA_INTR_ENABLE 0x25b8
159#define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
willy tarreau40ba35e2014-01-16 08:20:10 +0100160#define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF
161
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300162#define MVNETA_RXQ_CMD 0x2680
163#define MVNETA_RXQ_DISABLE_SHIFT 8
164#define MVNETA_RXQ_ENABLE_MASK 0x000000ff
165#define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
166#define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
167#define MVNETA_GMAC_CTRL_0 0x2c00
168#define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
169#define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
170#define MVNETA_GMAC0_PORT_ENABLE BIT(0)
171#define MVNETA_GMAC_CTRL_2 0x2c08
Stas Sergeev898b2972015-04-01 20:32:49 +0300172#define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
Thomas Petazzonia79121d2014-03-26 00:25:41 +0100173#define MVNETA_GMAC2_PCS_ENABLE BIT(3)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300174#define MVNETA_GMAC2_PORT_RGMII BIT(4)
175#define MVNETA_GMAC2_PORT_RESET BIT(6)
176#define MVNETA_GMAC_STATUS 0x2c10
177#define MVNETA_GMAC_LINK_UP BIT(0)
178#define MVNETA_GMAC_SPEED_1000 BIT(1)
179#define MVNETA_GMAC_SPEED_100 BIT(2)
180#define MVNETA_GMAC_FULL_DUPLEX BIT(3)
181#define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
182#define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
183#define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
184#define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
185#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
186#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
187#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
Stas Sergeev898b2972015-04-01 20:32:49 +0300188#define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300189#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
190#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
Thomas Petazzoni71408602013-09-04 16:21:18 +0200191#define MVNETA_GMAC_AN_SPEED_EN BIT(7)
Stas Sergeev898b2972015-04-01 20:32:49 +0300192#define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300193#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
Thomas Petazzoni71408602013-09-04 16:21:18 +0200194#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300195#define MVNETA_MIB_COUNTERS_BASE 0x3080
196#define MVNETA_MIB_LATE_COLLISION 0x7c
197#define MVNETA_DA_FILT_SPEC_MCAST 0x3400
198#define MVNETA_DA_FILT_OTH_MCAST 0x3500
199#define MVNETA_DA_FILT_UCAST_BASE 0x3600
200#define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
201#define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
202#define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
203#define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
204#define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
205#define MVNETA_TXQ_DEC_SENT_SHIFT 16
206#define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
207#define MVNETA_TXQ_SENT_DESC_SHIFT 16
208#define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
209#define MVNETA_PORT_TX_RESET 0x3cf0
210#define MVNETA_PORT_TX_DMA_RESET BIT(0)
211#define MVNETA_TX_MTU 0x3e0c
212#define MVNETA_TX_TOKEN_SIZE 0x3e14
213#define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
214#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
215#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
216
217#define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
218
219/* Descriptor ring Macros */
220#define MVNETA_QUEUE_NEXT_DESC(q, index) \
221 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
222
223/* Various constants */
224
225/* Coalescing */
willy tarreauaebea2b2014-12-02 08:13:04 +0100226#define MVNETA_TXDONE_COAL_PKTS 1
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300227#define MVNETA_RX_COAL_PKTS 32
228#define MVNETA_RX_COAL_USEC 100
229
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100230/* The two bytes Marvell header. Either contains a special value used
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300231 * by Marvell switches when a specific hardware mode is enabled (not
232 * supported by this driver) or is filled automatically by zeroes on
233 * the RX side. Those two bytes being at the front of the Ethernet
234 * header, they allow to have the IP header aligned on a 4 bytes
235 * boundary automatically: the hardware skips those two bytes on its
236 * own.
237 */
238#define MVNETA_MH_SIZE 2
239
240#define MVNETA_VLAN_TAG_LEN 4
241
242#define MVNETA_CPU_D_CACHE_LINE_SIZE 32
243#define MVNETA_TX_CSUM_MAX_SIZE 9800
244#define MVNETA_ACC_MODE_EXT 1
245
246/* Timeout constants */
247#define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
248#define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
249#define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
250
251#define MVNETA_TX_MTU_MAX 0x3ffff
252
Ezequiel Garcia2adb7192014-05-19 13:59:55 -0300253/* TSO header size */
254#define TSO_HEADER_SIZE 128
255
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300256/* Max number of Rx descriptors */
257#define MVNETA_MAX_RXD 128
258
259/* Max number of Tx descriptors */
260#define MVNETA_MAX_TXD 532
261
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -0300262/* Max number of allowed TCP segments for software TSO */
263#define MVNETA_MAX_TSO_SEGS 100
264
265#define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
266
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300267/* descriptor aligned size */
268#define MVNETA_DESC_ALIGNED_SIZE 32
269
270#define MVNETA_RX_PKT_SIZE(mtu) \
271 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
272 ETH_HLEN + ETH_FCS_LEN, \
273 MVNETA_CPU_D_CACHE_LINE_SIZE)
274
Ezequiel Garcia2e3173a2014-05-30 13:40:07 -0300275#define IS_TSO_HEADER(txq, addr) \
276 ((addr >= txq->tso_hdrs_phys) && \
277 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
278
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300279#define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
280
willy tarreau74c41b02014-01-16 08:20:08 +0100281struct mvneta_pcpu_stats {
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300282 struct u64_stats_sync syncp;
willy tarreau74c41b02014-01-16 08:20:08 +0100283 u64 rx_packets;
284 u64 rx_bytes;
285 u64 tx_packets;
286 u64 tx_bytes;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300287};
288
Maxime Ripard12bb03b2015-09-25 18:09:36 +0200289struct mvneta_pcpu_port {
290 /* Pointer to the shared port */
291 struct mvneta_port *pp;
292
293 /* Pointer to the CPU-local NAPI struct */
294 struct napi_struct napi;
295
296 /* Cause of the previous interrupt */
297 u32 cause_rx_tx;
298};
299
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300300struct mvneta_port {
Maxime Ripard12bb03b2015-09-25 18:09:36 +0200301 struct mvneta_pcpu_port __percpu *ports;
302 struct mvneta_pcpu_stats __percpu *stats;
303
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300304 int pkt_size;
willy tarreau8ec2cd42014-01-16 08:20:16 +0100305 unsigned int frag_size;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300306 void __iomem *base;
307 struct mvneta_rx_queue *rxqs;
308 struct mvneta_tx_queue *txqs;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300309 struct net_device *dev;
Maxime Ripardf8642882015-09-25 18:09:38 +0200310 struct notifier_block cpu_notifier;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300311
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300312 /* Core clock */
Thomas Petazzoni189dd622012-11-19 14:15:25 +0100313 struct clk *clk;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300314 u8 mcast_count[256];
315 u16 tx_ring_size;
316 u16 rx_ring_size;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300317
318 struct mii_bus *mii_bus;
319 struct phy_device *phy_dev;
320 phy_interface_t phy_interface;
321 struct device_node *phy_node;
322 unsigned int link;
323 unsigned int duplex;
324 unsigned int speed;
Simon Guinotb65657f2015-06-30 16:20:22 +0200325 unsigned int tx_csum_limit;
Stas Sergeev898b2972015-04-01 20:32:49 +0300326 int use_inband_status:1;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300327};
328
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100329/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300330 * layout of the transmit and reception DMA descriptors, and their
331 * layout is therefore defined by the hardware design
332 */
Thomas Petazzoni6083ed42013-07-29 15:21:27 +0200333
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300334#define MVNETA_TX_L3_OFF_SHIFT 0
335#define MVNETA_TX_IP_HLEN_SHIFT 8
336#define MVNETA_TX_L4_UDP BIT(16)
337#define MVNETA_TX_L3_IP6 BIT(17)
338#define MVNETA_TXD_IP_CSUM BIT(18)
339#define MVNETA_TXD_Z_PAD BIT(19)
340#define MVNETA_TXD_L_DESC BIT(20)
341#define MVNETA_TXD_F_DESC BIT(21)
342#define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
343 MVNETA_TXD_L_DESC | \
344 MVNETA_TXD_F_DESC)
345#define MVNETA_TX_L4_CSUM_FULL BIT(30)
346#define MVNETA_TX_L4_CSUM_NOT BIT(31)
347
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300348#define MVNETA_RXD_ERR_CRC 0x0
349#define MVNETA_RXD_ERR_SUMMARY BIT(16)
350#define MVNETA_RXD_ERR_OVERRUN BIT(17)
351#define MVNETA_RXD_ERR_LEN BIT(18)
352#define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
353#define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
354#define MVNETA_RXD_L3_IP4 BIT(25)
355#define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
356#define MVNETA_RXD_L4_CSUM_OK BIT(30)
357
Thomas Petazzoni9ad8fef2013-07-29 15:21:28 +0200358#if defined(__LITTLE_ENDIAN)
Thomas Petazzoni6083ed42013-07-29 15:21:27 +0200359struct mvneta_tx_desc {
360 u32 command; /* Options used by HW for packet transmitting.*/
361 u16 reserverd1; /* csum_l4 (for future use) */
362 u16 data_size; /* Data size of transmitted packet in bytes */
363 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
364 u32 reserved2; /* hw_cmd - (for future use, PMT) */
365 u32 reserved3[4]; /* Reserved - (for future use) */
366};
367
368struct mvneta_rx_desc {
369 u32 status; /* Info about received packet */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300370 u16 reserved1; /* pnc_info - (for future use, PnC) */
371 u16 data_size; /* Size of received packet in bytes */
Thomas Petazzoni6083ed42013-07-29 15:21:27 +0200372
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300373 u32 buf_phys_addr; /* Physical address of the buffer */
374 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
Thomas Petazzoni6083ed42013-07-29 15:21:27 +0200375
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300376 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
377 u16 reserved3; /* prefetch_cmd, for future use */
378 u16 reserved4; /* csum_l4 - (for future use, PnC) */
Thomas Petazzoni6083ed42013-07-29 15:21:27 +0200379
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300380 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
381 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
382};
Thomas Petazzoni9ad8fef2013-07-29 15:21:28 +0200383#else
384struct mvneta_tx_desc {
385 u16 data_size; /* Data size of transmitted packet in bytes */
386 u16 reserverd1; /* csum_l4 (for future use) */
387 u32 command; /* Options used by HW for packet transmitting.*/
388 u32 reserved2; /* hw_cmd - (for future use, PMT) */
389 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
390 u32 reserved3[4]; /* Reserved - (for future use) */
391};
392
393struct mvneta_rx_desc {
394 u16 data_size; /* Size of received packet in bytes */
395 u16 reserved1; /* pnc_info - (for future use, PnC) */
396 u32 status; /* Info about received packet */
397
398 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
399 u32 buf_phys_addr; /* Physical address of the buffer */
400
401 u16 reserved4; /* csum_l4 - (for future use, PnC) */
402 u16 reserved3; /* prefetch_cmd, for future use */
403 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
404
405 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
406 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
407};
408#endif
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300409
410struct mvneta_tx_queue {
411 /* Number of this TX queue, in the range 0-7 */
412 u8 id;
413
414 /* Number of TX DMA descriptors in the descriptor ring */
415 int size;
416
417 /* Number of currently used TX DMA descriptor in the
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100418 * descriptor ring
419 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300420 int count;
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -0300421 int tx_stop_threshold;
422 int tx_wake_threshold;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300423
424 /* Array of transmitted skb */
425 struct sk_buff **tx_skb;
426
427 /* Index of last TX DMA descriptor that was inserted */
428 int txq_put_index;
429
430 /* Index of the TX DMA descriptor to be cleaned up */
431 int txq_get_index;
432
433 u32 done_pkts_coal;
434
435 /* Virtual address of the TX DMA descriptors array */
436 struct mvneta_tx_desc *descs;
437
438 /* DMA address of the TX DMA descriptors array */
439 dma_addr_t descs_phys;
440
441 /* Index of the last TX DMA descriptor */
442 int last_desc;
443
444 /* Index of the next TX DMA descriptor to process */
445 int next_desc_to_proc;
Ezequiel Garcia2adb7192014-05-19 13:59:55 -0300446
447 /* DMA buffers for TSO headers */
448 char *tso_hdrs;
449
450 /* DMA address of TSO headers */
451 dma_addr_t tso_hdrs_phys;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300452};
453
454struct mvneta_rx_queue {
455 /* rx queue number, in the range 0-7 */
456 u8 id;
457
458 /* num of rx descriptors in the rx descriptor ring */
459 int size;
460
461 /* counter of times when mvneta_refill() failed */
462 int missed;
463
464 u32 pkts_coal;
465 u32 time_coal;
466
467 /* Virtual address of the RX DMA descriptors array */
468 struct mvneta_rx_desc *descs;
469
470 /* DMA address of the RX DMA descriptors array */
471 dma_addr_t descs_phys;
472
473 /* Index of the last RX DMA descriptor */
474 int last_desc;
475
476 /* Index of the next RX DMA descriptor to process */
477 int next_desc_to_proc;
478};
479
Ezequiel Garciaedadb7f2014-05-22 20:07:01 -0300480/* The hardware supports eight (8) rx queues, but we are only allowing
481 * the first one to be used. Therefore, let's just allocate one queue.
482 */
Maxime Ripardd8936652015-09-25 18:09:37 +0200483static int rxq_number = 8;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300484static int txq_number = 8;
485
486static int rxq_def;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300487
willy tarreauf19fadf2014-01-16 08:20:17 +0100488static int rx_copybreak __read_mostly = 256;
489
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300490#define MVNETA_DRIVER_NAME "mvneta"
491#define MVNETA_DRIVER_VERSION "1.0"
492
493/* Utility/helper methods */
494
495/* Write helper method */
496static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
497{
498 writel(data, pp->base + offset);
499}
500
501/* Read helper method */
502static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
503{
504 return readl(pp->base + offset);
505}
506
507/* Increment txq get counter */
508static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
509{
510 txq->txq_get_index++;
511 if (txq->txq_get_index == txq->size)
512 txq->txq_get_index = 0;
513}
514
515/* Increment txq put counter */
516static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
517{
518 txq->txq_put_index++;
519 if (txq->txq_put_index == txq->size)
520 txq->txq_put_index = 0;
521}
522
523
524/* Clear all MIB counters */
525static void mvneta_mib_counters_clear(struct mvneta_port *pp)
526{
527 int i;
528 u32 dummy;
529
530 /* Perform dummy reads from MIB counters */
531 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
532 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
533}
534
535/* Get System Network Statistics */
536struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
537 struct rtnl_link_stats64 *stats)
538{
539 struct mvneta_port *pp = netdev_priv(dev);
540 unsigned int start;
willy tarreau74c41b02014-01-16 08:20:08 +0100541 int cpu;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300542
willy tarreau74c41b02014-01-16 08:20:08 +0100543 for_each_possible_cpu(cpu) {
544 struct mvneta_pcpu_stats *cpu_stats;
545 u64 rx_packets;
546 u64 rx_bytes;
547 u64 tx_packets;
548 u64 tx_bytes;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300549
willy tarreau74c41b02014-01-16 08:20:08 +0100550 cpu_stats = per_cpu_ptr(pp->stats, cpu);
551 do {
Eric W. Biederman57a77442014-03-13 21:26:42 -0700552 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
willy tarreau74c41b02014-01-16 08:20:08 +0100553 rx_packets = cpu_stats->rx_packets;
554 rx_bytes = cpu_stats->rx_bytes;
555 tx_packets = cpu_stats->tx_packets;
556 tx_bytes = cpu_stats->tx_bytes;
Eric W. Biederman57a77442014-03-13 21:26:42 -0700557 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300558
willy tarreau74c41b02014-01-16 08:20:08 +0100559 stats->rx_packets += rx_packets;
560 stats->rx_bytes += rx_bytes;
561 stats->tx_packets += tx_packets;
562 stats->tx_bytes += tx_bytes;
563 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300564
565 stats->rx_errors = dev->stats.rx_errors;
566 stats->rx_dropped = dev->stats.rx_dropped;
567
568 stats->tx_dropped = dev->stats.tx_dropped;
569
570 return stats;
571}
572
573/* Rx descriptors helper methods */
574
willy tarreau54282132014-01-16 08:20:14 +0100575/* Checks whether the RX descriptor having this status is both the first
576 * and the last descriptor for the RX packet. Each RX packet is currently
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300577 * received through a single RX descriptor, so not having each RX
578 * descriptor with its first and last bits set is an error
579 */
willy tarreau54282132014-01-16 08:20:14 +0100580static int mvneta_rxq_desc_is_first_last(u32 status)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300581{
willy tarreau54282132014-01-16 08:20:14 +0100582 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300583 MVNETA_RXD_FIRST_LAST_DESC;
584}
585
586/* Add number of descriptors ready to receive new packets */
587static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
588 struct mvneta_rx_queue *rxq,
589 int ndescs)
590{
591 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100592 * be added at once
593 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300594 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
595 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
596 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
597 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
598 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
599 }
600
601 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
602 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
603}
604
605/* Get number of RX descriptors occupied by received packets */
606static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
607 struct mvneta_rx_queue *rxq)
608{
609 u32 val;
610
611 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
612 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
613}
614
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100615/* Update num of rx desc called upon return from rx path or
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300616 * from mvneta_rxq_drop_pkts().
617 */
618static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
619 struct mvneta_rx_queue *rxq,
620 int rx_done, int rx_filled)
621{
622 u32 val;
623
624 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
625 val = rx_done |
626 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
627 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
628 return;
629 }
630
631 /* Only 255 descriptors can be added at once */
632 while ((rx_done > 0) || (rx_filled > 0)) {
633 if (rx_done <= 0xff) {
634 val = rx_done;
635 rx_done = 0;
636 } else {
637 val = 0xff;
638 rx_done -= 0xff;
639 }
640 if (rx_filled <= 0xff) {
641 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
642 rx_filled = 0;
643 } else {
644 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
645 rx_filled -= 0xff;
646 }
647 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
648 }
649}
650
651/* Get pointer to next RX descriptor to be processed by SW */
652static struct mvneta_rx_desc *
653mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
654{
655 int rx_desc = rxq->next_desc_to_proc;
656
657 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
willy tarreau34e41792014-01-16 08:20:15 +0100658 prefetch(rxq->descs + rxq->next_desc_to_proc);
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300659 return rxq->descs + rx_desc;
660}
661
662/* Change maximum receive size of the port. */
663static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
664{
665 u32 val;
666
667 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
668 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
669 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
670 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
671 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
672}
673
674
675/* Set rx queue offset */
676static void mvneta_rxq_offset_set(struct mvneta_port *pp,
677 struct mvneta_rx_queue *rxq,
678 int offset)
679{
680 u32 val;
681
682 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
683 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
684
685 /* Offset is in */
686 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
687 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
688}
689
690
691/* Tx descriptors helper methods */
692
693/* Update HW with number of TX descriptors to be sent */
694static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
695 struct mvneta_tx_queue *txq,
696 int pend_desc)
697{
698 u32 val;
699
700 /* Only 255 descriptors can be added at once ; Assume caller
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100701 * process TX desriptors in quanta less than 256
702 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300703 val = pend_desc;
704 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
705}
706
707/* Get pointer to next TX descriptor to be processed (send) by HW */
708static struct mvneta_tx_desc *
709mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
710{
711 int tx_desc = txq->next_desc_to_proc;
712
713 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
714 return txq->descs + tx_desc;
715}
716
717/* Release the last allocated TX descriptor. Useful to handle DMA
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100718 * mapping failures in the TX path.
719 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300720static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
721{
722 if (txq->next_desc_to_proc == 0)
723 txq->next_desc_to_proc = txq->last_desc - 1;
724 else
725 txq->next_desc_to_proc--;
726}
727
728/* Set rxq buf size */
729static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
730 struct mvneta_rx_queue *rxq,
731 int buf_size)
732{
733 u32 val;
734
735 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
736
737 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
738 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
739
740 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
741}
742
743/* Disable buffer management (BM) */
744static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
745 struct mvneta_rx_queue *rxq)
746{
747 u32 val;
748
749 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
750 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
751 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
752}
753
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300754/* Start the Ethernet port RX and TX activity */
755static void mvneta_port_up(struct mvneta_port *pp)
756{
757 int queue;
758 u32 q_map;
759
760 /* Enable all initialized TXs. */
761 mvneta_mib_counters_clear(pp);
762 q_map = 0;
763 for (queue = 0; queue < txq_number; queue++) {
764 struct mvneta_tx_queue *txq = &pp->txqs[queue];
765 if (txq->descs != NULL)
766 q_map |= (1 << queue);
767 }
768 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
769
770 /* Enable all initialized RXQs. */
Maxime Ripardd8936652015-09-25 18:09:37 +0200771 mvreg_write(pp, MVNETA_RXQ_CMD, BIT(rxq_def));
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300772}
773
774/* Stop the Ethernet port activity */
775static void mvneta_port_down(struct mvneta_port *pp)
776{
777 u32 val;
778 int count;
779
780 /* Stop Rx port activity. Check port Rx activity. */
781 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
782
783 /* Issue stop command for active channels only */
784 if (val != 0)
785 mvreg_write(pp, MVNETA_RXQ_CMD,
786 val << MVNETA_RXQ_DISABLE_SHIFT);
787
788 /* Wait for all Rx activity to terminate. */
789 count = 0;
790 do {
791 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
792 netdev_warn(pp->dev,
793 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
794 val);
795 break;
796 }
797 mdelay(1);
798
799 val = mvreg_read(pp, MVNETA_RXQ_CMD);
800 } while (val & 0xff);
801
802 /* Stop Tx port activity. Check port Tx activity. Issue stop
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100803 * command for active channels only
804 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300805 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
806
807 if (val != 0)
808 mvreg_write(pp, MVNETA_TXQ_CMD,
809 (val << MVNETA_TXQ_DISABLE_SHIFT));
810
811 /* Wait for all Tx activity to terminate. */
812 count = 0;
813 do {
814 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
815 netdev_warn(pp->dev,
816 "TIMEOUT for TX stopped status=0x%08x\n",
817 val);
818 break;
819 }
820 mdelay(1);
821
822 /* Check TX Command reg that all Txqs are stopped */
823 val = mvreg_read(pp, MVNETA_TXQ_CMD);
824
825 } while (val & 0xff);
826
827 /* Double check to verify that TX FIFO is empty */
828 count = 0;
829 do {
830 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
831 netdev_warn(pp->dev,
832 "TX FIFO empty timeout status=0x08%x\n",
833 val);
834 break;
835 }
836 mdelay(1);
837
838 val = mvreg_read(pp, MVNETA_PORT_STATUS);
839 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
840 (val & MVNETA_TX_IN_PRGRS));
841
842 udelay(200);
843}
844
845/* Enable the port by setting the port enable bit of the MAC control register */
846static void mvneta_port_enable(struct mvneta_port *pp)
847{
848 u32 val;
849
850 /* Enable port */
851 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
852 val |= MVNETA_GMAC0_PORT_ENABLE;
853 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
854}
855
856/* Disable the port and wait for about 200 usec before retuning */
857static void mvneta_port_disable(struct mvneta_port *pp)
858{
859 u32 val;
860
861 /* Reset the Enable bit in the Serial Control Register */
862 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
863 val &= ~MVNETA_GMAC0_PORT_ENABLE;
864 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
865
866 udelay(200);
867}
868
869/* Multicast tables methods */
870
871/* Set all entries in Unicast MAC Table; queue==-1 means reject all */
872static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
873{
874 int offset;
875 u32 val;
876
877 if (queue == -1) {
878 val = 0;
879 } else {
880 val = 0x1 | (queue << 1);
881 val |= (val << 24) | (val << 16) | (val << 8);
882 }
883
884 for (offset = 0; offset <= 0xc; offset += 4)
885 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
886}
887
888/* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
889static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
890{
891 int offset;
892 u32 val;
893
894 if (queue == -1) {
895 val = 0;
896 } else {
897 val = 0x1 | (queue << 1);
898 val |= (val << 24) | (val << 16) | (val << 8);
899 }
900
901 for (offset = 0; offset <= 0xfc; offset += 4)
902 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
903
904}
905
906/* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
907static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
908{
909 int offset;
910 u32 val;
911
912 if (queue == -1) {
913 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
914 val = 0;
915 } else {
916 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
917 val = 0x1 | (queue << 1);
918 val |= (val << 24) | (val << 16) | (val << 8);
919 }
920
921 for (offset = 0; offset <= 0xfc; offset += 4)
922 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
923}
924
925/* This method sets defaults to the NETA port:
926 * Clears interrupt Cause and Mask registers.
927 * Clears all MAC tables.
928 * Sets defaults to all registers.
929 * Resets RX and TX descriptor rings.
930 * Resets PHY.
931 * This method can be called after mvneta_port_down() to return the port
932 * settings to defaults.
933 */
934static void mvneta_defaults_set(struct mvneta_port *pp)
935{
936 int cpu;
937 int queue;
938 u32 val;
939
940 /* Clear all Cause registers */
941 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
942 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
943 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
944
945 /* Mask all interrupts */
946 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
947 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
948 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
949 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
950
951 /* Enable MBUS Retry bit16 */
952 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
953
954 /* Set CPU queue access map - all CPUs have access to all RX
Thomas Petazzoni6a20c172012-11-19 11:41:25 +0100955 * queues and to all TX queues
956 */
Maxime Ripard2502d0e2015-09-25 18:09:35 +0200957 for_each_present_cpu(cpu)
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300958 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
959 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
960 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
961
962 /* Reset RX and TX DMAs */
963 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
964 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
965
966 /* Disable Legacy WRR, Disable EJP, Release from reset */
967 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
968 for (queue = 0; queue < txq_number; queue++) {
969 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
970 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
971 }
972
973 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
974 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
975
976 /* Set Port Acceleration Mode */
977 val = MVNETA_ACC_MODE_EXT;
978 mvreg_write(pp, MVNETA_ACC_MODE, val);
979
980 /* Update val of portCfg register accordingly with all RxQueue types */
981 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
982 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
983
984 val = 0;
985 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
986 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
987
988 /* Build PORT_SDMA_CONFIG_REG */
989 val = 0;
990
991 /* Default burst size */
992 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
993 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
Thomas Petazzoni9ad8fef2013-07-29 15:21:28 +0200994 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300995
Thomas Petazzoni9ad8fef2013-07-29 15:21:28 +0200996#if defined(__BIG_ENDIAN)
997 val |= MVNETA_DESC_SWAP;
998#endif
Thomas Petazzonic5aff182012-08-17 14:04:28 +0300999
1000 /* Assign port SDMA configuration */
1001 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1002
Thomas Petazzoni71408602013-09-04 16:21:18 +02001003 /* Disable PHY polling in hardware, since we're using the
1004 * kernel phylib to do this.
1005 */
1006 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1007 val &= ~MVNETA_PHY_POLLING_ENABLE;
1008 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1009
Stas Sergeev898b2972015-04-01 20:32:49 +03001010 if (pp->use_inband_status) {
1011 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1012 val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
1013 MVNETA_GMAC_FORCE_LINK_DOWN |
1014 MVNETA_GMAC_AN_FLOW_CTRL_EN);
1015 val |= MVNETA_GMAC_INBAND_AN_ENABLE |
1016 MVNETA_GMAC_AN_SPEED_EN |
1017 MVNETA_GMAC_AN_DUPLEX_EN;
1018 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1019 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1020 val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
1021 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
Stas Sergeev538761b2015-06-18 18:36:03 +03001022 } else {
1023 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1024 val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
1025 MVNETA_GMAC_AN_SPEED_EN |
1026 MVNETA_GMAC_AN_DUPLEX_EN);
1027 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
Stas Sergeev898b2972015-04-01 20:32:49 +03001028 }
1029
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001030 mvneta_set_ucast_table(pp, -1);
1031 mvneta_set_special_mcast_table(pp, -1);
1032 mvneta_set_other_mcast_table(pp, -1);
1033
1034 /* Set port interrupt enable register - default enable all */
1035 mvreg_write(pp, MVNETA_INTR_ENABLE,
1036 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1037 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1038}
1039
1040/* Set max sizes for tx queues */
1041static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1042
1043{
1044 u32 val, size, mtu;
1045 int queue;
1046
1047 mtu = max_tx_size * 8;
1048 if (mtu > MVNETA_TX_MTU_MAX)
1049 mtu = MVNETA_TX_MTU_MAX;
1050
1051 /* Set MTU */
1052 val = mvreg_read(pp, MVNETA_TX_MTU);
1053 val &= ~MVNETA_TX_MTU_MAX;
1054 val |= mtu;
1055 mvreg_write(pp, MVNETA_TX_MTU, val);
1056
1057 /* TX token size and all TXQs token size must be larger that MTU */
1058 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1059
1060 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1061 if (size < mtu) {
1062 size = mtu;
1063 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1064 val |= size;
1065 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1066 }
1067 for (queue = 0; queue < txq_number; queue++) {
1068 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1069
1070 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1071 if (size < mtu) {
1072 size = mtu;
1073 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1074 val |= size;
1075 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1076 }
1077 }
1078}
1079
1080/* Set unicast address */
1081static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1082 int queue)
1083{
1084 unsigned int unicast_reg;
1085 unsigned int tbl_offset;
1086 unsigned int reg_offset;
1087
1088 /* Locate the Unicast table entry */
1089 last_nibble = (0xf & last_nibble);
1090
1091 /* offset from unicast tbl base */
1092 tbl_offset = (last_nibble / 4) * 4;
1093
1094 /* offset within the above reg */
1095 reg_offset = last_nibble % 4;
1096
1097 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1098
1099 if (queue == -1) {
1100 /* Clear accepts frame bit at specified unicast DA tbl entry */
1101 unicast_reg &= ~(0xff << (8 * reg_offset));
1102 } else {
1103 unicast_reg &= ~(0xff << (8 * reg_offset));
1104 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1105 }
1106
1107 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1108}
1109
1110/* Set mac address */
1111static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1112 int queue)
1113{
1114 unsigned int mac_h;
1115 unsigned int mac_l;
1116
1117 if (queue != -1) {
1118 mac_l = (addr[4] << 8) | (addr[5]);
1119 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1120 (addr[2] << 8) | (addr[3] << 0);
1121
1122 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1123 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1124 }
1125
1126 /* Accept frames of this address */
1127 mvneta_set_ucast_addr(pp, addr[5], queue);
1128}
1129
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001130/* Set the number of packets that will be received before RX interrupt
1131 * will be generated by HW.
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001132 */
1133static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1134 struct mvneta_rx_queue *rxq, u32 value)
1135{
1136 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1137 value | MVNETA_RXQ_NON_OCCUPIED(0));
1138 rxq->pkts_coal = value;
1139}
1140
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001141/* Set the time delay in usec before RX interrupt will be generated by
1142 * HW.
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001143 */
1144static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1145 struct mvneta_rx_queue *rxq, u32 value)
1146{
Thomas Petazzoni189dd622012-11-19 14:15:25 +01001147 u32 val;
1148 unsigned long clk_rate;
1149
1150 clk_rate = clk_get_rate(pp->clk);
1151 val = (clk_rate / 1000000) * value;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001152
1153 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1154 rxq->time_coal = value;
1155}
1156
1157/* Set threshold for TX_DONE pkts coalescing */
1158static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1159 struct mvneta_tx_queue *txq, u32 value)
1160{
1161 u32 val;
1162
1163 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1164
1165 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1166 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1167
1168 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1169
1170 txq->done_pkts_coal = value;
1171}
1172
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001173/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1174static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1175 u32 phys_addr, u32 cookie)
1176{
1177 rx_desc->buf_cookie = cookie;
1178 rx_desc->buf_phys_addr = phys_addr;
1179}
1180
1181/* Decrement sent descriptors counter */
1182static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1183 struct mvneta_tx_queue *txq,
1184 int sent_desc)
1185{
1186 u32 val;
1187
1188 /* Only 255 TX descriptors can be updated at once */
1189 while (sent_desc > 0xff) {
1190 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1191 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1192 sent_desc = sent_desc - 0xff;
1193 }
1194
1195 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1196 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1197}
1198
1199/* Get number of TX descriptors already sent by HW */
1200static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1201 struct mvneta_tx_queue *txq)
1202{
1203 u32 val;
1204 int sent_desc;
1205
1206 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1207 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1208 MVNETA_TXQ_SENT_DESC_SHIFT;
1209
1210 return sent_desc;
1211}
1212
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001213/* Get number of sent descriptors and decrement counter.
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001214 * The number of sent descriptors is returned.
1215 */
1216static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1217 struct mvneta_tx_queue *txq)
1218{
1219 int sent_desc;
1220
1221 /* Get number of sent descriptors */
1222 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1223
1224 /* Decrement sent descriptors counter */
1225 if (sent_desc)
1226 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1227
1228 return sent_desc;
1229}
1230
1231/* Set TXQ descriptors fields relevant for CSUM calculation */
1232static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1233 int ip_hdr_len, int l4_proto)
1234{
1235 u32 command;
1236
1237 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001238 * G_L4_chk, L4_type; required only for checksum
1239 * calculation
1240 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001241 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1242 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1243
Thomas Fitzsimmons0a198582014-07-08 19:44:07 -04001244 if (l3_proto == htons(ETH_P_IP))
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001245 command |= MVNETA_TXD_IP_CSUM;
1246 else
1247 command |= MVNETA_TX_L3_IP6;
1248
1249 if (l4_proto == IPPROTO_TCP)
1250 command |= MVNETA_TX_L4_CSUM_FULL;
1251 else if (l4_proto == IPPROTO_UDP)
1252 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1253 else
1254 command |= MVNETA_TX_L4_CSUM_NOT;
1255
1256 return command;
1257}
1258
1259
1260/* Display more error info */
1261static void mvneta_rx_error(struct mvneta_port *pp,
1262 struct mvneta_rx_desc *rx_desc)
1263{
1264 u32 status = rx_desc->status;
1265
willy tarreau54282132014-01-16 08:20:14 +01001266 if (!mvneta_rxq_desc_is_first_last(status)) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001267 netdev_err(pp->dev,
1268 "bad rx status %08x (buffer oversize), size=%d\n",
willy tarreau54282132014-01-16 08:20:14 +01001269 status, rx_desc->data_size);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001270 return;
1271 }
1272
1273 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1274 case MVNETA_RXD_ERR_CRC:
1275 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1276 status, rx_desc->data_size);
1277 break;
1278 case MVNETA_RXD_ERR_OVERRUN:
1279 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1280 status, rx_desc->data_size);
1281 break;
1282 case MVNETA_RXD_ERR_LEN:
1283 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1284 status, rx_desc->data_size);
1285 break;
1286 case MVNETA_RXD_ERR_RESOURCE:
1287 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1288 status, rx_desc->data_size);
1289 break;
1290 }
1291}
1292
willy tarreau54282132014-01-16 08:20:14 +01001293/* Handle RX checksum offload based on the descriptor's status */
1294static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001295 struct sk_buff *skb)
1296{
willy tarreau54282132014-01-16 08:20:14 +01001297 if ((status & MVNETA_RXD_L3_IP4) &&
1298 (status & MVNETA_RXD_L4_CSUM_OK)) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001299 skb->csum = 0;
1300 skb->ip_summed = CHECKSUM_UNNECESSARY;
1301 return;
1302 }
1303
1304 skb->ip_summed = CHECKSUM_NONE;
1305}
1306
willy tarreau6c498972014-01-16 08:20:12 +01001307/* Return tx queue pointer (find last set bit) according to <cause> returned
1308 * form tx_done reg. <cause> must not be null. The return value is always a
1309 * valid queue for matching the first one found in <cause>.
1310 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001311static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1312 u32 cause)
1313{
1314 int queue = fls(cause) - 1;
1315
willy tarreau6c498972014-01-16 08:20:12 +01001316 return &pp->txqs[queue];
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001317}
1318
1319/* Free tx queue skbuffs */
1320static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1321 struct mvneta_tx_queue *txq, int num)
1322{
1323 int i;
1324
1325 for (i = 0; i < num; i++) {
1326 struct mvneta_tx_desc *tx_desc = txq->descs +
1327 txq->txq_get_index;
1328 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1329
1330 mvneta_txq_inc_get(txq);
1331
Ezequiel Garcia2e3173a2014-05-30 13:40:07 -03001332 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1333 dma_unmap_single(pp->dev->dev.parent,
1334 tx_desc->buf_phys_addr,
1335 tx_desc->data_size, DMA_TO_DEVICE);
Ezequiel Garciaba7e46e2014-05-30 13:40:06 -03001336 if (!skb)
1337 continue;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001338 dev_kfree_skb_any(skb);
1339 }
1340}
1341
1342/* Handle end of transmission */
Arnaud Ebalardcd713192014-01-16 08:20:19 +01001343static void mvneta_txq_done(struct mvneta_port *pp,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001344 struct mvneta_tx_queue *txq)
1345{
1346 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1347 int tx_done;
1348
1349 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
Arnaud Ebalardcd713192014-01-16 08:20:19 +01001350 if (!tx_done)
1351 return;
1352
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001353 mvneta_txq_bufs_free(pp, txq, tx_done);
1354
1355 txq->count -= tx_done;
1356
1357 if (netif_tx_queue_stopped(nq)) {
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -03001358 if (txq->count <= txq->tx_wake_threshold)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001359 netif_tx_wake_queue(nq);
1360 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001361}
1362
willy tarreau8ec2cd42014-01-16 08:20:16 +01001363static void *mvneta_frag_alloc(const struct mvneta_port *pp)
1364{
1365 if (likely(pp->frag_size <= PAGE_SIZE))
1366 return netdev_alloc_frag(pp->frag_size);
1367 else
1368 return kmalloc(pp->frag_size, GFP_ATOMIC);
1369}
1370
1371static void mvneta_frag_free(const struct mvneta_port *pp, void *data)
1372{
1373 if (likely(pp->frag_size <= PAGE_SIZE))
Alexander Duyck13dc0d22015-05-06 21:12:14 -07001374 skb_free_frag(data);
willy tarreau8ec2cd42014-01-16 08:20:16 +01001375 else
1376 kfree(data);
1377}
1378
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001379/* Refill processing */
1380static int mvneta_rx_refill(struct mvneta_port *pp,
1381 struct mvneta_rx_desc *rx_desc)
1382
1383{
1384 dma_addr_t phys_addr;
willy tarreau8ec2cd42014-01-16 08:20:16 +01001385 void *data;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001386
willy tarreau8ec2cd42014-01-16 08:20:16 +01001387 data = mvneta_frag_alloc(pp);
1388 if (!data)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001389 return -ENOMEM;
1390
willy tarreau8ec2cd42014-01-16 08:20:16 +01001391 phys_addr = dma_map_single(pp->dev->dev.parent, data,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001392 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1393 DMA_FROM_DEVICE);
1394 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
willy tarreau8ec2cd42014-01-16 08:20:16 +01001395 mvneta_frag_free(pp, data);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001396 return -ENOMEM;
1397 }
1398
willy tarreau8ec2cd42014-01-16 08:20:16 +01001399 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001400 return 0;
1401}
1402
1403/* Handle tx checksum */
1404static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1405{
1406 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1407 int ip_hdr_len = 0;
Vlad Yasevich817dbfa2014-08-25 10:34:54 -04001408 __be16 l3_proto = vlan_get_protocol(skb);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001409 u8 l4_proto;
1410
Vlad Yasevich817dbfa2014-08-25 10:34:54 -04001411 if (l3_proto == htons(ETH_P_IP)) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001412 struct iphdr *ip4h = ip_hdr(skb);
1413
1414 /* Calculate IPv4 checksum and L4 checksum */
1415 ip_hdr_len = ip4h->ihl;
1416 l4_proto = ip4h->protocol;
Vlad Yasevich817dbfa2014-08-25 10:34:54 -04001417 } else if (l3_proto == htons(ETH_P_IPV6)) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001418 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1419
1420 /* Read l4_protocol from one of IPv6 extra headers */
1421 if (skb_network_header_len(skb) > 0)
1422 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1423 l4_proto = ip6h->nexthdr;
1424 } else
1425 return MVNETA_TX_L4_CSUM_NOT;
1426
1427 return mvneta_txq_desc_csum(skb_network_offset(skb),
Vlad Yasevich817dbfa2014-08-25 10:34:54 -04001428 l3_proto, ip_hdr_len, l4_proto);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001429 }
1430
1431 return MVNETA_TX_L4_CSUM_NOT;
1432}
1433
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001434/* Drop packets received by the RXQ and free buffers */
1435static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1436 struct mvneta_rx_queue *rxq)
1437{
1438 int rx_done, i;
1439
1440 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1441 for (i = 0; i < rxq->size; i++) {
1442 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
willy tarreau8ec2cd42014-01-16 08:20:16 +01001443 void *data = (void *)rx_desc->buf_cookie;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001444
willy tarreau8ec2cd42014-01-16 08:20:16 +01001445 mvneta_frag_free(pp, data);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001446 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
Ezequiel Garciaa328f3a2013-12-05 13:35:37 -03001447 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001448 }
1449
1450 if (rx_done)
1451 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1452}
1453
1454/* Main rx processing */
1455static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1456 struct mvneta_rx_queue *rxq)
1457{
Maxime Ripard12bb03b2015-09-25 18:09:36 +02001458 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001459 struct net_device *dev = pp->dev;
Simon Guinota84e3282015-07-19 13:00:53 +02001460 int rx_done;
willy tarreaudc4277d2014-01-16 08:20:07 +01001461 u32 rcvd_pkts = 0;
1462 u32 rcvd_bytes = 0;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001463
1464 /* Get number of received packets */
1465 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1466
1467 if (rx_todo > rx_done)
1468 rx_todo = rx_done;
1469
1470 rx_done = 0;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001471
1472 /* Fairness NAPI loop */
1473 while (rx_done < rx_todo) {
1474 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1475 struct sk_buff *skb;
willy tarreau8ec2cd42014-01-16 08:20:16 +01001476 unsigned char *data;
Simon Guinotdaf158d2015-09-15 22:41:21 +02001477 dma_addr_t phys_addr;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001478 u32 rx_status;
1479 int rx_bytes, err;
1480
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001481 rx_done++;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001482 rx_status = rx_desc->status;
willy tarreauf19fadf2014-01-16 08:20:17 +01001483 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
willy tarreau8ec2cd42014-01-16 08:20:16 +01001484 data = (unsigned char *)rx_desc->buf_cookie;
Simon Guinotdaf158d2015-09-15 22:41:21 +02001485 phys_addr = rx_desc->buf_phys_addr;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001486
willy tarreau54282132014-01-16 08:20:14 +01001487 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
willy tarreauf19fadf2014-01-16 08:20:17 +01001488 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1489 err_drop_frame:
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001490 dev->stats.rx_errors++;
1491 mvneta_rx_error(pp, rx_desc);
willy tarreau8ec2cd42014-01-16 08:20:16 +01001492 /* leave the descriptor untouched */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001493 continue;
1494 }
1495
willy tarreauf19fadf2014-01-16 08:20:17 +01001496 if (rx_bytes <= rx_copybreak) {
1497 /* better copy a small frame and not unmap the DMA region */
1498 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1499 if (unlikely(!skb))
1500 goto err_drop_frame;
1501
1502 dma_sync_single_range_for_cpu(dev->dev.parent,
1503 rx_desc->buf_phys_addr,
1504 MVNETA_MH_SIZE + NET_SKB_PAD,
1505 rx_bytes,
1506 DMA_FROM_DEVICE);
1507 memcpy(skb_put(skb, rx_bytes),
1508 data + MVNETA_MH_SIZE + NET_SKB_PAD,
1509 rx_bytes);
1510
1511 skb->protocol = eth_type_trans(skb, dev);
1512 mvneta_rx_csum(pp, rx_status, skb);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02001513 napi_gro_receive(&port->napi, skb);
willy tarreauf19fadf2014-01-16 08:20:17 +01001514
1515 rcvd_pkts++;
1516 rcvd_bytes += rx_bytes;
1517
1518 /* leave the descriptor and buffer untouched */
1519 continue;
1520 }
1521
Simon Guinota84e3282015-07-19 13:00:53 +02001522 /* Refill processing */
1523 err = mvneta_rx_refill(pp, rx_desc);
1524 if (err) {
1525 netdev_err(dev, "Linux processing - Can't refill\n");
1526 rxq->missed++;
1527 goto err_drop_frame;
1528 }
1529
willy tarreauf19fadf2014-01-16 08:20:17 +01001530 skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size);
1531 if (!skb)
1532 goto err_drop_frame;
1533
Simon Guinotdaf158d2015-09-15 22:41:21 +02001534 dma_unmap_single(dev->dev.parent, phys_addr,
Ezequiel Garciaa328f3a2013-12-05 13:35:37 -03001535 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001536
willy tarreaudc4277d2014-01-16 08:20:07 +01001537 rcvd_pkts++;
1538 rcvd_bytes += rx_bytes;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001539
1540 /* Linux processing */
willy tarreau8ec2cd42014-01-16 08:20:16 +01001541 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001542 skb_put(skb, rx_bytes);
1543
1544 skb->protocol = eth_type_trans(skb, dev);
1545
willy tarreau54282132014-01-16 08:20:14 +01001546 mvneta_rx_csum(pp, rx_status, skb);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001547
Maxime Ripard12bb03b2015-09-25 18:09:36 +02001548 napi_gro_receive(&port->napi, skb);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001549 }
1550
willy tarreaudc4277d2014-01-16 08:20:07 +01001551 if (rcvd_pkts) {
willy tarreau74c41b02014-01-16 08:20:08 +01001552 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1553
1554 u64_stats_update_begin(&stats->syncp);
1555 stats->rx_packets += rcvd_pkts;
1556 stats->rx_bytes += rcvd_bytes;
1557 u64_stats_update_end(&stats->syncp);
willy tarreaudc4277d2014-01-16 08:20:07 +01001558 }
1559
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001560 /* Update rxq management counters */
Simon Guinota84e3282015-07-19 13:00:53 +02001561 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001562
1563 return rx_done;
1564}
1565
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03001566static inline void
1567mvneta_tso_put_hdr(struct sk_buff *skb,
1568 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
1569{
1570 struct mvneta_tx_desc *tx_desc;
1571 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1572
1573 txq->tx_skb[txq->txq_put_index] = NULL;
1574 tx_desc = mvneta_txq_next_desc_get(txq);
1575 tx_desc->data_size = hdr_len;
1576 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
1577 tx_desc->command |= MVNETA_TXD_F_DESC;
1578 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
1579 txq->txq_put_index * TSO_HEADER_SIZE;
1580 mvneta_txq_inc_put(txq);
1581}
1582
1583static inline int
1584mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
1585 struct sk_buff *skb, char *data, int size,
1586 bool last_tcp, bool is_last)
1587{
1588 struct mvneta_tx_desc *tx_desc;
1589
1590 tx_desc = mvneta_txq_next_desc_get(txq);
1591 tx_desc->data_size = size;
1592 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
1593 size, DMA_TO_DEVICE);
1594 if (unlikely(dma_mapping_error(dev->dev.parent,
1595 tx_desc->buf_phys_addr))) {
1596 mvneta_txq_desc_put(txq);
1597 return -ENOMEM;
1598 }
1599
1600 tx_desc->command = 0;
1601 txq->tx_skb[txq->txq_put_index] = NULL;
1602
1603 if (last_tcp) {
1604 /* last descriptor in the TCP packet */
1605 tx_desc->command = MVNETA_TXD_L_DESC;
1606
1607 /* last descriptor in SKB */
1608 if (is_last)
1609 txq->tx_skb[txq->txq_put_index] = skb;
1610 }
1611 mvneta_txq_inc_put(txq);
1612 return 0;
1613}
1614
1615static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
1616 struct mvneta_tx_queue *txq)
1617{
1618 int total_len, data_left;
1619 int desc_count = 0;
1620 struct mvneta_port *pp = netdev_priv(dev);
1621 struct tso_t tso;
1622 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1623 int i;
1624
1625 /* Count needed descriptors */
1626 if ((txq->count + tso_count_descs(skb)) >= txq->size)
1627 return 0;
1628
1629 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
1630 pr_info("*** Is this even possible???!?!?\n");
1631 return 0;
1632 }
1633
1634 /* Initialize the TSO handler, and prepare the first payload */
1635 tso_start(skb, &tso);
1636
1637 total_len = skb->len - hdr_len;
1638 while (total_len > 0) {
1639 char *hdr;
1640
1641 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
1642 total_len -= data_left;
1643 desc_count++;
1644
1645 /* prepare packet headers: MAC + IP + TCP */
1646 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
1647 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
1648
1649 mvneta_tso_put_hdr(skb, pp, txq);
1650
1651 while (data_left > 0) {
1652 int size;
1653 desc_count++;
1654
1655 size = min_t(int, tso.size, data_left);
1656
1657 if (mvneta_tso_put_data(dev, txq, skb,
1658 tso.data, size,
1659 size == data_left,
1660 total_len == 0))
1661 goto err_release;
1662 data_left -= size;
1663
1664 tso_build_data(skb, &tso, size);
1665 }
1666 }
1667
1668 return desc_count;
1669
1670err_release:
1671 /* Release all used data descriptors; header descriptors must not
1672 * be DMA-unmapped.
1673 */
1674 for (i = desc_count - 1; i >= 0; i--) {
1675 struct mvneta_tx_desc *tx_desc = txq->descs + i;
Ezequiel Garcia2e3173a2014-05-30 13:40:07 -03001676 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03001677 dma_unmap_single(pp->dev->dev.parent,
1678 tx_desc->buf_phys_addr,
1679 tx_desc->data_size,
1680 DMA_TO_DEVICE);
1681 mvneta_txq_desc_put(txq);
1682 }
1683 return 0;
1684}
1685
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001686/* Handle tx fragmentation processing */
1687static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1688 struct mvneta_tx_queue *txq)
1689{
1690 struct mvneta_tx_desc *tx_desc;
Ezequiel Garcia3d4ea022014-05-22 20:06:57 -03001691 int i, nr_frags = skb_shinfo(skb)->nr_frags;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001692
Ezequiel Garcia3d4ea022014-05-22 20:06:57 -03001693 for (i = 0; i < nr_frags; i++) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001694 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1695 void *addr = page_address(frag->page.p) + frag->page_offset;
1696
1697 tx_desc = mvneta_txq_next_desc_get(txq);
1698 tx_desc->data_size = frag->size;
1699
1700 tx_desc->buf_phys_addr =
1701 dma_map_single(pp->dev->dev.parent, addr,
1702 tx_desc->data_size, DMA_TO_DEVICE);
1703
1704 if (dma_mapping_error(pp->dev->dev.parent,
1705 tx_desc->buf_phys_addr)) {
1706 mvneta_txq_desc_put(txq);
1707 goto error;
1708 }
1709
Ezequiel Garcia3d4ea022014-05-22 20:06:57 -03001710 if (i == nr_frags - 1) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001711 /* Last descriptor */
1712 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001713 txq->tx_skb[txq->txq_put_index] = skb;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001714 } else {
1715 /* Descriptor in the middle: Not First, Not Last */
1716 tx_desc->command = 0;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001717 txq->tx_skb[txq->txq_put_index] = NULL;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001718 }
Ezequiel Garcia3d4ea022014-05-22 20:06:57 -03001719 mvneta_txq_inc_put(txq);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001720 }
1721
1722 return 0;
1723
1724error:
1725 /* Release all descriptors that were used to map fragments of
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001726 * this packet, as well as the corresponding DMA mappings
1727 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001728 for (i = i - 1; i >= 0; i--) {
1729 tx_desc = txq->descs + i;
1730 dma_unmap_single(pp->dev->dev.parent,
1731 tx_desc->buf_phys_addr,
1732 tx_desc->data_size,
1733 DMA_TO_DEVICE);
1734 mvneta_txq_desc_put(txq);
1735 }
1736
1737 return -ENOMEM;
1738}
1739
1740/* Main tx processing */
1741static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1742{
1743 struct mvneta_port *pp = netdev_priv(dev);
Willy Tarreauee40a112013-04-11 23:00:37 +02001744 u16 txq_id = skb_get_queue_mapping(skb);
1745 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001746 struct mvneta_tx_desc *tx_desc;
Eric Dumazet5f478b42014-12-02 04:30:59 -08001747 int len = skb->len;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001748 int frags = 0;
1749 u32 tx_cmd;
1750
1751 if (!netif_running(dev))
1752 goto out;
1753
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03001754 if (skb_is_gso(skb)) {
1755 frags = mvneta_tx_tso(skb, dev, txq);
1756 goto out;
1757 }
1758
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001759 frags = skb_shinfo(skb)->nr_frags + 1;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001760
1761 /* Get a descriptor for the first part of the packet */
1762 tx_desc = mvneta_txq_next_desc_get(txq);
1763
1764 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1765
1766 tx_desc->data_size = skb_headlen(skb);
1767
1768 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1769 tx_desc->data_size,
1770 DMA_TO_DEVICE);
1771 if (unlikely(dma_mapping_error(dev->dev.parent,
1772 tx_desc->buf_phys_addr))) {
1773 mvneta_txq_desc_put(txq);
1774 frags = 0;
1775 goto out;
1776 }
1777
1778 if (frags == 1) {
1779 /* First and Last descriptor */
1780 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1781 tx_desc->command = tx_cmd;
1782 txq->tx_skb[txq->txq_put_index] = skb;
1783 mvneta_txq_inc_put(txq);
1784 } else {
1785 /* First but not Last */
1786 tx_cmd |= MVNETA_TXD_F_DESC;
1787 txq->tx_skb[txq->txq_put_index] = NULL;
1788 mvneta_txq_inc_put(txq);
1789 tx_desc->command = tx_cmd;
1790 /* Continue with other skb fragments */
1791 if (mvneta_tx_frag_process(pp, skb, txq)) {
1792 dma_unmap_single(dev->dev.parent,
1793 tx_desc->buf_phys_addr,
1794 tx_desc->data_size,
1795 DMA_TO_DEVICE);
1796 mvneta_txq_desc_put(txq);
1797 frags = 0;
1798 goto out;
1799 }
1800 }
1801
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001802out:
1803 if (frags > 0) {
willy tarreau74c41b02014-01-16 08:20:08 +01001804 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
Ezequiel Garciae19d2dd2014-05-19 13:59:54 -03001805 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
1806
1807 txq->count += frags;
1808 mvneta_txq_pend_desc_add(pp, txq, frags);
1809
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -03001810 if (txq->count >= txq->tx_stop_threshold)
Ezequiel Garciae19d2dd2014-05-19 13:59:54 -03001811 netif_tx_stop_queue(nq);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001812
willy tarreau74c41b02014-01-16 08:20:08 +01001813 u64_stats_update_begin(&stats->syncp);
1814 stats->tx_packets++;
Eric Dumazet5f478b42014-12-02 04:30:59 -08001815 stats->tx_bytes += len;
willy tarreau74c41b02014-01-16 08:20:08 +01001816 u64_stats_update_end(&stats->syncp);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001817 } else {
1818 dev->stats.tx_dropped++;
1819 dev_kfree_skb_any(skb);
1820 }
1821
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001822 return NETDEV_TX_OK;
1823}
1824
1825
1826/* Free tx resources, when resetting a port */
1827static void mvneta_txq_done_force(struct mvneta_port *pp,
1828 struct mvneta_tx_queue *txq)
1829
1830{
1831 int tx_done = txq->count;
1832
1833 mvneta_txq_bufs_free(pp, txq, tx_done);
1834
1835 /* reset txq */
1836 txq->count = 0;
1837 txq->txq_put_index = 0;
1838 txq->txq_get_index = 0;
1839}
1840
willy tarreau6c498972014-01-16 08:20:12 +01001841/* Handle tx done - called in softirq context. The <cause_tx_done> argument
1842 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
1843 */
Arnaud Ebalard0713a862014-01-16 08:20:18 +01001844static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001845{
1846 struct mvneta_tx_queue *txq;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001847 struct netdev_queue *nq;
1848
willy tarreau6c498972014-01-16 08:20:12 +01001849 while (cause_tx_done) {
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001850 txq = mvneta_tx_done_policy(pp, cause_tx_done);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001851
1852 nq = netdev_get_tx_queue(pp->dev, txq->id);
1853 __netif_tx_lock(nq, smp_processor_id());
1854
Arnaud Ebalard0713a862014-01-16 08:20:18 +01001855 if (txq->count)
1856 mvneta_txq_done(pp, txq);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001857
1858 __netif_tx_unlock(nq);
1859 cause_tx_done &= ~((1 << txq->id));
1860 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001861}
1862
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01001863/* Compute crc8 of the specified address, using a unique algorithm ,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03001864 * according to hw spec, different than generic crc8 algorithm
1865 */
1866static int mvneta_addr_crc(unsigned char *addr)
1867{
1868 int crc = 0;
1869 int i;
1870
1871 for (i = 0; i < ETH_ALEN; i++) {
1872 int j;
1873
1874 crc = (crc ^ addr[i]) << 8;
1875 for (j = 7; j >= 0; j--) {
1876 if (crc & (0x100 << j))
1877 crc ^= 0x107 << j;
1878 }
1879 }
1880
1881 return crc;
1882}
1883
1884/* This method controls the net device special MAC multicast support.
1885 * The Special Multicast Table for MAC addresses supports MAC of the form
1886 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1887 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1888 * Table entries in the DA-Filter table. This method set the Special
1889 * Multicast Table appropriate entry.
1890 */
1891static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1892 unsigned char last_byte,
1893 int queue)
1894{
1895 unsigned int smc_table_reg;
1896 unsigned int tbl_offset;
1897 unsigned int reg_offset;
1898
1899 /* Register offset from SMC table base */
1900 tbl_offset = (last_byte / 4);
1901 /* Entry offset within the above reg */
1902 reg_offset = last_byte % 4;
1903
1904 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1905 + tbl_offset * 4));
1906
1907 if (queue == -1)
1908 smc_table_reg &= ~(0xff << (8 * reg_offset));
1909 else {
1910 smc_table_reg &= ~(0xff << (8 * reg_offset));
1911 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1912 }
1913
1914 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1915 smc_table_reg);
1916}
1917
1918/* This method controls the network device Other MAC multicast support.
1919 * The Other Multicast Table is used for multicast of another type.
1920 * A CRC-8 is used as an index to the Other Multicast Table entries
1921 * in the DA-Filter table.
1922 * The method gets the CRC-8 value from the calling routine and
1923 * sets the Other Multicast Table appropriate entry according to the
1924 * specified CRC-8 .
1925 */
1926static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1927 unsigned char crc8,
1928 int queue)
1929{
1930 unsigned int omc_table_reg;
1931 unsigned int tbl_offset;
1932 unsigned int reg_offset;
1933
1934 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1935 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1936
1937 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
1938
1939 if (queue == -1) {
1940 /* Clear accepts frame bit at specified Other DA table entry */
1941 omc_table_reg &= ~(0xff << (8 * reg_offset));
1942 } else {
1943 omc_table_reg &= ~(0xff << (8 * reg_offset));
1944 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1945 }
1946
1947 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
1948}
1949
1950/* The network device supports multicast using two tables:
1951 * 1) Special Multicast Table for MAC addresses of the form
1952 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1953 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1954 * Table entries in the DA-Filter table.
1955 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1956 * is used as an index to the Other Multicast Table entries in the
1957 * DA-Filter table.
1958 */
1959static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
1960 int queue)
1961{
1962 unsigned char crc_result = 0;
1963
1964 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
1965 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
1966 return 0;
1967 }
1968
1969 crc_result = mvneta_addr_crc(p_addr);
1970 if (queue == -1) {
1971 if (pp->mcast_count[crc_result] == 0) {
1972 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
1973 crc_result);
1974 return -EINVAL;
1975 }
1976
1977 pp->mcast_count[crc_result]--;
1978 if (pp->mcast_count[crc_result] != 0) {
1979 netdev_info(pp->dev,
1980 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1981 pp->mcast_count[crc_result], crc_result);
1982 return -EINVAL;
1983 }
1984 } else
1985 pp->mcast_count[crc_result]++;
1986
1987 mvneta_set_other_mcast_addr(pp, crc_result, queue);
1988
1989 return 0;
1990}
1991
1992/* Configure Fitering mode of Ethernet port */
1993static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
1994 int is_promisc)
1995{
1996 u32 port_cfg_reg, val;
1997
1998 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
1999
2000 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2001
2002 /* Set / Clear UPM bit in port configuration register */
2003 if (is_promisc) {
2004 /* Accept all Unicast addresses */
2005 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2006 val |= MVNETA_FORCE_UNI;
2007 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2008 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2009 } else {
2010 /* Reject all Unicast addresses */
2011 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2012 val &= ~MVNETA_FORCE_UNI;
2013 }
2014
2015 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2016 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2017}
2018
2019/* register unicast and multicast addresses */
2020static void mvneta_set_rx_mode(struct net_device *dev)
2021{
2022 struct mvneta_port *pp = netdev_priv(dev);
2023 struct netdev_hw_addr *ha;
2024
2025 if (dev->flags & IFF_PROMISC) {
2026 /* Accept all: Multicast + Unicast */
2027 mvneta_rx_unicast_promisc_set(pp, 1);
2028 mvneta_set_ucast_table(pp, rxq_def);
2029 mvneta_set_special_mcast_table(pp, rxq_def);
2030 mvneta_set_other_mcast_table(pp, rxq_def);
2031 } else {
2032 /* Accept single Unicast */
2033 mvneta_rx_unicast_promisc_set(pp, 0);
2034 mvneta_set_ucast_table(pp, -1);
2035 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2036
2037 if (dev->flags & IFF_ALLMULTI) {
2038 /* Accept all multicast */
2039 mvneta_set_special_mcast_table(pp, rxq_def);
2040 mvneta_set_other_mcast_table(pp, rxq_def);
2041 } else {
2042 /* Accept only initialized multicast */
2043 mvneta_set_special_mcast_table(pp, -1);
2044 mvneta_set_other_mcast_table(pp, -1);
2045
2046 if (!netdev_mc_empty(dev)) {
2047 netdev_for_each_mc_addr(ha, dev) {
2048 mvneta_mcast_addr_set(pp, ha->addr,
2049 rxq_def);
2050 }
2051 }
2052 }
2053 }
2054}
2055
2056/* Interrupt handling - the callback for request_irq() */
2057static irqreturn_t mvneta_isr(int irq, void *dev_id)
2058{
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002059 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002060
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002061 disable_percpu_irq(port->pp->dev->irq);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002062 napi_schedule(&port->napi);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002063
2064 return IRQ_HANDLED;
2065}
2066
Stas Sergeev898b2972015-04-01 20:32:49 +03002067static int mvneta_fixed_link_update(struct mvneta_port *pp,
2068 struct phy_device *phy)
2069{
2070 struct fixed_phy_status status;
2071 struct fixed_phy_status changed = {};
2072 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2073
2074 status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
2075 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
2076 status.speed = SPEED_1000;
2077 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
2078 status.speed = SPEED_100;
2079 else
2080 status.speed = SPEED_10;
2081 status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
2082 changed.link = 1;
2083 changed.speed = 1;
2084 changed.duplex = 1;
2085 fixed_phy_update_state(phy, &status, &changed);
2086 return 0;
2087}
2088
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002089/* NAPI handler
2090 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2091 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2092 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2093 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2094 * Each CPU has its own causeRxTx register
2095 */
2096static int mvneta_poll(struct napi_struct *napi, int budget)
2097{
2098 int rx_done = 0;
2099 u32 cause_rx_tx;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002100 struct mvneta_port *pp = netdev_priv(napi->dev);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002101 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002102
2103 if (!netif_running(pp->dev)) {
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002104 napi_complete(&port->napi);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002105 return rx_done;
2106 }
2107
2108 /* Read cause register */
Stas Sergeev898b2972015-04-01 20:32:49 +03002109 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2110 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2111 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2112
2113 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2114 if (pp->use_inband_status && (cause_misc &
2115 (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2116 MVNETA_CAUSE_LINK_CHANGE |
2117 MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
2118 mvneta_fixed_link_update(pp, pp->phy_dev);
2119 }
2120 }
willy tarreau71f6d1b2014-01-16 08:20:11 +01002121
2122 /* Release Tx descriptors */
2123 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
Arnaud Ebalard0713a862014-01-16 08:20:18 +01002124 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
willy tarreau71f6d1b2014-01-16 08:20:11 +01002125 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2126 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002127
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01002128 /* For the case where the last mvneta_poll did not process all
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002129 * RX packets
2130 */
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002131 cause_rx_tx |= port->cause_rx_tx;
Maxime Ripardd8936652015-09-25 18:09:37 +02002132 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
2133 budget -= rx_done;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002134
2135 if (budget > 0) {
2136 cause_rx_tx = 0;
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002137 napi_complete(&port->napi);
2138 enable_percpu_irq(pp->dev->irq, 0);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002139 }
2140
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002141 port->cause_rx_tx = cause_rx_tx;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002142 return rx_done;
2143}
2144
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002145/* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2146static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2147 int num)
2148{
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002149 int i;
2150
2151 for (i = 0; i < num; i++) {
willy tarreaua1a65ab2014-01-16 08:20:13 +01002152 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2153 if (mvneta_rx_refill(pp, rxq->descs + i) != 0) {
2154 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002155 __func__, rxq->id, i, num);
2156 break;
2157 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002158 }
2159
2160 /* Add this number of RX descriptors as non occupied (ready to
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01002161 * get packets)
2162 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002163 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2164
2165 return i;
2166}
2167
2168/* Free all packets pending transmit from all TXQs and reset TX port */
2169static void mvneta_tx_reset(struct mvneta_port *pp)
2170{
2171 int queue;
2172
Ezequiel Garcia96728502014-05-22 20:06:59 -03002173 /* free the skb's in the tx ring */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002174 for (queue = 0; queue < txq_number; queue++)
2175 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2176
2177 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2178 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2179}
2180
2181static void mvneta_rx_reset(struct mvneta_port *pp)
2182{
2183 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2184 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2185}
2186
2187/* Rx/Tx queue initialization/cleanup methods */
2188
2189/* Create a specified RX queue */
2190static int mvneta_rxq_init(struct mvneta_port *pp,
2191 struct mvneta_rx_queue *rxq)
2192
2193{
2194 rxq->size = pp->rx_ring_size;
2195
2196 /* Allocate memory for RX descriptors */
2197 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2198 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2199 &rxq->descs_phys, GFP_KERNEL);
Joe Perchesd0320f72013-03-14 13:07:21 +00002200 if (rxq->descs == NULL)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002201 return -ENOMEM;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002202
2203 BUG_ON(rxq->descs !=
2204 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2205
2206 rxq->last_desc = rxq->size - 1;
2207
2208 /* Set Rx descriptors queue starting address */
2209 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2210 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2211
2212 /* Set Offset */
2213 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2214
2215 /* Set coalescing pkts and time */
2216 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2217 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2218
2219 /* Fill RXQ with buffers from RX pool */
2220 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2221 mvneta_rxq_bm_disable(pp, rxq);
2222 mvneta_rxq_fill(pp, rxq, rxq->size);
2223
2224 return 0;
2225}
2226
2227/* Cleanup Rx queue */
2228static void mvneta_rxq_deinit(struct mvneta_port *pp,
2229 struct mvneta_rx_queue *rxq)
2230{
2231 mvneta_rxq_drop_pkts(pp, rxq);
2232
2233 if (rxq->descs)
2234 dma_free_coherent(pp->dev->dev.parent,
2235 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2236 rxq->descs,
2237 rxq->descs_phys);
2238
2239 rxq->descs = NULL;
2240 rxq->last_desc = 0;
2241 rxq->next_desc_to_proc = 0;
2242 rxq->descs_phys = 0;
2243}
2244
2245/* Create and initialize a tx queue */
2246static int mvneta_txq_init(struct mvneta_port *pp,
2247 struct mvneta_tx_queue *txq)
2248{
2249 txq->size = pp->tx_ring_size;
2250
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -03002251 /* A queue must always have room for at least one skb.
2252 * Therefore, stop the queue when the free entries reaches
2253 * the maximum number of descriptors per skb.
2254 */
2255 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2256 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2257
2258
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002259 /* Allocate memory for TX descriptors */
2260 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2261 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2262 &txq->descs_phys, GFP_KERNEL);
Joe Perchesd0320f72013-03-14 13:07:21 +00002263 if (txq->descs == NULL)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002264 return -ENOMEM;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002265
2266 /* Make sure descriptor address is cache line size aligned */
2267 BUG_ON(txq->descs !=
2268 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2269
2270 txq->last_desc = txq->size - 1;
2271
2272 /* Set maximum bandwidth for enabled TXQs */
2273 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2274 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2275
2276 /* Set Tx descriptors queue starting address */
2277 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2278 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2279
2280 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2281 if (txq->tx_skb == NULL) {
2282 dma_free_coherent(pp->dev->dev.parent,
2283 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2284 txq->descs, txq->descs_phys);
2285 return -ENOMEM;
2286 }
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03002287
2288 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2289 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2290 txq->size * TSO_HEADER_SIZE,
2291 &txq->tso_hdrs_phys, GFP_KERNEL);
2292 if (txq->tso_hdrs == NULL) {
2293 kfree(txq->tx_skb);
2294 dma_free_coherent(pp->dev->dev.parent,
2295 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2296 txq->descs, txq->descs_phys);
2297 return -ENOMEM;
2298 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002299 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2300
2301 return 0;
2302}
2303
2304/* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2305static void mvneta_txq_deinit(struct mvneta_port *pp,
2306 struct mvneta_tx_queue *txq)
2307{
2308 kfree(txq->tx_skb);
2309
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03002310 if (txq->tso_hdrs)
2311 dma_free_coherent(pp->dev->dev.parent,
2312 txq->size * TSO_HEADER_SIZE,
2313 txq->tso_hdrs, txq->tso_hdrs_phys);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002314 if (txq->descs)
2315 dma_free_coherent(pp->dev->dev.parent,
2316 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2317 txq->descs, txq->descs_phys);
2318
2319 txq->descs = NULL;
2320 txq->last_desc = 0;
2321 txq->next_desc_to_proc = 0;
2322 txq->descs_phys = 0;
2323
2324 /* Set minimum bandwidth for disabled TXQs */
2325 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2326 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2327
2328 /* Set Tx descriptors queue starting address and size */
2329 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2330 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2331}
2332
2333/* Cleanup all Tx queues */
2334static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2335{
2336 int queue;
2337
2338 for (queue = 0; queue < txq_number; queue++)
2339 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2340}
2341
2342/* Cleanup all Rx queues */
2343static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2344{
Maxime Ripardd8936652015-09-25 18:09:37 +02002345 mvneta_rxq_deinit(pp, &pp->rxqs[rxq_def]);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002346}
2347
2348
2349/* Init all Rx queues */
2350static int mvneta_setup_rxqs(struct mvneta_port *pp)
2351{
Maxime Ripardd8936652015-09-25 18:09:37 +02002352 int err = mvneta_rxq_init(pp, &pp->rxqs[rxq_def]);
2353 if (err) {
2354 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2355 __func__, rxq_def);
2356 mvneta_cleanup_rxqs(pp);
2357 return err;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002358 }
2359
2360 return 0;
2361}
2362
2363/* Init all tx queues */
2364static int mvneta_setup_txqs(struct mvneta_port *pp)
2365{
2366 int queue;
2367
2368 for (queue = 0; queue < txq_number; queue++) {
2369 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2370 if (err) {
2371 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2372 __func__, queue);
2373 mvneta_cleanup_txqs(pp);
2374 return err;
2375 }
2376 }
2377
2378 return 0;
2379}
2380
2381static void mvneta_start_dev(struct mvneta_port *pp)
2382{
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002383 unsigned int cpu;
2384
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002385 mvneta_max_rx_size_set(pp, pp->pkt_size);
2386 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2387
2388 /* start the Rx/Tx activity */
2389 mvneta_port_enable(pp);
2390
2391 /* Enable polling on the port */
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002392 for_each_present_cpu(cpu) {
2393 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2394
2395 napi_enable(&port->napi);
2396 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002397
2398 /* Unmask interrupts */
2399 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
Stas Sergeev898b2972015-04-01 20:32:49 +03002400 MVNETA_RX_INTR_MASK(rxq_number) |
2401 MVNETA_TX_INTR_MASK(txq_number) |
2402 MVNETA_MISCINTR_INTR_MASK);
2403 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2404 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2405 MVNETA_CAUSE_LINK_CHANGE |
2406 MVNETA_CAUSE_PSC_SYNC_CHANGE);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002407
2408 phy_start(pp->phy_dev);
2409 netif_tx_start_all_queues(pp->dev);
2410}
2411
2412static void mvneta_stop_dev(struct mvneta_port *pp)
2413{
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002414 unsigned int cpu;
2415
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002416 phy_stop(pp->phy_dev);
2417
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002418 for_each_present_cpu(cpu) {
2419 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2420
2421 napi_disable(&port->napi);
2422 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002423
2424 netif_carrier_off(pp->dev);
2425
2426 mvneta_port_down(pp);
2427 netif_tx_stop_all_queues(pp->dev);
2428
2429 /* Stop the port activity */
2430 mvneta_port_disable(pp);
2431
2432 /* Clear all ethernet port interrupts */
2433 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2434 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2435
2436 /* Mask all ethernet port interrupts */
2437 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2438 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2439 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2440
2441 mvneta_tx_reset(pp);
2442 mvneta_rx_reset(pp);
2443}
2444
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002445/* Return positive if MTU is valid */
2446static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2447{
2448 if (mtu < 68) {
2449 netdev_err(dev, "cannot change mtu to less than 68\n");
2450 return -EINVAL;
2451 }
2452
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01002453 /* 9676 == 9700 - 20 and rounding to 8 */
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002454 if (mtu > 9676) {
2455 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2456 mtu = 9676;
2457 }
2458
2459 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2460 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2461 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2462 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2463 }
2464
2465 return mtu;
2466}
2467
2468/* Change the device mtu */
2469static int mvneta_change_mtu(struct net_device *dev, int mtu)
2470{
2471 struct mvneta_port *pp = netdev_priv(dev);
2472 int ret;
2473
2474 mtu = mvneta_check_mtu_valid(dev, mtu);
2475 if (mtu < 0)
2476 return -EINVAL;
2477
2478 dev->mtu = mtu;
2479
Simon Guinotb65657f2015-06-30 16:20:22 +02002480 if (!netif_running(dev)) {
2481 netdev_update_features(dev);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002482 return 0;
Simon Guinotb65657f2015-06-30 16:20:22 +02002483 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002484
Thomas Petazzoni6a20c172012-11-19 11:41:25 +01002485 /* The interface is running, so we have to force a
Ezequiel Garciaa92dbd92014-05-22 20:06:58 -03002486 * reallocation of the queues
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002487 */
2488 mvneta_stop_dev(pp);
2489
2490 mvneta_cleanup_txqs(pp);
2491 mvneta_cleanup_rxqs(pp);
2492
Ezequiel Garciaa92dbd92014-05-22 20:06:58 -03002493 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
willy tarreau8ec2cd42014-01-16 08:20:16 +01002494 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2495 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002496
2497 ret = mvneta_setup_rxqs(pp);
2498 if (ret) {
Ezequiel Garciaa92dbd92014-05-22 20:06:58 -03002499 netdev_err(dev, "unable to setup rxqs after MTU change\n");
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002500 return ret;
2501 }
2502
Ezequiel Garciaa92dbd92014-05-22 20:06:58 -03002503 ret = mvneta_setup_txqs(pp);
2504 if (ret) {
2505 netdev_err(dev, "unable to setup txqs after MTU change\n");
2506 return ret;
2507 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002508
2509 mvneta_start_dev(pp);
2510 mvneta_port_up(pp);
2511
Simon Guinotb65657f2015-06-30 16:20:22 +02002512 netdev_update_features(dev);
2513
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002514 return 0;
2515}
2516
Simon Guinotb65657f2015-06-30 16:20:22 +02002517static netdev_features_t mvneta_fix_features(struct net_device *dev,
2518 netdev_features_t features)
2519{
2520 struct mvneta_port *pp = netdev_priv(dev);
2521
2522 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
2523 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
2524 netdev_info(dev,
2525 "Disable IP checksum for MTU greater than %dB\n",
2526 pp->tx_csum_limit);
2527 }
2528
2529 return features;
2530}
2531
Thomas Petazzoni8cc3e432013-06-04 04:52:23 +00002532/* Get mac address */
2533static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2534{
2535 u32 mac_addr_l, mac_addr_h;
2536
2537 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2538 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2539 addr[0] = (mac_addr_h >> 24) & 0xFF;
2540 addr[1] = (mac_addr_h >> 16) & 0xFF;
2541 addr[2] = (mac_addr_h >> 8) & 0xFF;
2542 addr[3] = mac_addr_h & 0xFF;
2543 addr[4] = (mac_addr_l >> 8) & 0xFF;
2544 addr[5] = mac_addr_l & 0xFF;
2545}
2546
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002547/* Handle setting mac address */
2548static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2549{
2550 struct mvneta_port *pp = netdev_priv(dev);
Ezequiel Garciae68de362014-05-22 20:07:00 -03002551 struct sockaddr *sockaddr = addr;
2552 int ret;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002553
Ezequiel Garciae68de362014-05-22 20:07:00 -03002554 ret = eth_prepare_mac_addr_change(dev, addr);
2555 if (ret < 0)
2556 return ret;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002557 /* Remove previous address table entry */
2558 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2559
2560 /* Set new addr in hw */
Ezequiel Garciae68de362014-05-22 20:07:00 -03002561 mvneta_mac_addr_set(pp, sockaddr->sa_data, rxq_def);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002562
Ezequiel Garciae68de362014-05-22 20:07:00 -03002563 eth_commit_mac_addr_change(dev, addr);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002564 return 0;
2565}
2566
2567static void mvneta_adjust_link(struct net_device *ndev)
2568{
2569 struct mvneta_port *pp = netdev_priv(ndev);
2570 struct phy_device *phydev = pp->phy_dev;
2571 int status_change = 0;
2572
2573 if (phydev->link) {
2574 if ((pp->speed != phydev->speed) ||
2575 (pp->duplex != phydev->duplex)) {
2576 u32 val;
2577
2578 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2579 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2580 MVNETA_GMAC_CONFIG_GMII_SPEED |
Stas Sergeev898b2972015-04-01 20:32:49 +03002581 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002582
2583 if (phydev->duplex)
2584 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2585
2586 if (phydev->speed == SPEED_1000)
2587 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
Thomas Petazzoni4d12bc62014-07-08 10:49:43 +02002588 else if (phydev->speed == SPEED_100)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002589 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2590
2591 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2592
2593 pp->duplex = phydev->duplex;
2594 pp->speed = phydev->speed;
2595 }
2596 }
2597
2598 if (phydev->link != pp->link) {
2599 if (!phydev->link) {
2600 pp->duplex = -1;
2601 pp->speed = 0;
2602 }
2603
2604 pp->link = phydev->link;
2605 status_change = 1;
2606 }
2607
2608 if (status_change) {
2609 if (phydev->link) {
Stas Sergeev898b2972015-04-01 20:32:49 +03002610 if (!pp->use_inband_status) {
2611 u32 val = mvreg_read(pp,
2612 MVNETA_GMAC_AUTONEG_CONFIG);
2613 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
2614 val |= MVNETA_GMAC_FORCE_LINK_PASS;
2615 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2616 val);
2617 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002618 mvneta_port_up(pp);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002619 } else {
Stas Sergeev898b2972015-04-01 20:32:49 +03002620 if (!pp->use_inband_status) {
2621 u32 val = mvreg_read(pp,
2622 MVNETA_GMAC_AUTONEG_CONFIG);
2623 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
2624 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
2625 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2626 val);
2627 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002628 mvneta_port_down(pp);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002629 }
Ezequiel Garcia0089b742014-10-31 12:57:20 -03002630 phy_print_status(phydev);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002631 }
2632}
2633
2634static int mvneta_mdio_probe(struct mvneta_port *pp)
2635{
2636 struct phy_device *phy_dev;
2637
2638 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2639 pp->phy_interface);
2640 if (!phy_dev) {
2641 netdev_err(pp->dev, "could not find the PHY\n");
2642 return -ENODEV;
2643 }
2644
2645 phy_dev->supported &= PHY_GBIT_FEATURES;
2646 phy_dev->advertising = phy_dev->supported;
2647
2648 pp->phy_dev = phy_dev;
2649 pp->link = 0;
2650 pp->duplex = 0;
2651 pp->speed = 0;
2652
2653 return 0;
2654}
2655
2656static void mvneta_mdio_remove(struct mvneta_port *pp)
2657{
2658 phy_disconnect(pp->phy_dev);
2659 pp->phy_dev = NULL;
2660}
2661
Maxime Ripardf8642882015-09-25 18:09:38 +02002662static void mvneta_percpu_enable(void *arg)
2663{
2664 struct mvneta_port *pp = arg;
2665
2666 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
2667}
2668
2669static void mvneta_percpu_disable(void *arg)
2670{
2671 struct mvneta_port *pp = arg;
2672
2673 disable_percpu_irq(pp->dev->irq);
2674}
2675
2676static void mvneta_percpu_elect(struct mvneta_port *pp)
2677{
2678 int online_cpu_idx, cpu, i = 0;
2679
2680 online_cpu_idx = rxq_def % num_online_cpus();
2681
2682 for_each_online_cpu(cpu) {
2683 if (i == online_cpu_idx)
2684 /* Enable per-CPU interrupt on the one CPU we
2685 * just elected
2686 */
2687 smp_call_function_single(cpu, mvneta_percpu_enable,
2688 pp, true);
2689 else
2690 /* Disable per-CPU interrupt on all the other CPU */
2691 smp_call_function_single(cpu, mvneta_percpu_disable,
2692 pp, true);
2693 i++;
2694 }
2695};
2696
2697static int mvneta_percpu_notifier(struct notifier_block *nfb,
2698 unsigned long action, void *hcpu)
2699{
2700 struct mvneta_port *pp = container_of(nfb, struct mvneta_port,
2701 cpu_notifier);
2702 int cpu = (unsigned long)hcpu, other_cpu;
2703 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
2704
2705 switch (action) {
2706 case CPU_ONLINE:
2707 case CPU_ONLINE_FROZEN:
2708 netif_tx_stop_all_queues(pp->dev);
2709
2710 /* We have to synchronise on tha napi of each CPU
2711 * except the one just being waked up
2712 */
2713 for_each_online_cpu(other_cpu) {
2714 if (other_cpu != cpu) {
2715 struct mvneta_pcpu_port *other_port =
2716 per_cpu_ptr(pp->ports, other_cpu);
2717
2718 napi_synchronize(&other_port->napi);
2719 }
2720 }
2721
2722 /* Mask all ethernet port interrupts */
2723 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2724 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2725 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2726 napi_enable(&port->napi);
2727
2728 /* Enable per-CPU interrupt on the one CPU we care
2729 * about.
2730 */
2731 mvneta_percpu_elect(pp);
2732
2733 /* Unmask all ethernet port interrupts */
2734 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2735 MVNETA_RX_INTR_MASK(rxq_number) |
2736 MVNETA_TX_INTR_MASK(txq_number) |
2737 MVNETA_MISCINTR_INTR_MASK);
2738 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2739 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2740 MVNETA_CAUSE_LINK_CHANGE |
2741 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2742 netif_tx_start_all_queues(pp->dev);
2743 break;
2744 case CPU_DOWN_PREPARE:
2745 case CPU_DOWN_PREPARE_FROZEN:
2746 netif_tx_stop_all_queues(pp->dev);
2747 /* Mask all ethernet port interrupts */
2748 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2749 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2750 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2751
2752 napi_synchronize(&port->napi);
2753 napi_disable(&port->napi);
2754 /* Disable per-CPU interrupts on the CPU that is
2755 * brought down.
2756 */
2757 smp_call_function_single(cpu, mvneta_percpu_disable,
2758 pp, true);
2759
2760 break;
2761 case CPU_DEAD:
2762 case CPU_DEAD_FROZEN:
2763 /* Check if a new CPU must be elected now this on is down */
2764 mvneta_percpu_elect(pp);
2765 /* Unmask all ethernet port interrupts */
2766 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2767 MVNETA_RX_INTR_MASK(rxq_number) |
2768 MVNETA_TX_INTR_MASK(txq_number) |
2769 MVNETA_MISCINTR_INTR_MASK);
2770 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2771 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2772 MVNETA_CAUSE_LINK_CHANGE |
2773 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2774 netif_tx_start_all_queues(pp->dev);
2775 break;
2776 }
2777
2778 return NOTIFY_OK;
2779}
2780
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002781static int mvneta_open(struct net_device *dev)
2782{
2783 struct mvneta_port *pp = netdev_priv(dev);
2784 int ret;
2785
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002786 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
willy tarreau8ec2cd42014-01-16 08:20:16 +01002787 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2788 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002789
2790 ret = mvneta_setup_rxqs(pp);
2791 if (ret)
2792 return ret;
2793
2794 ret = mvneta_setup_txqs(pp);
2795 if (ret)
2796 goto err_cleanup_rxqs;
2797
2798 /* Connect to port interrupt line */
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002799 ret = request_percpu_irq(pp->dev->irq, mvneta_isr,
2800 MVNETA_DRIVER_NAME, pp->ports);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002801 if (ret) {
2802 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2803 goto err_cleanup_txqs;
2804 }
2805
Maxime Ripardf8642882015-09-25 18:09:38 +02002806 /* Even though the documentation says that request_percpu_irq
2807 * doesn't enable the interrupts automatically, it actually
2808 * does so on the local CPU.
2809 *
2810 * Make sure it's disabled.
2811 */
2812 mvneta_percpu_disable(pp);
2813
2814 /* Elect a CPU to handle our RX queue interrupt */
2815 mvneta_percpu_elect(pp);
2816
2817 /* Register a CPU notifier to handle the case where our CPU
2818 * might be taken offline.
2819 */
2820 register_cpu_notifier(&pp->cpu_notifier);
2821
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002822 /* In default link is down */
2823 netif_carrier_off(pp->dev);
2824
2825 ret = mvneta_mdio_probe(pp);
2826 if (ret < 0) {
2827 netdev_err(dev, "cannot probe MDIO bus\n");
2828 goto err_free_irq;
2829 }
2830
2831 mvneta_start_dev(pp);
2832
2833 return 0;
2834
2835err_free_irq:
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002836 free_percpu_irq(pp->dev->irq, pp->ports);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002837err_cleanup_txqs:
2838 mvneta_cleanup_txqs(pp);
2839err_cleanup_rxqs:
2840 mvneta_cleanup_rxqs(pp);
2841 return ret;
2842}
2843
2844/* Stop the port, free port interrupt line */
2845static int mvneta_stop(struct net_device *dev)
2846{
2847 struct mvneta_port *pp = netdev_priv(dev);
Maxime Ripardf8642882015-09-25 18:09:38 +02002848 int cpu;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002849
2850 mvneta_stop_dev(pp);
2851 mvneta_mdio_remove(pp);
Maxime Ripardf8642882015-09-25 18:09:38 +02002852 unregister_cpu_notifier(&pp->cpu_notifier);
2853 for_each_present_cpu(cpu)
2854 smp_call_function_single(cpu, mvneta_percpu_disable, pp, true);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02002855 free_percpu_irq(dev->irq, pp->ports);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002856 mvneta_cleanup_rxqs(pp);
2857 mvneta_cleanup_txqs(pp);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002858
2859 return 0;
2860}
2861
Thomas Petazzoni15f59452013-09-04 16:26:52 +02002862static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2863{
2864 struct mvneta_port *pp = netdev_priv(dev);
Thomas Petazzoni15f59452013-09-04 16:26:52 +02002865
2866 if (!pp->phy_dev)
2867 return -ENOTSUPP;
2868
Stas Sergeevecf7b362015-04-01 19:23:29 +03002869 return phy_mii_ioctl(pp->phy_dev, ifr, cmd);
Thomas Petazzoni15f59452013-09-04 16:26:52 +02002870}
2871
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002872/* Ethtool methods */
2873
2874/* Get settings (phy address, speed) for ethtools */
2875int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2876{
2877 struct mvneta_port *pp = netdev_priv(dev);
2878
2879 if (!pp->phy_dev)
2880 return -ENODEV;
2881
2882 return phy_ethtool_gset(pp->phy_dev, cmd);
2883}
2884
2885/* Set settings (phy address, speed) for ethtools */
2886int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2887{
2888 struct mvneta_port *pp = netdev_priv(dev);
2889
2890 if (!pp->phy_dev)
2891 return -ENODEV;
2892
2893 return phy_ethtool_sset(pp->phy_dev, cmd);
2894}
2895
2896/* Set interrupt coalescing for ethtools */
2897static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2898 struct ethtool_coalesce *c)
2899{
2900 struct mvneta_port *pp = netdev_priv(dev);
2901 int queue;
2902
2903 for (queue = 0; queue < rxq_number; queue++) {
2904 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2905 rxq->time_coal = c->rx_coalesce_usecs;
2906 rxq->pkts_coal = c->rx_max_coalesced_frames;
2907 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2908 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2909 }
2910
2911 for (queue = 0; queue < txq_number; queue++) {
2912 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2913 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2914 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2915 }
2916
2917 return 0;
2918}
2919
2920/* get coalescing for ethtools */
2921static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2922 struct ethtool_coalesce *c)
2923{
2924 struct mvneta_port *pp = netdev_priv(dev);
2925
2926 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2927 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2928
2929 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2930 return 0;
2931}
2932
2933
2934static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2935 struct ethtool_drvinfo *drvinfo)
2936{
2937 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2938 sizeof(drvinfo->driver));
2939 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2940 sizeof(drvinfo->version));
2941 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
2942 sizeof(drvinfo->bus_info));
2943}
2944
2945
2946static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
2947 struct ethtool_ringparam *ring)
2948{
2949 struct mvneta_port *pp = netdev_priv(netdev);
2950
2951 ring->rx_max_pending = MVNETA_MAX_RXD;
2952 ring->tx_max_pending = MVNETA_MAX_TXD;
2953 ring->rx_pending = pp->rx_ring_size;
2954 ring->tx_pending = pp->tx_ring_size;
2955}
2956
2957static int mvneta_ethtool_set_ringparam(struct net_device *dev,
2958 struct ethtool_ringparam *ring)
2959{
2960 struct mvneta_port *pp = netdev_priv(dev);
2961
2962 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
2963 return -EINVAL;
2964 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
2965 ring->rx_pending : MVNETA_MAX_RXD;
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -03002966
2967 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
2968 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
2969 if (pp->tx_ring_size != ring->tx_pending)
2970 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2971 pp->tx_ring_size, ring->tx_pending);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002972
2973 if (netif_running(dev)) {
2974 mvneta_stop(dev);
2975 if (mvneta_open(dev)) {
2976 netdev_err(dev,
2977 "error on opening device after ring param change\n");
2978 return -ENOMEM;
2979 }
2980 }
2981
2982 return 0;
2983}
2984
2985static const struct net_device_ops mvneta_netdev_ops = {
2986 .ndo_open = mvneta_open,
2987 .ndo_stop = mvneta_stop,
2988 .ndo_start_xmit = mvneta_tx,
2989 .ndo_set_rx_mode = mvneta_set_rx_mode,
2990 .ndo_set_mac_address = mvneta_set_mac_addr,
2991 .ndo_change_mtu = mvneta_change_mtu,
Simon Guinotb65657f2015-06-30 16:20:22 +02002992 .ndo_fix_features = mvneta_fix_features,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002993 .ndo_get_stats64 = mvneta_get_stats64,
Thomas Petazzoni15f59452013-09-04 16:26:52 +02002994 .ndo_do_ioctl = mvneta_ioctl,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03002995};
2996
2997const struct ethtool_ops mvneta_eth_tool_ops = {
2998 .get_link = ethtool_op_get_link,
2999 .get_settings = mvneta_ethtool_get_settings,
3000 .set_settings = mvneta_ethtool_set_settings,
3001 .set_coalesce = mvneta_ethtool_set_coalesce,
3002 .get_coalesce = mvneta_ethtool_get_coalesce,
3003 .get_drvinfo = mvneta_ethtool_get_drvinfo,
3004 .get_ringparam = mvneta_ethtool_get_ringparam,
3005 .set_ringparam = mvneta_ethtool_set_ringparam,
3006};
3007
3008/* Initialize hw */
Ezequiel Garcia96728502014-05-22 20:06:59 -03003009static int mvneta_init(struct device *dev, struct mvneta_port *pp)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003010{
3011 int queue;
3012
3013 /* Disable port */
3014 mvneta_port_disable(pp);
3015
3016 /* Set port default values */
3017 mvneta_defaults_set(pp);
3018
Ezequiel Garcia96728502014-05-22 20:06:59 -03003019 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue),
3020 GFP_KERNEL);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003021 if (!pp->txqs)
3022 return -ENOMEM;
3023
3024 /* Initialize TX descriptor rings */
3025 for (queue = 0; queue < txq_number; queue++) {
3026 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3027 txq->id = queue;
3028 txq->size = pp->tx_ring_size;
3029 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
3030 }
3031
Ezequiel Garcia96728502014-05-22 20:06:59 -03003032 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue),
3033 GFP_KERNEL);
3034 if (!pp->rxqs)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003035 return -ENOMEM;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003036
3037 /* Create Rx descriptor rings */
3038 for (queue = 0; queue < rxq_number; queue++) {
3039 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3040 rxq->id = queue;
3041 rxq->size = pp->rx_ring_size;
3042 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
3043 rxq->time_coal = MVNETA_RX_COAL_USEC;
3044 }
3045
3046 return 0;
3047}
3048
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003049/* platform glue : initialize decoding windows */
Greg KH03ce7582012-12-21 13:42:15 +00003050static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
3051 const struct mbus_dram_target_info *dram)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003052{
3053 u32 win_enable;
3054 u32 win_protect;
3055 int i;
3056
3057 for (i = 0; i < 6; i++) {
3058 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
3059 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
3060
3061 if (i < 4)
3062 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
3063 }
3064
3065 win_enable = 0x3f;
3066 win_protect = 0;
3067
3068 for (i = 0; i < dram->num_cs; i++) {
3069 const struct mbus_dram_window *cs = dram->cs + i;
3070 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
3071 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
3072
3073 mvreg_write(pp, MVNETA_WIN_SIZE(i),
3074 (cs->size - 1) & 0xffff0000);
3075
3076 win_enable &= ~(1 << i);
3077 win_protect |= 3 << (2 * i);
3078 }
3079
3080 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
3081}
3082
3083/* Power up the port */
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003084static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003085{
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003086 u32 ctrl;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003087
3088 /* MAC Cause register should be cleared */
3089 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
3090
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003091 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003092
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003093 /* Even though it might look weird, when we're configured in
3094 * SGMII or QSGMII mode, the RGMII bit needs to be set.
3095 */
3096 switch(phy_mode) {
3097 case PHY_INTERFACE_MODE_QSGMII:
3098 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
3099 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3100 break;
3101 case PHY_INTERFACE_MODE_SGMII:
3102 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
3103 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
3104 break;
3105 case PHY_INTERFACE_MODE_RGMII:
3106 case PHY_INTERFACE_MODE_RGMII_ID:
3107 ctrl |= MVNETA_GMAC2_PORT_RGMII;
3108 break;
3109 default:
3110 return -EINVAL;
3111 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003112
Stas Sergeev898b2972015-04-01 20:32:49 +03003113 if (pp->use_inband_status)
3114 ctrl |= MVNETA_GMAC2_INBAND_AN_ENABLE;
3115
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003116 /* Cancel Port Reset */
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003117 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
3118 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003119
3120 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
3121 MVNETA_GMAC2_PORT_RESET) != 0)
3122 continue;
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003123
3124 return 0;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003125}
3126
3127/* Device initialization routine */
Greg KH03ce7582012-12-21 13:42:15 +00003128static int mvneta_probe(struct platform_device *pdev)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003129{
3130 const struct mbus_dram_target_info *dram_target_info;
Thomas Petazzonic3f0dd32014-03-27 11:39:29 +01003131 struct resource *res;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003132 struct device_node *dn = pdev->dev.of_node;
3133 struct device_node *phy_node;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003134 struct mvneta_port *pp;
3135 struct net_device *dev;
Thomas Petazzoni8cc3e432013-06-04 04:52:23 +00003136 const char *dt_mac_addr;
3137 char hw_mac_addr[ETH_ALEN];
3138 const char *mac_from;
Stas Sergeevf8af8e62015-07-20 17:49:58 -07003139 const char *managed;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003140 int phy_mode;
3141 int err;
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003142 int cpu;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003143
Willy Tarreauee40a112013-04-11 23:00:37 +02003144 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003145 if (!dev)
3146 return -ENOMEM;
3147
3148 dev->irq = irq_of_parse_and_map(dn, 0);
3149 if (dev->irq == 0) {
3150 err = -EINVAL;
3151 goto err_free_netdev;
3152 }
3153
3154 phy_node = of_parse_phandle(dn, "phy", 0);
3155 if (!phy_node) {
Thomas Petazzoni83895be2014-05-16 16:14:06 +02003156 if (!of_phy_is_fixed_link(dn)) {
3157 dev_err(&pdev->dev, "no PHY specified\n");
3158 err = -ENODEV;
3159 goto err_free_irq;
3160 }
3161
3162 err = of_phy_register_fixed_link(dn);
3163 if (err < 0) {
3164 dev_err(&pdev->dev, "cannot register fixed PHY\n");
3165 goto err_free_irq;
3166 }
3167
3168 /* In the case of a fixed PHY, the DT node associated
3169 * to the PHY is the Ethernet MAC DT node.
3170 */
Uwe Kleine-Königc891c242014-08-07 21:58:46 +02003171 phy_node = of_node_get(dn);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003172 }
3173
3174 phy_mode = of_get_phy_mode(dn);
3175 if (phy_mode < 0) {
3176 dev_err(&pdev->dev, "incorrect phy-mode\n");
3177 err = -EINVAL;
Uwe Kleine-Königc891c242014-08-07 21:58:46 +02003178 goto err_put_phy_node;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003179 }
3180
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003181 dev->tx_queue_len = MVNETA_MAX_TXD;
3182 dev->watchdog_timeo = 5 * HZ;
3183 dev->netdev_ops = &mvneta_netdev_ops;
3184
Wilfried Klaebe7ad24ea2014-05-11 00:12:32 +00003185 dev->ethtool_ops = &mvneta_eth_tool_ops;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003186
3187 pp = netdev_priv(dev);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003188 pp->phy_node = phy_node;
3189 pp->phy_interface = phy_mode;
Stas Sergeevf8af8e62015-07-20 17:49:58 -07003190
3191 err = of_property_read_string(dn, "managed", &managed);
3192 pp->use_inband_status = (err == 0 &&
3193 strcmp(managed, "in-band-status") == 0);
Maxime Ripardf8642882015-09-25 18:09:38 +02003194 pp->cpu_notifier.notifier_call = mvneta_percpu_notifier;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003195
Thomas Petazzoni189dd622012-11-19 14:15:25 +01003196 pp->clk = devm_clk_get(&pdev->dev, NULL);
3197 if (IS_ERR(pp->clk)) {
3198 err = PTR_ERR(pp->clk);
Uwe Kleine-Königc891c242014-08-07 21:58:46 +02003199 goto err_put_phy_node;
Thomas Petazzoni189dd622012-11-19 14:15:25 +01003200 }
3201
3202 clk_prepare_enable(pp->clk);
3203
Thomas Petazzonic3f0dd32014-03-27 11:39:29 +01003204 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3205 pp->base = devm_ioremap_resource(&pdev->dev, res);
3206 if (IS_ERR(pp->base)) {
3207 err = PTR_ERR(pp->base);
Arnaud Patard \(Rtp\)5445eaf2013-07-29 21:56:48 +02003208 goto err_clk;
3209 }
3210
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003211 /* Alloc per-cpu port structure */
3212 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
3213 if (!pp->ports) {
3214 err = -ENOMEM;
3215 goto err_clk;
3216 }
3217
willy tarreau74c41b02014-01-16 08:20:08 +01003218 /* Alloc per-cpu stats */
WANG Cong1c213bd2014-02-13 11:46:28 -08003219 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
willy tarreau74c41b02014-01-16 08:20:08 +01003220 if (!pp->stats) {
3221 err = -ENOMEM;
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003222 goto err_free_ports;
willy tarreau74c41b02014-01-16 08:20:08 +01003223 }
3224
Thomas Petazzoni8cc3e432013-06-04 04:52:23 +00003225 dt_mac_addr = of_get_mac_address(dn);
Luka Perkov6c7a9a32013-10-30 00:10:01 +01003226 if (dt_mac_addr) {
Thomas Petazzoni8cc3e432013-06-04 04:52:23 +00003227 mac_from = "device tree";
3228 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
3229 } else {
3230 mvneta_get_mac_addr(pp, hw_mac_addr);
3231 if (is_valid_ether_addr(hw_mac_addr)) {
3232 mac_from = "hardware";
3233 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
3234 } else {
3235 mac_from = "random";
3236 eth_hw_addr_random(dev);
3237 }
3238 }
3239
Simon Guinotb65657f2015-06-30 16:20:22 +02003240 if (of_device_is_compatible(dn, "marvell,armada-370-neta"))
3241 pp->tx_csum_limit = 1600;
3242
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003243 pp->tx_ring_size = MVNETA_MAX_TXD;
3244 pp->rx_ring_size = MVNETA_MAX_RXD;
3245
3246 pp->dev = dev;
3247 SET_NETDEV_DEV(dev, &pdev->dev);
3248
Ezequiel Garcia96728502014-05-22 20:06:59 -03003249 err = mvneta_init(&pdev->dev, pp);
3250 if (err < 0)
willy tarreau74c41b02014-01-16 08:20:08 +01003251 goto err_free_stats;
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003252
3253 err = mvneta_port_power_up(pp, phy_mode);
3254 if (err < 0) {
3255 dev_err(&pdev->dev, "can't power up port\n");
Ezequiel Garcia96728502014-05-22 20:06:59 -03003256 goto err_free_stats;
Thomas Petazzoni3f1dd4b2014-04-15 15:50:20 +02003257 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003258
3259 dram_target_info = mv_mbus_dram_info();
3260 if (dram_target_info)
3261 mvneta_conf_mbus_windows(pp, dram_target_info);
3262
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003263 for_each_present_cpu(cpu) {
3264 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3265
3266 netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT);
3267 port->pp = pp;
3268 }
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003269
Ezequiel Garcia2adb7192014-05-19 13:59:55 -03003270 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
Ezequiel Garcia01ef26c2014-05-19 13:59:53 -03003271 dev->hw_features |= dev->features;
3272 dev->vlan_features |= dev->features;
willy tarreaub50b72d2013-04-06 08:47:01 +00003273 dev->priv_flags |= IFF_UNICAST_FLT;
Ezequiel Garcia8eef5f92014-05-30 13:40:05 -03003274 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
willy tarreaub50b72d2013-04-06 08:47:01 +00003275
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003276 err = register_netdev(dev);
3277 if (err < 0) {
3278 dev_err(&pdev->dev, "failed to register\n");
Ezequiel Garcia96728502014-05-22 20:06:59 -03003279 goto err_free_stats;
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003280 }
3281
Thomas Petazzoni8cc3e432013-06-04 04:52:23 +00003282 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
3283 dev->dev_addr);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003284
3285 platform_set_drvdata(pdev, pp->dev);
3286
Stas Sergeev898b2972015-04-01 20:32:49 +03003287 if (pp->use_inband_status) {
3288 struct phy_device *phy = of_phy_find_device(dn);
3289
3290 mvneta_fixed_link_update(pp, phy);
Russell King04d53b22015-09-24 20:36:18 +01003291
3292 put_device(&phy->dev);
Stas Sergeev898b2972015-04-01 20:32:49 +03003293 }
3294
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003295 return 0;
3296
willy tarreau74c41b02014-01-16 08:20:08 +01003297err_free_stats:
3298 free_percpu(pp->stats);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003299err_free_ports:
3300 free_percpu(pp->ports);
Arnaud Patard \(Rtp\)5445eaf2013-07-29 21:56:48 +02003301err_clk:
3302 clk_disable_unprepare(pp->clk);
Uwe Kleine-Königc891c242014-08-07 21:58:46 +02003303err_put_phy_node:
3304 of_node_put(phy_node);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003305err_free_irq:
3306 irq_dispose_mapping(dev->irq);
3307err_free_netdev:
3308 free_netdev(dev);
3309 return err;
3310}
3311
3312/* Device removal routine */
Greg KH03ce7582012-12-21 13:42:15 +00003313static int mvneta_remove(struct platform_device *pdev)
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003314{
3315 struct net_device *dev = platform_get_drvdata(pdev);
3316 struct mvneta_port *pp = netdev_priv(dev);
3317
3318 unregister_netdev(dev);
Thomas Petazzoni189dd622012-11-19 14:15:25 +01003319 clk_disable_unprepare(pp->clk);
Maxime Ripard12bb03b2015-09-25 18:09:36 +02003320 free_percpu(pp->ports);
willy tarreau74c41b02014-01-16 08:20:08 +01003321 free_percpu(pp->stats);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003322 irq_dispose_mapping(dev->irq);
Uwe Kleine-Königc891c242014-08-07 21:58:46 +02003323 of_node_put(pp->phy_node);
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003324 free_netdev(dev);
3325
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003326 return 0;
3327}
3328
3329static const struct of_device_id mvneta_match[] = {
3330 { .compatible = "marvell,armada-370-neta" },
Simon Guinotf522a972015-06-30 16:20:20 +02003331 { .compatible = "marvell,armada-xp-neta" },
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003332 { }
3333};
3334MODULE_DEVICE_TABLE(of, mvneta_match);
3335
3336static struct platform_driver mvneta_driver = {
3337 .probe = mvneta_probe,
Greg KH03ce7582012-12-21 13:42:15 +00003338 .remove = mvneta_remove,
Thomas Petazzonic5aff182012-08-17 14:04:28 +03003339 .driver = {
3340 .name = MVNETA_DRIVER_NAME,
3341 .of_match_table = mvneta_match,
3342 },
3343};
3344
3345module_platform_driver(mvneta_driver);
3346
3347MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
3348MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
3349MODULE_LICENSE("GPL");
3350
3351module_param(rxq_number, int, S_IRUGO);
3352module_param(txq_number, int, S_IRUGO);
3353
3354module_param(rxq_def, int, S_IRUGO);
willy tarreauf19fadf2014-01-16 08:20:17 +01003355module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);