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Kaiwan N Billimoria78961a52007-07-17 04:04:05 -07001spi_lm70llp : LM70-LLP parport-to-SPI adapter
2==============================================
3
4Supported board/chip:
5 * National Semiconductor LM70 LLP evaluation board
6 Datasheet: http://www.national.com/pf/LM/LM70.html
7
8Author:
9 Kaiwan N Billimoria <kaiwan@designergraphix.com>
10
11Description
12-----------
13This driver provides glue code connecting a National Semiconductor LM70 LLP
14temperature sensor evaluation board to the kernel's SPI core subsystem.
15
16In effect, this driver turns the parallel port interface on the eval board
17into a SPI bus with a single device, which will be driven by the generic
18LM70 driver (drivers/hwmon/lm70.c).
19
20The hardware interfacing on the LM70 LLP eval board is as follows:
21
22 Parallel LM70 LLP
23 Port Direction JP2 Header
24 ----------- --------- ----------------
25 D0 2 - -
26 D1 3 --> V+ 5
27 D2 4 --> V+ 5
28 D3 5 --> V+ 5
29 D4 6 --> V+ 5
30 D5 7 --> nCS 8
31 D6 8 --> SCLK 3
32 D7 9 --> SI/O 5
33 GND 25 - GND 7
34 Select 13 <-- SI/O 1
35 ----------- --------- ----------------
36
37Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin
38is connected to both pin D7 (as Master Out) and Select (as Master In)
39using an arrangment that lets either the parport or the LM70 pull the
40pin low. This can't be shared with true SPI devices, but other 3-wire
41devices might share the same SI/SO pin.
42
43The bitbanger routine in this driver (lm70_txrx) is called back from
44the bound "hwmon/lm70" protocol driver through its sysfs hook, using a
45spi_write_then_read() call. It performs Mode 0 (SPI/Microwire) bitbanging.
46The lm70 driver then inteprets the resulting digital temperature value
47and exports it through sysfs.
48
49A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic
50shows that the SI/O line from the LM70 chip is connected to the base of a
51transistor Q1 (and also a pullup, and a zener diode to D7); while the
52collector is tied to VCC.
53
54Interpreting this circuit, when the LM70 SI/O line is High (or tristate
55and not grounded by the host via D7), the transistor conducts and switches
56the collector to zero, which is reflected on pin 13 of the DB25 parport
57connector. When SI/O is Low (driven by the LM70 or the host) on the other
58hand, the transistor is cut off and the voltage tied to it's collector is
59reflected on pin 13 as a High level.
60
61So: the getmiso inline routine in this driver takes this fact into account,
62inverting the value read at pin 13.
63
64
65Thanks to
66---------
67o David Brownell for mentoring the SPI-side driver development.
68o Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version.
69o Nadir Billimoria for help interpreting the circuit schematic.