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Huang Shijie8eabdd12014-04-10 16:27:28 +08001/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
Huang Shijief39d2fa2014-02-24 18:37:35 +080010#ifndef __LINUX_MTD_SPI_NOR_H
11#define __LINUX_MTD_SPI_NOR_H
12
Brian Norris801cf212015-09-01 12:57:06 -070013#include <linux/bitops.h>
Brian Norrisdb4745e2015-09-01 12:57:08 -070014#include <linux/mtd/cfi.h>
15
16/*
17 * Manufacturer IDs
18 *
19 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
20 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
21 */
22#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
23#define SNOR_MFR_INTEL CFI_MFR_INTEL
24#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
25#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
26#define SNOR_MFR_SPANSION CFI_MFR_AMD
27#define SNOR_MFR_SST CFI_MFR_SST
28#define SNOR_MFR_WINBOND 0xef
Brian Norris801cf212015-09-01 12:57:06 -070029
Brian Norris58b89a12014-04-08 19:16:49 -070030/*
31 * Note on opcode nomenclature: some opcodes have a format like
32 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
33 * of I/O lines used for the opcode, address, and data (respectively). The
34 * FUNCTION has an optional suffix of '4', to represent an opcode which
35 * requires a 4-byte (32-bit) address.
36 */
37
Huang Shijief39d2fa2014-02-24 18:37:35 +080038/* Flash opcodes. */
Brian Norrisb02e7f32014-04-08 18:15:31 -070039#define SPINOR_OP_WREN 0x06 /* Write enable */
40#define SPINOR_OP_RDSR 0x05 /* Read status register */
41#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
Brian Norris58b89a12014-04-08 19:16:49 -070042#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
43#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
44#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
45#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
Brian Norrisb02e7f32014-04-08 18:15:31 -070046#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
47#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
48#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
49#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
50#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
51#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
52#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
53#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
grmoore@altera.comc14dedd2014-04-29 10:29:51 -050054#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
Huang Shijief39d2fa2014-02-24 18:37:35 +080055
56/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
Brian Norris58b89a12014-04-08 19:16:49 -070057#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
58#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
59#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
60#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
Brian Norrisb02e7f32014-04-08 18:15:31 -070061#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
62#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
Huang Shijief39d2fa2014-02-24 18:37:35 +080063
64/* Used for SST flashes only. */
Brian Norrisb02e7f32014-04-08 18:15:31 -070065#define SPINOR_OP_BP 0x02 /* Byte program */
66#define SPINOR_OP_WRDI 0x04 /* Write disable */
67#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
Huang Shijief39d2fa2014-02-24 18:37:35 +080068
69/* Used for Macronix and Winbond flashes. */
Brian Norrisb02e7f32014-04-08 18:15:31 -070070#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
71#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
Huang Shijief39d2fa2014-02-24 18:37:35 +080072
73/* Used for Spansion flashes only. */
Brian Norrisb02e7f32014-04-08 18:15:31 -070074#define SPINOR_OP_BRWR 0x17 /* Bank register write */
Huang Shijief39d2fa2014-02-24 18:37:35 +080075
Bean Huo 霍斌斌 (beanhuo)548cd3ab2014-12-17 07:35:45 +000076/* Used for Micron flashes only. */
77#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
78#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
79
Huang Shijief39d2fa2014-02-24 18:37:35 +080080/* Status Register bits. */
Brian Norrisa8a16452015-09-01 12:57:07 -070081#define SR_WIP BIT(0) /* Write in progress */
82#define SR_WEL BIT(1) /* Write enable latch */
Huang Shijief39d2fa2014-02-24 18:37:35 +080083/* meaning of other SR_* bits may differ between vendors */
Brian Norrisa8a16452015-09-01 12:57:07 -070084#define SR_BP0 BIT(2) /* Block protect 0 */
85#define SR_BP1 BIT(3) /* Block protect 1 */
86#define SR_BP2 BIT(4) /* Block protect 2 */
87#define SR_SRWD BIT(7) /* SR write protect */
Huang Shijief39d2fa2014-02-24 18:37:35 +080088
Brian Norrisa8a16452015-09-01 12:57:07 -070089#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
Huang Shijief39d2fa2014-02-24 18:37:35 +080090
Bean Huo 霍斌斌 (beanhuo)548cd3ab2014-12-17 07:35:45 +000091/* Enhanced Volatile Configuration Register bits */
Brian Norrisa8a16452015-09-01 12:57:07 -070092#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
Bean Huo 霍斌斌 (beanhuo)548cd3ab2014-12-17 07:35:45 +000093
grmoore@altera.comc14dedd2014-04-29 10:29:51 -050094/* Flag Status Register bits */
Brian Norrisa8a16452015-09-01 12:57:07 -070095#define FSR_READY BIT(7)
grmoore@altera.comc14dedd2014-04-29 10:29:51 -050096
Huang Shijief39d2fa2014-02-24 18:37:35 +080097/* Configuration Register bits. */
Brian Norrisa8a16452015-09-01 12:57:07 -070098#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
Huang Shijief39d2fa2014-02-24 18:37:35 +080099
Huang Shijie6e602ef2014-02-24 18:37:36 +0800100enum read_mode {
101 SPI_NOR_NORMAL = 0,
102 SPI_NOR_FAST,
103 SPI_NOR_DUAL,
104 SPI_NOR_QUAD,
105};
106
Brian Norrisbecd0cb2014-04-08 18:10:23 -0700107#define SPI_NOR_MAX_CMD_SIZE 8
Huang Shijie6e602ef2014-02-24 18:37:36 +0800108enum spi_nor_ops {
109 SPI_NOR_OPS_READ = 0,
110 SPI_NOR_OPS_WRITE,
111 SPI_NOR_OPS_ERASE,
112 SPI_NOR_OPS_LOCK,
113 SPI_NOR_OPS_UNLOCK,
114};
115
Brian Norris6af91942014-08-06 18:16:58 -0700116enum spi_nor_option_flags {
117 SNOR_F_USE_FSR = BIT(0),
118};
119
Brian Norrisa39f1d52015-08-13 15:46:04 -0700120struct mtd_info;
121
Huang Shijie6e602ef2014-02-24 18:37:36 +0800122/**
123 * struct spi_nor - Structure for defining a the SPI NOR layer
124 * @mtd: point to a mtd_info structure
125 * @lock: the lock for the read/write/erase/lock/unlock operations
126 * @dev: point to a spi device, or a spi nor controller device.
Marek Vasut11bff0b2015-09-03 18:35:36 +0200127 * @flash_node: point to a device node describing this flash instance.
Huang Shijie6e602ef2014-02-24 18:37:36 +0800128 * @page_size: the page size of the SPI NOR
129 * @addr_width: number of address bytes
130 * @erase_opcode: the opcode for erasing a sector
131 * @read_opcode: the read opcode
132 * @read_dummy: the dummy needed by the read operation
133 * @program_opcode: the program opcode
134 * @flash_read: the mode of the read
135 * @sst_write_second: used by the SST write operation
Brian Norris6af91942014-08-06 18:16:58 -0700136 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
Huang Shijie6e602ef2014-02-24 18:37:36 +0800137 * @cmd_buf: used by the write_reg
138 * @prepare: [OPTIONAL] do some preparations for the
139 * read/write/erase/lock/unlock operations
140 * @unprepare: [OPTIONAL] do some post work after the
141 * read/write/erase/lock/unlock operations
Huang Shijie6e602ef2014-02-24 18:37:36 +0800142 * @read_reg: [DRIVER-SPECIFIC] read out the register
143 * @write_reg: [DRIVER-SPECIFIC] write data to the register
Huang Shijie6e602ef2014-02-24 18:37:36 +0800144 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
145 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
146 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
147 * at the offset @offs
Brian Norrisf8900252015-09-01 12:57:10 -0700148 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
149 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
Huang Shijie6e602ef2014-02-24 18:37:36 +0800150 * @priv: the private data
151 */
152struct spi_nor {
Brian Norris19763672015-08-13 15:46:05 -0700153 struct mtd_info mtd;
Huang Shijie6e602ef2014-02-24 18:37:36 +0800154 struct mutex lock;
155 struct device *dev;
Marek Vasut11bff0b2015-09-03 18:35:36 +0200156 struct device_node *flash_node;
Huang Shijie6e602ef2014-02-24 18:37:36 +0800157 u32 page_size;
158 u8 addr_width;
159 u8 erase_opcode;
160 u8 read_opcode;
161 u8 read_dummy;
162 u8 program_opcode;
163 enum read_mode flash_read;
164 bool sst_write_second;
Brian Norris6af91942014-08-06 18:16:58 -0700165 u32 flags;
Huang Shijie6e602ef2014-02-24 18:37:36 +0800166 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
167
168 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
169 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
Huang Shijie6e602ef2014-02-24 18:37:36 +0800170 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
Jagan Tekif9f3ce82015-08-19 15:26:44 +0530171 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
Huang Shijie6e602ef2014-02-24 18:37:36 +0800172
173 int (*read)(struct spi_nor *nor, loff_t from,
174 size_t len, size_t *retlen, u_char *read_buf);
175 void (*write)(struct spi_nor *nor, loff_t to,
176 size_t len, size_t *retlen, const u_char *write_buf);
177 int (*erase)(struct spi_nor *nor, loff_t offs);
178
Brian Norris8cc7f332015-03-13 00:38:39 -0700179 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
180 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
181
Huang Shijie6e602ef2014-02-24 18:37:36 +0800182 void *priv;
183};
Huang Shijieb1994892014-02-24 18:37:37 +0800184
185/**
186 * spi_nor_scan() - scan the SPI NOR
187 * @nor: the spi_nor structure
Ben Hutchings70f3ce02014-09-29 11:47:54 +0200188 * @name: the chip type name
Huang Shijieb1994892014-02-24 18:37:37 +0800189 * @mode: the read mode supported by the driver
190 *
191 * The drivers can use this fuction to scan the SPI NOR.
192 * In the scanning, it will try to get all the necessary information to
193 * fill the mtd_info{} and the spi_nor{}.
194 *
Ben Hutchings70f3ce02014-09-29 11:47:54 +0200195 * The chip type name can be provided through the @name parameter.
Huang Shijieb1994892014-02-24 18:37:37 +0800196 *
197 * Return: 0 for success, others for failure.
198 */
Ben Hutchings70f3ce02014-09-29 11:47:54 +0200199int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode);
Huang Shijieb1994892014-02-24 18:37:37 +0800200
Huang Shijief39d2fa2014-02-24 18:37:35 +0800201#endif