Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 1 | /* |
| 2 | * GPIOs on MPC8349/8572/8610 and compatible |
| 3 | * |
| 4 | * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/spinlock.h> |
| 14 | #include <linux/io.h> |
| 15 | #include <linux/of.h> |
| 16 | #include <linux/of_gpio.h> |
| 17 | #include <linux/gpio.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 18 | #include <linux/slab.h> |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 19 | #include <linux/irq.h> |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 20 | |
| 21 | #define MPC8XXX_GPIO_PINS 32 |
| 22 | |
| 23 | #define GPIO_DIR 0x00 |
| 24 | #define GPIO_ODR 0x04 |
| 25 | #define GPIO_DAT 0x08 |
| 26 | #define GPIO_IER 0x0c |
| 27 | #define GPIO_IMR 0x10 |
| 28 | #define GPIO_ICR 0x14 |
| 29 | |
| 30 | struct mpc8xxx_gpio_chip { |
| 31 | struct of_mm_gpio_chip mm_gc; |
| 32 | spinlock_t lock; |
| 33 | |
| 34 | /* |
| 35 | * shadowed data register to be able to clear/set output pins in |
| 36 | * open drain mode safely |
| 37 | */ |
| 38 | u32 data; |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 39 | struct irq_host *irq; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) |
| 43 | { |
| 44 | return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); |
| 45 | } |
| 46 | |
| 47 | static inline struct mpc8xxx_gpio_chip * |
| 48 | to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm) |
| 49 | { |
| 50 | return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc); |
| 51 | } |
| 52 | |
| 53 | static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm) |
| 54 | { |
| 55 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 56 | |
| 57 | mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); |
| 58 | } |
| 59 | |
Felix Radensky | c1a676d | 2009-08-12 08:57:39 +0300 | [diff] [blame] | 60 | /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs |
| 61 | * defined as output cannot be determined by reading GPDAT register, |
| 62 | * so we use shadow data register instead. The status of input pins |
| 63 | * is determined by reading GPDAT register. |
| 64 | */ |
| 65 | static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
| 66 | { |
| 67 | u32 val; |
| 68 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 69 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 70 | |
| 71 | val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR); |
| 72 | |
| 73 | return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio); |
| 74 | } |
| 75 | |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 76 | static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
| 77 | { |
| 78 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 79 | |
| 80 | return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); |
| 81 | } |
| 82 | |
| 83 | static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
| 84 | { |
| 85 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 86 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 87 | unsigned long flags; |
| 88 | |
| 89 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 90 | |
| 91 | if (val) |
| 92 | mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio); |
| 93 | else |
| 94 | mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); |
| 95 | |
| 96 | out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); |
| 97 | |
| 98 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 99 | } |
| 100 | |
| 101 | static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) |
| 102 | { |
| 103 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 104 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 105 | unsigned long flags; |
| 106 | |
| 107 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 108 | |
| 109 | clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); |
| 110 | |
| 111 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 112 | |
| 113 | return 0; |
| 114 | } |
| 115 | |
| 116 | static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) |
| 117 | { |
| 118 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 119 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 120 | unsigned long flags; |
| 121 | |
| 122 | mpc8xxx_gpio_set(gc, gpio, val); |
| 123 | |
| 124 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 125 | |
| 126 | setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); |
| 127 | |
| 128 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 129 | |
| 130 | return 0; |
| 131 | } |
| 132 | |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 133 | static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
| 134 | { |
| 135 | struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); |
| 136 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); |
| 137 | |
| 138 | if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) |
| 139 | return irq_create_mapping(mpc8xxx_gc->irq, offset); |
| 140 | else |
| 141 | return -ENXIO; |
| 142 | } |
| 143 | |
| 144 | static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) |
| 145 | { |
| 146 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc); |
| 147 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 148 | unsigned int mask; |
| 149 | |
| 150 | mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); |
| 151 | if (mask) |
| 152 | generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, |
| 153 | 32 - ffs(mask))); |
| 154 | } |
| 155 | |
| 156 | static void mpc8xxx_irq_unmask(unsigned int virq) |
| 157 | { |
| 158 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); |
| 159 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 160 | unsigned long flags; |
| 161 | |
| 162 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 163 | |
| 164 | setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq))); |
| 165 | |
| 166 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 167 | } |
| 168 | |
| 169 | static void mpc8xxx_irq_mask(unsigned int virq) |
| 170 | { |
| 171 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); |
| 172 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 173 | unsigned long flags; |
| 174 | |
| 175 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 176 | |
| 177 | clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq))); |
| 178 | |
| 179 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 180 | } |
| 181 | |
| 182 | static void mpc8xxx_irq_ack(unsigned int virq) |
| 183 | { |
| 184 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); |
| 185 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 186 | |
| 187 | out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(virq))); |
| 188 | } |
| 189 | |
| 190 | static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type) |
| 191 | { |
| 192 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); |
| 193 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
| 194 | unsigned long flags; |
| 195 | |
| 196 | switch (flow_type) { |
| 197 | case IRQ_TYPE_EDGE_FALLING: |
| 198 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 199 | setbits32(mm->regs + GPIO_ICR, |
| 200 | mpc8xxx_gpio2mask(virq_to_hw(virq))); |
| 201 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 202 | break; |
| 203 | |
| 204 | case IRQ_TYPE_EDGE_BOTH: |
| 205 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
| 206 | clrbits32(mm->regs + GPIO_ICR, |
| 207 | mpc8xxx_gpio2mask(virq_to_hw(virq))); |
| 208 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
| 209 | break; |
| 210 | |
| 211 | default: |
| 212 | return -EINVAL; |
| 213 | } |
| 214 | |
| 215 | return 0; |
| 216 | } |
| 217 | |
| 218 | static struct irq_chip mpc8xxx_irq_chip = { |
| 219 | .name = "mpc8xxx-gpio", |
| 220 | .unmask = mpc8xxx_irq_unmask, |
| 221 | .mask = mpc8xxx_irq_mask, |
| 222 | .ack = mpc8xxx_irq_ack, |
| 223 | .set_type = mpc8xxx_irq_set_type, |
| 224 | }; |
| 225 | |
| 226 | static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, |
| 227 | irq_hw_number_t hw) |
| 228 | { |
| 229 | set_irq_chip_data(virq, h->host_data); |
| 230 | set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); |
| 231 | set_irq_type(virq, IRQ_TYPE_NONE); |
| 232 | |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct, |
| 237 | const u32 *intspec, unsigned int intsize, |
| 238 | irq_hw_number_t *out_hwirq, |
| 239 | unsigned int *out_flags) |
| 240 | |
| 241 | { |
| 242 | /* interrupt sense values coming from the device tree equal either |
| 243 | * EDGE_FALLING or EDGE_BOTH |
| 244 | */ |
| 245 | *out_hwirq = intspec[0]; |
| 246 | *out_flags = intspec[1]; |
| 247 | |
| 248 | return 0; |
| 249 | } |
| 250 | |
| 251 | static struct irq_host_ops mpc8xxx_gpio_irq_ops = { |
| 252 | .map = mpc8xxx_gpio_irq_map, |
| 253 | .xlate = mpc8xxx_gpio_irq_xlate, |
| 254 | }; |
| 255 | |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 256 | static void __init mpc8xxx_add_controller(struct device_node *np) |
| 257 | { |
| 258 | struct mpc8xxx_gpio_chip *mpc8xxx_gc; |
| 259 | struct of_mm_gpio_chip *mm_gc; |
| 260 | struct of_gpio_chip *of_gc; |
| 261 | struct gpio_chip *gc; |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 262 | unsigned hwirq; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 263 | int ret; |
| 264 | |
| 265 | mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL); |
| 266 | if (!mpc8xxx_gc) { |
| 267 | ret = -ENOMEM; |
| 268 | goto err; |
| 269 | } |
| 270 | |
| 271 | spin_lock_init(&mpc8xxx_gc->lock); |
| 272 | |
| 273 | mm_gc = &mpc8xxx_gc->mm_gc; |
| 274 | of_gc = &mm_gc->of_gc; |
| 275 | gc = &of_gc->gc; |
| 276 | |
| 277 | mm_gc->save_regs = mpc8xxx_gpio_save_regs; |
| 278 | of_gc->gpio_cells = 2; |
| 279 | gc->ngpio = MPC8XXX_GPIO_PINS; |
| 280 | gc->direction_input = mpc8xxx_gpio_dir_in; |
| 281 | gc->direction_output = mpc8xxx_gpio_dir_out; |
Felix Radensky | c1a676d | 2009-08-12 08:57:39 +0300 | [diff] [blame] | 282 | if (of_device_is_compatible(np, "fsl,mpc8572-gpio")) |
| 283 | gc->get = mpc8572_gpio_get; |
| 284 | else |
| 285 | gc->get = mpc8xxx_gpio_get; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 286 | gc->set = mpc8xxx_gpio_set; |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 287 | gc->to_irq = mpc8xxx_gpio_to_irq; |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 288 | |
| 289 | ret = of_mm_gpiochip_add(np, mm_gc); |
| 290 | if (ret) |
| 291 | goto err; |
| 292 | |
Peter Korsgaard | 345e5c8 | 2010-01-07 17:57:46 +0100 | [diff] [blame] | 293 | hwirq = irq_of_parse_and_map(np, 0); |
| 294 | if (hwirq == NO_IRQ) |
| 295 | goto skip_irq; |
| 296 | |
| 297 | mpc8xxx_gc->irq = |
| 298 | irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS, |
| 299 | &mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS); |
| 300 | if (!mpc8xxx_gc->irq) |
| 301 | goto skip_irq; |
| 302 | |
| 303 | mpc8xxx_gc->irq->host_data = mpc8xxx_gc; |
| 304 | |
| 305 | /* ack and mask all irqs */ |
| 306 | out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); |
| 307 | out_be32(mm_gc->regs + GPIO_IMR, 0); |
| 308 | |
| 309 | set_irq_data(hwirq, mpc8xxx_gc); |
| 310 | set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); |
| 311 | |
| 312 | skip_irq: |
Peter Korsgaard | 1e16dfc | 2008-09-23 17:35:38 +0200 | [diff] [blame] | 313 | return; |
| 314 | |
| 315 | err: |
| 316 | pr_err("%s: registration failed with status %d\n", |
| 317 | np->full_name, ret); |
| 318 | kfree(mpc8xxx_gc); |
| 319 | |
| 320 | return; |
| 321 | } |
| 322 | |
| 323 | static int __init mpc8xxx_add_gpiochips(void) |
| 324 | { |
| 325 | struct device_node *np; |
| 326 | |
| 327 | for_each_compatible_node(np, NULL, "fsl,mpc8349-gpio") |
| 328 | mpc8xxx_add_controller(np); |
| 329 | |
| 330 | for_each_compatible_node(np, NULL, "fsl,mpc8572-gpio") |
| 331 | mpc8xxx_add_controller(np); |
| 332 | |
| 333 | for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio") |
| 334 | mpc8xxx_add_controller(np); |
| 335 | |
| 336 | return 0; |
| 337 | } |
| 338 | arch_initcall(mpc8xxx_add_gpiochips); |