blob: 5fd75fdaa631bd930fc96986ee0649b9d94729eb [file] [log] [blame]
Casey Leedomc6e0d912010-06-25 12:13:28 +00001/*
2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
3 * driver for Linux.
4 *
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/if_vlan.h>
40#include <linux/ip.h>
41#include <net/ipv6.h>
42#include <net/tcp.h>
43#include <linux/dma-mapping.h>
Paul Gortmaker70c71602011-05-22 16:47:17 -040044#include <linux/prefetch.h>
Casey Leedomc6e0d912010-06-25 12:13:28 +000045
46#include "t4vf_common.h"
47#include "t4vf_defs.h"
48
49#include "../cxgb4/t4_regs.h"
50#include "../cxgb4/t4fw_api.h"
51#include "../cxgb4/t4_msg.h"
52
53/*
54 * Decoded Adapter Parameters.
55 */
56static u32 FL_PG_ORDER; /* large page allocation size */
57static u32 STAT_LEN; /* length of status page at ring end */
58static u32 PKTSHIFT; /* padding between CPL and packet data */
59static u32 FL_ALIGN; /* response queue message alignment */
60
61/*
62 * Constants ...
63 */
64enum {
65 /*
66 * Egress Queue sizes, producer and consumer indices are all in units
67 * of Egress Context Units bytes. Note that as far as the hardware is
68 * concerned, the free list is an Egress Queue (the host produces free
69 * buffers which the hardware consumes) and free list entries are
70 * 64-bit PCI DMA addresses.
71 */
72 EQ_UNIT = SGE_EQ_IDXSIZE,
73 FL_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
74 TXD_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
75
76 /*
77 * Max number of TX descriptors we clean up at a time. Should be
78 * modest as freeing skbs isn't cheap and it happens while holding
79 * locks. We just need to free packets faster than they arrive, we
80 * eventually catch up and keep the amortized cost reasonable.
81 */
82 MAX_TX_RECLAIM = 16,
83
84 /*
85 * Max number of Rx buffers we replenish at a time. Again keep this
86 * modest, allocating buffers isn't cheap either.
87 */
88 MAX_RX_REFILL = 16,
89
90 /*
91 * Period of the Rx queue check timer. This timer is infrequent as it
92 * has something to do only when the system experiences severe memory
93 * shortage.
94 */
95 RX_QCHECK_PERIOD = (HZ / 2),
96
97 /*
98 * Period of the TX queue check timer and the maximum number of TX
99 * descriptors to be reclaimed by the TX timer.
100 */
101 TX_QCHECK_PERIOD = (HZ / 2),
102 MAX_TIMER_TX_RECLAIM = 100,
103
104 /*
105 * An FL with <= FL_STARVE_THRES buffers is starving and a periodic
106 * timer will attempt to refill it.
107 */
108 FL_STARVE_THRES = 4,
109
110 /*
111 * Suspend an Ethernet TX queue with fewer available descriptors than
112 * this. We always want to have room for a maximum sized packet:
113 * inline immediate data + MAX_SKB_FRAGS. This is the same as
114 * calc_tx_flits() for a TSO packet with nr_frags == MAX_SKB_FRAGS
115 * (see that function and its helpers for a description of the
116 * calculation).
117 */
118 ETHTXQ_MAX_FRAGS = MAX_SKB_FRAGS + 1,
119 ETHTXQ_MAX_SGL_LEN = ((3 * (ETHTXQ_MAX_FRAGS-1))/2 +
120 ((ETHTXQ_MAX_FRAGS-1) & 1) +
121 2),
122 ETHTXQ_MAX_HDR = (sizeof(struct fw_eth_tx_pkt_vm_wr) +
123 sizeof(struct cpl_tx_pkt_lso_core) +
124 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64),
125 ETHTXQ_MAX_FLITS = ETHTXQ_MAX_SGL_LEN + ETHTXQ_MAX_HDR,
126
127 ETHTXQ_STOP_THRES = 1 + DIV_ROUND_UP(ETHTXQ_MAX_FLITS, TXD_PER_EQ_UNIT),
128
129 /*
130 * Max TX descriptor space we allow for an Ethernet packet to be
131 * inlined into a WR. This is limited by the maximum value which
132 * we can specify for immediate data in the firmware Ethernet TX
133 * Work Request.
134 */
135 MAX_IMM_TX_PKT_LEN = FW_WR_IMMDLEN_MASK,
136
137 /*
138 * Max size of a WR sent through a control TX queue.
139 */
140 MAX_CTRL_WR_LEN = 256,
141
142 /*
143 * Maximum amount of data which we'll ever need to inline into a
144 * TX ring: max(MAX_IMM_TX_PKT_LEN, MAX_CTRL_WR_LEN).
145 */
146 MAX_IMM_TX_LEN = (MAX_IMM_TX_PKT_LEN > MAX_CTRL_WR_LEN
147 ? MAX_IMM_TX_PKT_LEN
148 : MAX_CTRL_WR_LEN),
149
150 /*
151 * For incoming packets less than RX_COPY_THRES, we copy the data into
152 * an skb rather than referencing the data. We allocate enough
153 * in-line room in skb's to accommodate pulling in RX_PULL_LEN bytes
154 * of the data (header).
155 */
156 RX_COPY_THRES = 256,
157 RX_PULL_LEN = 128,
Casey Leedomc6e0d912010-06-25 12:13:28 +0000158
Casey Leedomeb6c5032010-11-11 09:06:50 +0000159 /*
160 * Main body length for sk_buffs used for RX Ethernet packets with
161 * fragments. Should be >= RX_PULL_LEN but possibly bigger to give
162 * pskb_may_pull() some room.
163 */
164 RX_SKB_LEN = 512,
165};
Casey Leedomc6e0d912010-06-25 12:13:28 +0000166
167/*
168 * Software state per TX descriptor.
169 */
170struct tx_sw_desc {
171 struct sk_buff *skb; /* socket buffer of TX data source */
172 struct ulptx_sgl *sgl; /* scatter/gather list in TX Queue */
173};
174
175/*
176 * Software state per RX Free List descriptor. We keep track of the allocated
177 * FL page, its size, and its PCI DMA address (if the page is mapped). The FL
178 * page size and its PCI DMA mapped state are stored in the low bits of the
179 * PCI DMA address as per below.
180 */
181struct rx_sw_desc {
182 struct page *page; /* Free List page buffer */
183 dma_addr_t dma_addr; /* PCI DMA address (if mapped) */
184 /* and flags (see below) */
185};
186
187/*
188 * The low bits of rx_sw_desc.dma_addr have special meaning. Note that the
189 * SGE also uses the low 4 bits to determine the size of the buffer. It uses
190 * those bits to index into the SGE_FL_BUFFER_SIZE[index] register array.
191 * Since we only use SGE_FL_BUFFER_SIZE0 and SGE_FL_BUFFER_SIZE1, these low 4
192 * bits can only contain a 0 or a 1 to indicate which size buffer we're giving
193 * to the SGE. Thus, our software state of "is the buffer mapped for DMA" is
194 * maintained in an inverse sense so the hardware never sees that bit high.
195 */
196enum {
197 RX_LARGE_BUF = 1 << 0, /* buffer is SGE_FL_BUFFER_SIZE[1] */
198 RX_UNMAPPED_BUF = 1 << 1, /* buffer is not mapped */
199};
200
201/**
202 * get_buf_addr - return DMA buffer address of software descriptor
203 * @sdesc: pointer to the software buffer descriptor
204 *
205 * Return the DMA buffer address of a software descriptor (stripping out
206 * our low-order flag bits).
207 */
208static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *sdesc)
209{
210 return sdesc->dma_addr & ~(dma_addr_t)(RX_LARGE_BUF | RX_UNMAPPED_BUF);
211}
212
213/**
214 * is_buf_mapped - is buffer mapped for DMA?
215 * @sdesc: pointer to the software buffer descriptor
216 *
217 * Determine whether the buffer associated with a software descriptor in
218 * mapped for DMA or not.
219 */
220static inline bool is_buf_mapped(const struct rx_sw_desc *sdesc)
221{
222 return !(sdesc->dma_addr & RX_UNMAPPED_BUF);
223}
224
225/**
226 * need_skb_unmap - does the platform need unmapping of sk_buffs?
227 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300228 * Returns true if the platform needs sk_buff unmapping. The compiler
229 * optimizes away unnecessary code if this returns true.
Casey Leedomc6e0d912010-06-25 12:13:28 +0000230 */
231static inline int need_skb_unmap(void)
232{
FUJITA Tomonori57b2eaf2010-07-07 23:52:37 +0000233#ifdef CONFIG_NEED_DMA_MAP_STATE
234 return 1;
235#else
236 return 0;
237#endif
Casey Leedomc6e0d912010-06-25 12:13:28 +0000238}
239
240/**
241 * txq_avail - return the number of available slots in a TX queue
242 * @tq: the TX queue
243 *
244 * Returns the number of available descriptors in a TX queue.
245 */
246static inline unsigned int txq_avail(const struct sge_txq *tq)
247{
248 return tq->size - 1 - tq->in_use;
249}
250
251/**
252 * fl_cap - return the capacity of a Free List
253 * @fl: the Free List
254 *
255 * Returns the capacity of a Free List. The capacity is less than the
256 * size because an Egress Queue Index Unit worth of descriptors needs to
257 * be left unpopulated, otherwise the Producer and Consumer indices PIDX
258 * and CIDX will match and the hardware will think the FL is empty.
259 */
260static inline unsigned int fl_cap(const struct sge_fl *fl)
261{
262 return fl->size - FL_PER_EQ_UNIT;
263}
264
265/**
266 * fl_starving - return whether a Free List is starving.
267 * @fl: the Free List
268 *
269 * Tests specified Free List to see whether the number of buffers
270 * available to the hardware has falled below our "starvation"
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300271 * threshold.
Casey Leedomc6e0d912010-06-25 12:13:28 +0000272 */
273static inline bool fl_starving(const struct sge_fl *fl)
274{
275 return fl->avail - fl->pend_cred <= FL_STARVE_THRES;
276}
277
278/**
279 * map_skb - map an skb for DMA to the device
280 * @dev: the egress net device
281 * @skb: the packet to map
282 * @addr: a pointer to the base of the DMA mapping array
283 *
284 * Map an skb for DMA to the device and return an array of DMA addresses.
285 */
286static int map_skb(struct device *dev, const struct sk_buff *skb,
287 dma_addr_t *addr)
288{
289 const skb_frag_t *fp, *end;
290 const struct skb_shared_info *si;
291
292 *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
293 if (dma_mapping_error(dev, *addr))
294 goto out_err;
295
296 si = skb_shinfo(skb);
297 end = &si->frags[si->nr_frags];
298 for (fp = si->frags; fp < end; fp++) {
299 *++addr = dma_map_page(dev, fp->page, fp->page_offset, fp->size,
300 DMA_TO_DEVICE);
301 if (dma_mapping_error(dev, *addr))
302 goto unwind;
303 }
304 return 0;
305
306unwind:
307 while (fp-- > si->frags)
308 dma_unmap_page(dev, *--addr, fp->size, DMA_TO_DEVICE);
309 dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE);
310
311out_err:
312 return -ENOMEM;
313}
314
315static void unmap_sgl(struct device *dev, const struct sk_buff *skb,
316 const struct ulptx_sgl *sgl, const struct sge_txq *tq)
317{
318 const struct ulptx_sge_pair *p;
319 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
320
321 if (likely(skb_headlen(skb)))
322 dma_unmap_single(dev, be64_to_cpu(sgl->addr0),
323 be32_to_cpu(sgl->len0), DMA_TO_DEVICE);
324 else {
325 dma_unmap_page(dev, be64_to_cpu(sgl->addr0),
326 be32_to_cpu(sgl->len0), DMA_TO_DEVICE);
327 nfrags--;
328 }
329
330 /*
331 * the complexity below is because of the possibility of a wrap-around
332 * in the middle of an SGL
333 */
334 for (p = sgl->sge; nfrags >= 2; nfrags -= 2) {
335 if (likely((u8 *)(p + 1) <= (u8 *)tq->stat)) {
336unmap:
337 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
338 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
339 dma_unmap_page(dev, be64_to_cpu(p->addr[1]),
340 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
341 p++;
342 } else if ((u8 *)p == (u8 *)tq->stat) {
343 p = (const struct ulptx_sge_pair *)tq->desc;
344 goto unmap;
345 } else if ((u8 *)p + 8 == (u8 *)tq->stat) {
346 const __be64 *addr = (const __be64 *)tq->desc;
347
348 dma_unmap_page(dev, be64_to_cpu(addr[0]),
349 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
350 dma_unmap_page(dev, be64_to_cpu(addr[1]),
351 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
352 p = (const struct ulptx_sge_pair *)&addr[2];
353 } else {
354 const __be64 *addr = (const __be64 *)tq->desc;
355
356 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
357 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
358 dma_unmap_page(dev, be64_to_cpu(addr[0]),
359 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
360 p = (const struct ulptx_sge_pair *)&addr[1];
361 }
362 }
363 if (nfrags) {
364 __be64 addr;
365
366 if ((u8 *)p == (u8 *)tq->stat)
367 p = (const struct ulptx_sge_pair *)tq->desc;
368 addr = ((u8 *)p + 16 <= (u8 *)tq->stat
369 ? p->addr[0]
370 : *(const __be64 *)tq->desc);
371 dma_unmap_page(dev, be64_to_cpu(addr), be32_to_cpu(p->len[0]),
372 DMA_TO_DEVICE);
373 }
374}
375
376/**
377 * free_tx_desc - reclaims TX descriptors and their buffers
378 * @adapter: the adapter
379 * @tq: the TX queue to reclaim descriptors from
380 * @n: the number of descriptors to reclaim
381 * @unmap: whether the buffers should be unmapped for DMA
382 *
383 * Reclaims TX descriptors from an SGE TX queue and frees the associated
384 * TX buffers. Called with the TX queue lock held.
385 */
386static void free_tx_desc(struct adapter *adapter, struct sge_txq *tq,
387 unsigned int n, bool unmap)
388{
389 struct tx_sw_desc *sdesc;
390 unsigned int cidx = tq->cidx;
391 struct device *dev = adapter->pdev_dev;
392
393 const int need_unmap = need_skb_unmap() && unmap;
394
395 sdesc = &tq->sdesc[cidx];
396 while (n--) {
397 /*
398 * If we kept a reference to the original TX skb, we need to
399 * unmap it from PCI DMA space (if required) and free it.
400 */
401 if (sdesc->skb) {
402 if (need_unmap)
403 unmap_sgl(dev, sdesc->skb, sdesc->sgl, tq);
404 kfree_skb(sdesc->skb);
405 sdesc->skb = NULL;
406 }
407
408 sdesc++;
409 if (++cidx == tq->size) {
410 cidx = 0;
411 sdesc = tq->sdesc;
412 }
413 }
414 tq->cidx = cidx;
415}
416
417/*
418 * Return the number of reclaimable descriptors in a TX queue.
419 */
420static inline int reclaimable(const struct sge_txq *tq)
421{
422 int hw_cidx = be16_to_cpu(tq->stat->cidx);
423 int reclaimable = hw_cidx - tq->cidx;
424 if (reclaimable < 0)
425 reclaimable += tq->size;
426 return reclaimable;
427}
428
429/**
430 * reclaim_completed_tx - reclaims completed TX descriptors
431 * @adapter: the adapter
432 * @tq: the TX queue to reclaim completed descriptors from
433 * @unmap: whether the buffers should be unmapped for DMA
434 *
435 * Reclaims TX descriptors that the SGE has indicated it has processed,
436 * and frees the associated buffers if possible. Called with the TX
437 * queue locked.
438 */
439static inline void reclaim_completed_tx(struct adapter *adapter,
440 struct sge_txq *tq,
441 bool unmap)
442{
443 int avail = reclaimable(tq);
444
445 if (avail) {
446 /*
447 * Limit the amount of clean up work we do at a time to keep
448 * the TX lock hold time O(1).
449 */
450 if (avail > MAX_TX_RECLAIM)
451 avail = MAX_TX_RECLAIM;
452
453 free_tx_desc(adapter, tq, avail, unmap);
454 tq->in_use -= avail;
455 }
456}
457
458/**
459 * get_buf_size - return the size of an RX Free List buffer.
460 * @sdesc: pointer to the software buffer descriptor
461 */
462static inline int get_buf_size(const struct rx_sw_desc *sdesc)
463{
464 return FL_PG_ORDER > 0 && (sdesc->dma_addr & RX_LARGE_BUF)
465 ? (PAGE_SIZE << FL_PG_ORDER)
466 : PAGE_SIZE;
467}
468
469/**
470 * free_rx_bufs - free RX buffers on an SGE Free List
471 * @adapter: the adapter
472 * @fl: the SGE Free List to free buffers from
473 * @n: how many buffers to free
474 *
475 * Release the next @n buffers on an SGE Free List RX queue. The
476 * buffers must be made inaccessible to hardware before calling this
477 * function.
478 */
479static void free_rx_bufs(struct adapter *adapter, struct sge_fl *fl, int n)
480{
481 while (n--) {
482 struct rx_sw_desc *sdesc = &fl->sdesc[fl->cidx];
483
484 if (is_buf_mapped(sdesc))
485 dma_unmap_page(adapter->pdev_dev, get_buf_addr(sdesc),
486 get_buf_size(sdesc), PCI_DMA_FROMDEVICE);
487 put_page(sdesc->page);
488 sdesc->page = NULL;
489 if (++fl->cidx == fl->size)
490 fl->cidx = 0;
491 fl->avail--;
492 }
493}
494
495/**
496 * unmap_rx_buf - unmap the current RX buffer on an SGE Free List
497 * @adapter: the adapter
498 * @fl: the SGE Free List
499 *
500 * Unmap the current buffer on an SGE Free List RX queue. The
501 * buffer must be made inaccessible to HW before calling this function.
502 *
503 * This is similar to @free_rx_bufs above but does not free the buffer.
504 * Do note that the FL still loses any further access to the buffer.
505 * This is used predominantly to "transfer ownership" of an FL buffer
506 * to another entity (typically an skb's fragment list).
507 */
508static void unmap_rx_buf(struct adapter *adapter, struct sge_fl *fl)
509{
510 struct rx_sw_desc *sdesc = &fl->sdesc[fl->cidx];
511
512 if (is_buf_mapped(sdesc))
513 dma_unmap_page(adapter->pdev_dev, get_buf_addr(sdesc),
514 get_buf_size(sdesc), PCI_DMA_FROMDEVICE);
515 sdesc->page = NULL;
516 if (++fl->cidx == fl->size)
517 fl->cidx = 0;
518 fl->avail--;
519}
520
521/**
522 * ring_fl_db - righ doorbell on free list
523 * @adapter: the adapter
524 * @fl: the Free List whose doorbell should be rung ...
525 *
526 * Tell the Scatter Gather Engine that there are new free list entries
527 * available.
528 */
529static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
530{
531 /*
532 * The SGE keeps track of its Producer and Consumer Indices in terms
533 * of Egress Queue Units so we can only tell it about integral numbers
534 * of multiples of Free List Entries per Egress Queue Units ...
535 */
536 if (fl->pend_cred >= FL_PER_EQ_UNIT) {
537 wmb();
538 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
539 DBPRIO |
540 QID(fl->cntxt_id) |
541 PIDX(fl->pend_cred / FL_PER_EQ_UNIT));
542 fl->pend_cred %= FL_PER_EQ_UNIT;
543 }
544}
545
546/**
547 * set_rx_sw_desc - initialize software RX buffer descriptor
548 * @sdesc: pointer to the softwore RX buffer descriptor
549 * @page: pointer to the page data structure backing the RX buffer
550 * @dma_addr: PCI DMA address (possibly with low-bit flags)
551 */
552static inline void set_rx_sw_desc(struct rx_sw_desc *sdesc, struct page *page,
553 dma_addr_t dma_addr)
554{
555 sdesc->page = page;
556 sdesc->dma_addr = dma_addr;
557}
558
559/*
560 * Support for poisoning RX buffers ...
561 */
562#define POISON_BUF_VAL -1
563
564static inline void poison_buf(struct page *page, size_t sz)
565{
566#if POISON_BUF_VAL >= 0
567 memset(page_address(page), POISON_BUF_VAL, sz);
568#endif
569}
570
571/**
572 * refill_fl - refill an SGE RX buffer ring
573 * @adapter: the adapter
574 * @fl: the Free List ring to refill
575 * @n: the number of new buffers to allocate
576 * @gfp: the gfp flags for the allocations
577 *
578 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
579 * allocated with the supplied gfp flags. The caller must assure that
580 * @n does not exceed the queue's capacity -- i.e. (cidx == pidx) _IN
581 * EGRESS QUEUE UNITS_ indicates an empty Free List! Returns the number
582 * of buffers allocated. If afterwards the queue is found critically low,
583 * mark it as starving in the bitmap of starving FLs.
584 */
585static unsigned int refill_fl(struct adapter *adapter, struct sge_fl *fl,
586 int n, gfp_t gfp)
587{
588 struct page *page;
589 dma_addr_t dma_addr;
590 unsigned int cred = fl->avail;
591 __be64 *d = &fl->desc[fl->pidx];
592 struct rx_sw_desc *sdesc = &fl->sdesc[fl->pidx];
593
594 /*
595 * Sanity: ensure that the result of adding n Free List buffers
596 * won't result in wrapping the SGE's Producer Index around to
597 * it's Consumer Index thereby indicating an empty Free List ...
598 */
599 BUG_ON(fl->avail + n > fl->size - FL_PER_EQ_UNIT);
600
601 /*
602 * If we support large pages, prefer large buffers and fail over to
603 * small pages if we can't allocate large pages to satisfy the refill.
604 * If we don't support large pages, drop directly into the small page
605 * allocation code.
606 */
607 if (FL_PG_ORDER == 0)
608 goto alloc_small_pages;
609
610 while (n) {
611 page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN,
612 FL_PG_ORDER);
613 if (unlikely(!page)) {
614 /*
615 * We've failed inour attempt to allocate a "large
616 * page". Fail over to the "small page" allocation
617 * below.
618 */
619 fl->large_alloc_failed++;
620 break;
621 }
622 poison_buf(page, PAGE_SIZE << FL_PG_ORDER);
623
624 dma_addr = dma_map_page(adapter->pdev_dev, page, 0,
625 PAGE_SIZE << FL_PG_ORDER,
626 PCI_DMA_FROMDEVICE);
627 if (unlikely(dma_mapping_error(adapter->pdev_dev, dma_addr))) {
628 /*
629 * We've run out of DMA mapping space. Free up the
630 * buffer and return with what we've managed to put
631 * into the free list. We don't want to fail over to
632 * the small page allocation below in this case
633 * because DMA mapping resources are typically
634 * critical resources once they become scarse.
635 */
636 __free_pages(page, FL_PG_ORDER);
637 goto out;
638 }
639 dma_addr |= RX_LARGE_BUF;
640 *d++ = cpu_to_be64(dma_addr);
641
642 set_rx_sw_desc(sdesc, page, dma_addr);
643 sdesc++;
644
645 fl->avail++;
646 if (++fl->pidx == fl->size) {
647 fl->pidx = 0;
648 sdesc = fl->sdesc;
649 d = fl->desc;
650 }
651 n--;
652 }
653
654alloc_small_pages:
655 while (n--) {
656 page = __netdev_alloc_page(adapter->port[0],
657 gfp | __GFP_NOWARN);
658 if (unlikely(!page)) {
659 fl->alloc_failed++;
660 break;
661 }
662 poison_buf(page, PAGE_SIZE);
663
664 dma_addr = dma_map_page(adapter->pdev_dev, page, 0, PAGE_SIZE,
665 PCI_DMA_FROMDEVICE);
666 if (unlikely(dma_mapping_error(adapter->pdev_dev, dma_addr))) {
667 netdev_free_page(adapter->port[0], page);
668 break;
669 }
670 *d++ = cpu_to_be64(dma_addr);
671
672 set_rx_sw_desc(sdesc, page, dma_addr);
673 sdesc++;
674
675 fl->avail++;
676 if (++fl->pidx == fl->size) {
677 fl->pidx = 0;
678 sdesc = fl->sdesc;
679 d = fl->desc;
680 }
681 }
682
683out:
684 /*
685 * Update our accounting state to incorporate the new Free List
686 * buffers, tell the hardware about them and return the number of
687 * bufers which we were able to allocate.
688 */
689 cred = fl->avail - cred;
690 fl->pend_cred += cred;
691 ring_fl_db(adapter, fl);
692
693 if (unlikely(fl_starving(fl))) {
694 smp_wmb();
695 set_bit(fl->cntxt_id, adapter->sge.starving_fl);
696 }
697
698 return cred;
699}
700
701/*
702 * Refill a Free List to its capacity or the Maximum Refill Increment,
703 * whichever is smaller ...
704 */
705static inline void __refill_fl(struct adapter *adapter, struct sge_fl *fl)
706{
707 refill_fl(adapter, fl,
708 min((unsigned int)MAX_RX_REFILL, fl_cap(fl) - fl->avail),
709 GFP_ATOMIC);
710}
711
712/**
713 * alloc_ring - allocate resources for an SGE descriptor ring
714 * @dev: the PCI device's core device
715 * @nelem: the number of descriptors
716 * @hwsize: the size of each hardware descriptor
717 * @swsize: the size of each software descriptor
718 * @busaddrp: the physical PCI bus address of the allocated ring
719 * @swringp: return address pointer for software ring
720 * @stat_size: extra space in hardware ring for status information
721 *
722 * Allocates resources for an SGE descriptor ring, such as TX queues,
723 * free buffer lists, response queues, etc. Each SGE ring requires
724 * space for its hardware descriptors plus, optionally, space for software
725 * state associated with each hardware entry (the metadata). The function
726 * returns three values: the virtual address for the hardware ring (the
727 * return value of the function), the PCI bus address of the hardware
728 * ring (in *busaddrp), and the address of the software ring (in swringp).
729 * Both the hardware and software rings are returned zeroed out.
730 */
731static void *alloc_ring(struct device *dev, size_t nelem, size_t hwsize,
732 size_t swsize, dma_addr_t *busaddrp, void *swringp,
733 size_t stat_size)
734{
735 /*
736 * Allocate the hardware ring and PCI DMA bus address space for said.
737 */
738 size_t hwlen = nelem * hwsize + stat_size;
739 void *hwring = dma_alloc_coherent(dev, hwlen, busaddrp, GFP_KERNEL);
740
741 if (!hwring)
742 return NULL;
743
744 /*
745 * If the caller wants a software ring, allocate it and return a
746 * pointer to it in *swringp.
747 */
748 BUG_ON((swsize != 0) != (swringp != NULL));
749 if (swsize) {
750 void *swring = kcalloc(nelem, swsize, GFP_KERNEL);
751
752 if (!swring) {
753 dma_free_coherent(dev, hwlen, hwring, *busaddrp);
754 return NULL;
755 }
756 *(void **)swringp = swring;
757 }
758
759 /*
760 * Zero out the hardware ring and return its address as our function
761 * value.
762 */
763 memset(hwring, 0, hwlen);
764 return hwring;
765}
766
767/**
768 * sgl_len - calculates the size of an SGL of the given capacity
769 * @n: the number of SGL entries
770 *
771 * Calculates the number of flits (8-byte units) needed for a Direct
772 * Scatter/Gather List that can hold the given number of entries.
773 */
774static inline unsigned int sgl_len(unsigned int n)
775{
776 /*
777 * A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA
778 * addresses. The DSGL Work Request starts off with a 32-bit DSGL
779 * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N,
780 * repeated sequences of { Length[i], Length[i+1], Address[i],
781 * Address[i+1] } (this ensures that all addresses are on 64-bit
782 * boundaries). If N is even, then Length[N+1] should be set to 0 and
783 * Address[N+1] is omitted.
784 *
785 * The following calculation incorporates all of the above. It's
786 * somewhat hard to follow but, briefly: the "+2" accounts for the
787 * first two flits which include the DSGL header, Length0 and
788 * Address0; the "(3*(n-1))/2" covers the main body of list entries (3
789 * flits for every pair of the remaining N) +1 if (n-1) is odd; and
790 * finally the "+((n-1)&1)" adds the one remaining flit needed if
791 * (n-1) is odd ...
792 */
793 n--;
794 return (3 * n) / 2 + (n & 1) + 2;
795}
796
797/**
798 * flits_to_desc - returns the num of TX descriptors for the given flits
799 * @flits: the number of flits
800 *
801 * Returns the number of TX descriptors needed for the supplied number
802 * of flits.
803 */
804static inline unsigned int flits_to_desc(unsigned int flits)
805{
806 BUG_ON(flits > SGE_MAX_WR_LEN / sizeof(__be64));
807 return DIV_ROUND_UP(flits, TXD_PER_EQ_UNIT);
808}
809
810/**
811 * is_eth_imm - can an Ethernet packet be sent as immediate data?
812 * @skb: the packet
813 *
814 * Returns whether an Ethernet packet is small enough to fit completely as
815 * immediate data.
816 */
817static inline int is_eth_imm(const struct sk_buff *skb)
818{
819 /*
820 * The VF Driver uses the FW_ETH_TX_PKT_VM_WR firmware Work Request
821 * which does not accommodate immediate data. We could dike out all
822 * of the support code for immediate data but that would tie our hands
823 * too much if we ever want to enhace the firmware. It would also
824 * create more differences between the PF and VF Drivers.
825 */
826 return false;
827}
828
829/**
830 * calc_tx_flits - calculate the number of flits for a packet TX WR
831 * @skb: the packet
832 *
833 * Returns the number of flits needed for a TX Work Request for the
834 * given Ethernet packet, including the needed WR and CPL headers.
835 */
836static inline unsigned int calc_tx_flits(const struct sk_buff *skb)
837{
838 unsigned int flits;
839
840 /*
841 * If the skb is small enough, we can pump it out as a work request
842 * with only immediate data. In that case we just have to have the
843 * TX Packet header plus the skb data in the Work Request.
844 */
845 if (is_eth_imm(skb))
846 return DIV_ROUND_UP(skb->len + sizeof(struct cpl_tx_pkt),
847 sizeof(__be64));
848
849 /*
850 * Otherwise, we're going to have to construct a Scatter gather list
851 * of the skb body and fragments. We also include the flits necessary
852 * for the TX Packet Work Request and CPL. We always have a firmware
853 * Write Header (incorporated as part of the cpl_tx_pkt_lso and
854 * cpl_tx_pkt structures), followed by either a TX Packet Write CPL
855 * message or, if we're doing a Large Send Offload, an LSO CPL message
856 * with an embeded TX Packet Write CPL message.
857 */
858 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1);
859 if (skb_shinfo(skb)->gso_size)
860 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
861 sizeof(struct cpl_tx_pkt_lso_core) +
862 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
863 else
864 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
865 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
866 return flits;
867}
868
869/**
870 * write_sgl - populate a Scatter/Gather List for a packet
871 * @skb: the packet
872 * @tq: the TX queue we are writing into
873 * @sgl: starting location for writing the SGL
874 * @end: points right after the end of the SGL
875 * @start: start offset into skb main-body data to include in the SGL
876 * @addr: the list of DMA bus addresses for the SGL elements
877 *
878 * Generates a Scatter/Gather List for the buffers that make up a packet.
879 * The caller must provide adequate space for the SGL that will be written.
880 * The SGL includes all of the packet's page fragments and the data in its
881 * main body except for the first @start bytes. @pos must be 16-byte
882 * aligned and within a TX descriptor with available space. @end points
883 * write after the end of the SGL but does not account for any potential
884 * wrap around, i.e., @end > @tq->stat.
885 */
886static void write_sgl(const struct sk_buff *skb, struct sge_txq *tq,
887 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
888 const dma_addr_t *addr)
889{
890 unsigned int i, len;
891 struct ulptx_sge_pair *to;
892 const struct skb_shared_info *si = skb_shinfo(skb);
893 unsigned int nfrags = si->nr_frags;
894 struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1];
895
896 len = skb_headlen(skb) - start;
897 if (likely(len)) {
898 sgl->len0 = htonl(len);
899 sgl->addr0 = cpu_to_be64(addr[0] + start);
900 nfrags++;
901 } else {
902 sgl->len0 = htonl(si->frags[0].size);
903 sgl->addr0 = cpu_to_be64(addr[1]);
904 }
905
906 sgl->cmd_nsge = htonl(ULPTX_CMD(ULP_TX_SC_DSGL) |
907 ULPTX_NSGE(nfrags));
908 if (likely(--nfrags == 0))
909 return;
910 /*
911 * Most of the complexity below deals with the possibility we hit the
912 * end of the queue in the middle of writing the SGL. For this case
913 * only we create the SGL in a temporary buffer and then copy it.
914 */
915 to = (u8 *)end > (u8 *)tq->stat ? buf : sgl->sge;
916
917 for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) {
918 to->len[0] = cpu_to_be32(si->frags[i].size);
919 to->len[1] = cpu_to_be32(si->frags[++i].size);
920 to->addr[0] = cpu_to_be64(addr[i]);
921 to->addr[1] = cpu_to_be64(addr[++i]);
922 }
923 if (nfrags) {
924 to->len[0] = cpu_to_be32(si->frags[i].size);
925 to->len[1] = cpu_to_be32(0);
926 to->addr[0] = cpu_to_be64(addr[i + 1]);
927 }
928 if (unlikely((u8 *)end > (u8 *)tq->stat)) {
929 unsigned int part0 = (u8 *)tq->stat - (u8 *)sgl->sge, part1;
930
931 if (likely(part0))
932 memcpy(sgl->sge, buf, part0);
933 part1 = (u8 *)end - (u8 *)tq->stat;
934 memcpy(tq->desc, (u8 *)buf + part0, part1);
935 end = (void *)tq->desc + part1;
936 }
937 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
938 *(u64 *)end = 0;
939}
940
941/**
942 * check_ring_tx_db - check and potentially ring a TX queue's doorbell
943 * @adapter: the adapter
944 * @tq: the TX queue
945 * @n: number of new descriptors to give to HW
946 *
947 * Ring the doorbel for a TX queue.
948 */
949static inline void ring_tx_db(struct adapter *adapter, struct sge_txq *tq,
950 int n)
951{
952 /*
953 * Warn if we write doorbells with the wrong priority and write
954 * descriptors before telling HW.
955 */
956 WARN_ON((QID(tq->cntxt_id) | PIDX(n)) & DBPRIO);
957 wmb();
958 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
959 QID(tq->cntxt_id) | PIDX(n));
960}
961
962/**
963 * inline_tx_skb - inline a packet's data into TX descriptors
964 * @skb: the packet
965 * @tq: the TX queue where the packet will be inlined
966 * @pos: starting position in the TX queue to inline the packet
967 *
968 * Inline a packet's contents directly into TX descriptors, starting at
969 * the given position within the TX DMA ring.
970 * Most of the complexity of this operation is dealing with wrap arounds
971 * in the middle of the packet we want to inline.
972 */
973static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *tq,
974 void *pos)
975{
976 u64 *p;
977 int left = (void *)tq->stat - pos;
978
979 if (likely(skb->len <= left)) {
980 if (likely(!skb->data_len))
981 skb_copy_from_linear_data(skb, pos, skb->len);
982 else
983 skb_copy_bits(skb, 0, pos, skb->len);
984 pos += skb->len;
985 } else {
986 skb_copy_bits(skb, 0, pos, left);
987 skb_copy_bits(skb, left, tq->desc, skb->len - left);
988 pos = (void *)tq->desc + (skb->len - left);
989 }
990
991 /* 0-pad to multiple of 16 */
992 p = PTR_ALIGN(pos, 8);
993 if ((uintptr_t)p & 8)
994 *p = 0;
995}
996
997/*
998 * Figure out what HW csum a packet wants and return the appropriate control
999 * bits.
1000 */
1001static u64 hwcsum(const struct sk_buff *skb)
1002{
1003 int csum_type;
1004 const struct iphdr *iph = ip_hdr(skb);
1005
1006 if (iph->version == 4) {
1007 if (iph->protocol == IPPROTO_TCP)
1008 csum_type = TX_CSUM_TCPIP;
1009 else if (iph->protocol == IPPROTO_UDP)
1010 csum_type = TX_CSUM_UDPIP;
1011 else {
1012nocsum:
1013 /*
1014 * unknown protocol, disable HW csum
1015 * and hope a bad packet is detected
1016 */
1017 return TXPKT_L4CSUM_DIS;
1018 }
1019 } else {
1020 /*
1021 * this doesn't work with extension headers
1022 */
1023 const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph;
1024
1025 if (ip6h->nexthdr == IPPROTO_TCP)
1026 csum_type = TX_CSUM_TCPIP6;
1027 else if (ip6h->nexthdr == IPPROTO_UDP)
1028 csum_type = TX_CSUM_UDPIP6;
1029 else
1030 goto nocsum;
1031 }
1032
1033 if (likely(csum_type >= TX_CSUM_TCPIP))
1034 return TXPKT_CSUM_TYPE(csum_type) |
1035 TXPKT_IPHDR_LEN(skb_network_header_len(skb)) |
1036 TXPKT_ETHHDR_LEN(skb_network_offset(skb) - ETH_HLEN);
1037 else {
1038 int start = skb_transport_offset(skb);
1039
1040 return TXPKT_CSUM_TYPE(csum_type) |
1041 TXPKT_CSUM_START(start) |
1042 TXPKT_CSUM_LOC(start + skb->csum_offset);
1043 }
1044}
1045
1046/*
1047 * Stop an Ethernet TX queue and record that state change.
1048 */
1049static void txq_stop(struct sge_eth_txq *txq)
1050{
1051 netif_tx_stop_queue(txq->txq);
1052 txq->q.stops++;
1053}
1054
1055/*
1056 * Advance our software state for a TX queue by adding n in use descriptors.
1057 */
1058static inline void txq_advance(struct sge_txq *tq, unsigned int n)
1059{
1060 tq->in_use += n;
1061 tq->pidx += n;
1062 if (tq->pidx >= tq->size)
1063 tq->pidx -= tq->size;
1064}
1065
1066/**
1067 * t4vf_eth_xmit - add a packet to an Ethernet TX queue
1068 * @skb: the packet
1069 * @dev: the egress net device
1070 *
1071 * Add a packet to an SGE Ethernet TX queue. Runs with softirqs disabled.
1072 */
1073int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1074{
Casey Leedom7f9dd2f2010-07-12 14:39:07 -07001075 u32 wr_mid;
Casey Leedomc6e0d912010-06-25 12:13:28 +00001076 u64 cntrl, *end;
1077 int qidx, credits;
1078 unsigned int flits, ndesc;
1079 struct adapter *adapter;
1080 struct sge_eth_txq *txq;
1081 const struct port_info *pi;
1082 struct fw_eth_tx_pkt_vm_wr *wr;
1083 struct cpl_tx_pkt_core *cpl;
1084 const struct skb_shared_info *ssi;
1085 dma_addr_t addr[MAX_SKB_FRAGS + 1];
1086 const size_t fw_hdr_copy_len = (sizeof(wr->ethmacdst) +
1087 sizeof(wr->ethmacsrc) +
1088 sizeof(wr->ethtype) +
1089 sizeof(wr->vlantci));
1090
1091 /*
1092 * The chip minimum packet length is 10 octets but the firmware
1093 * command that we are using requires that we copy the Ethernet header
1094 * (including the VLAN tag) into the header so we reject anything
1095 * smaller than that ...
1096 */
1097 if (unlikely(skb->len < fw_hdr_copy_len))
1098 goto out_free;
1099
1100 /*
1101 * Figure out which TX Queue we're going to use.
1102 */
1103 pi = netdev_priv(dev);
1104 adapter = pi->adapter;
1105 qidx = skb_get_queue_mapping(skb);
1106 BUG_ON(qidx >= pi->nqsets);
1107 txq = &adapter->sge.ethtxq[pi->first_qset + qidx];
1108
1109 /*
1110 * Take this opportunity to reclaim any TX Descriptors whose DMA
1111 * transfers have completed.
1112 */
1113 reclaim_completed_tx(adapter, &txq->q, true);
1114
1115 /*
1116 * Calculate the number of flits and TX Descriptors we're going to
1117 * need along with how many TX Descriptors will be left over after
1118 * we inject our Work Request.
1119 */
1120 flits = calc_tx_flits(skb);
1121 ndesc = flits_to_desc(flits);
1122 credits = txq_avail(&txq->q) - ndesc;
1123
1124 if (unlikely(credits < 0)) {
1125 /*
1126 * Not enough room for this packet's Work Request. Stop the
1127 * TX Queue and return a "busy" condition. The queue will get
1128 * started later on when the firmware informs us that space
1129 * has opened up.
1130 */
1131 txq_stop(txq);
1132 dev_err(adapter->pdev_dev,
1133 "%s: TX ring %u full while queue awake!\n",
1134 dev->name, qidx);
1135 return NETDEV_TX_BUSY;
1136 }
1137
1138 if (!is_eth_imm(skb) &&
1139 unlikely(map_skb(adapter->pdev_dev, skb, addr) < 0)) {
1140 /*
1141 * We need to map the skb into PCI DMA space (because it can't
1142 * be in-lined directly into the Work Request) and the mapping
1143 * operation failed. Record the error and drop the packet.
1144 */
1145 txq->mapping_err++;
1146 goto out_free;
1147 }
1148
Casey Leedom7f9dd2f2010-07-12 14:39:07 -07001149 wr_mid = FW_WR_LEN16(DIV_ROUND_UP(flits, 2));
Casey Leedomc6e0d912010-06-25 12:13:28 +00001150 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
1151 /*
1152 * After we're done injecting the Work Request for this
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001153 * packet, we'll be below our "stop threshold" so stop the TX
Casey Leedom7f9dd2f2010-07-12 14:39:07 -07001154 * Queue now and schedule a request for an SGE Egress Queue
1155 * Update message. The queue will get started later on when
1156 * the firmware processes this Work Request and sends us an
1157 * Egress Queue Status Update message indicating that space
1158 * has opened up.
Casey Leedomc6e0d912010-06-25 12:13:28 +00001159 */
1160 txq_stop(txq);
Casey Leedom7f9dd2f2010-07-12 14:39:07 -07001161 wr_mid |= FW_WR_EQUEQ | FW_WR_EQUIQ;
Casey Leedomc6e0d912010-06-25 12:13:28 +00001162 }
1163
1164 /*
1165 * Start filling in our Work Request. Note that we do _not_ handle
1166 * the WR Header wrapping around the TX Descriptor Ring. If our
1167 * maximum header size ever exceeds one TX Descriptor, we'll need to
1168 * do something else here.
1169 */
1170 BUG_ON(DIV_ROUND_UP(ETHTXQ_MAX_HDR, TXD_PER_EQ_UNIT) > 1);
1171 wr = (void *)&txq->q.desc[txq->q.pidx];
Casey Leedom7f9dd2f2010-07-12 14:39:07 -07001172 wr->equiq_to_len16 = cpu_to_be32(wr_mid);
Casey Leedomc6e0d912010-06-25 12:13:28 +00001173 wr->r3[0] = cpu_to_be64(0);
1174 wr->r3[1] = cpu_to_be64(0);
1175 skb_copy_from_linear_data(skb, (void *)wr->ethmacdst, fw_hdr_copy_len);
1176 end = (u64 *)wr + flits;
1177
1178 /*
1179 * If this is a Large Send Offload packet we'll put in an LSO CPL
1180 * message with an encapsulated TX Packet CPL message. Otherwise we
1181 * just use a TX Packet CPL message.
1182 */
1183 ssi = skb_shinfo(skb);
1184 if (ssi->gso_size) {
1185 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
1186 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0;
1187 int l3hdr_len = skb_network_header_len(skb);
1188 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1189
1190 wr->op_immdlen =
1191 cpu_to_be32(FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
1192 FW_WR_IMMDLEN(sizeof(*lso) +
1193 sizeof(*cpl)));
1194 /*
1195 * Fill in the LSO CPL message.
1196 */
1197 lso->lso_ctrl =
1198 cpu_to_be32(LSO_OPCODE(CPL_TX_PKT_LSO) |
1199 LSO_FIRST_SLICE |
1200 LSO_LAST_SLICE |
1201 LSO_IPV6(v6) |
1202 LSO_ETHHDR_LEN(eth_xtra_len/4) |
1203 LSO_IPHDR_LEN(l3hdr_len/4) |
1204 LSO_TCPHDR_LEN(tcp_hdr(skb)->doff));
1205 lso->ipid_ofst = cpu_to_be16(0);
1206 lso->mss = cpu_to_be16(ssi->gso_size);
1207 lso->seqno_offset = cpu_to_be32(0);
1208 lso->len = cpu_to_be32(skb->len);
1209
1210 /*
1211 * Set up TX Packet CPL pointer, control word and perform
1212 * accounting.
1213 */
1214 cpl = (void *)(lso + 1);
1215 cntrl = (TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1216 TXPKT_IPHDR_LEN(l3hdr_len) |
1217 TXPKT_ETHHDR_LEN(eth_xtra_len));
1218 txq->tso++;
1219 txq->tx_cso += ssi->gso_segs;
1220 } else {
1221 int len;
1222
1223 len = is_eth_imm(skb) ? skb->len + sizeof(*cpl) : sizeof(*cpl);
1224 wr->op_immdlen =
1225 cpu_to_be32(FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
1226 FW_WR_IMMDLEN(len));
1227
1228 /*
1229 * Set up TX Packet CPL pointer, control word and perform
1230 * accounting.
1231 */
1232 cpl = (void *)(wr + 1);
1233 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1234 cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS;
1235 txq->tx_cso++;
1236 } else
1237 cntrl = TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS;
1238 }
1239
1240 /*
1241 * If there's a VLAN tag present, add that to the list of things to
1242 * do in this Work Request.
1243 */
1244 if (vlan_tx_tag_present(skb)) {
1245 txq->vlan_ins++;
1246 cntrl |= TXPKT_VLAN_VLD | TXPKT_VLAN(vlan_tx_tag_get(skb));
1247 }
1248
1249 /*
1250 * Fill in the TX Packet CPL message header.
1251 */
1252 cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE(CPL_TX_PKT_XT) |
1253 TXPKT_INTF(pi->port_id) |
1254 TXPKT_PF(0));
1255 cpl->pack = cpu_to_be16(0);
1256 cpl->len = cpu_to_be16(skb->len);
1257 cpl->ctrl1 = cpu_to_be64(cntrl);
1258
1259#ifdef T4_TRACE
1260 T4_TRACE5(adapter->tb[txq->q.cntxt_id & 7],
1261 "eth_xmit: ndesc %u, credits %u, pidx %u, len %u, frags %u",
1262 ndesc, credits, txq->q.pidx, skb->len, ssi->nr_frags);
1263#endif
1264
1265 /*
1266 * Fill in the body of the TX Packet CPL message with either in-lined
1267 * data or a Scatter/Gather List.
1268 */
1269 if (is_eth_imm(skb)) {
1270 /*
1271 * In-line the packet's data and free the skb since we don't
1272 * need it any longer.
1273 */
1274 inline_tx_skb(skb, &txq->q, cpl + 1);
1275 dev_kfree_skb(skb);
1276 } else {
1277 /*
1278 * Write the skb's Scatter/Gather list into the TX Packet CPL
1279 * message and retain a pointer to the skb so we can free it
1280 * later when its DMA completes. (We store the skb pointer
1281 * in the Software Descriptor corresponding to the last TX
1282 * Descriptor used by the Work Request.)
1283 *
1284 * The retained skb will be freed when the corresponding TX
1285 * Descriptors are reclaimed after their DMAs complete.
1286 * However, this could take quite a while since, in general,
1287 * the hardware is set up to be lazy about sending DMA
1288 * completion notifications to us and we mostly perform TX
1289 * reclaims in the transmit routine.
1290 *
1291 * This is good for performamce but means that we rely on new
1292 * TX packets arriving to run the destructors of completed
1293 * packets, which open up space in their sockets' send queues.
1294 * Sometimes we do not get such new packets causing TX to
1295 * stall. A single UDP transmitter is a good example of this
1296 * situation. We have a clean up timer that periodically
1297 * reclaims completed packets but it doesn't run often enough
1298 * (nor do we want it to) to prevent lengthy stalls. A
1299 * solution to this problem is to run the destructor early,
1300 * after the packet is queued but before it's DMAd. A con is
1301 * that we lie to socket memory accounting, but the amount of
1302 * extra memory is reasonable (limited by the number of TX
1303 * descriptors), the packets do actually get freed quickly by
1304 * new packets almost always, and for protocols like TCP that
1305 * wait for acks to really free up the data the extra memory
1306 * is even less. On the positive side we run the destructors
1307 * on the sending CPU rather than on a potentially different
Casey Leedom64bb3362010-06-29 12:53:39 +00001308 * completing CPU, usually a good thing.
Casey Leedomc6e0d912010-06-25 12:13:28 +00001309 *
1310 * Run the destructor before telling the DMA engine about the
1311 * packet to make sure it doesn't complete and get freed
1312 * prematurely.
1313 */
1314 struct ulptx_sgl *sgl = (struct ulptx_sgl *)(cpl + 1);
1315 struct sge_txq *tq = &txq->q;
1316 int last_desc;
1317
1318 /*
1319 * If the Work Request header was an exact multiple of our TX
1320 * Descriptor length, then it's possible that the starting SGL
1321 * pointer lines up exactly with the end of our TX Descriptor
1322 * ring. If that's the case, wrap around to the beginning
1323 * here ...
1324 */
1325 if (unlikely((void *)sgl == (void *)tq->stat)) {
1326 sgl = (void *)tq->desc;
1327 end = (void *)((void *)tq->desc +
1328 ((void *)end - (void *)tq->stat));
1329 }
1330
1331 write_sgl(skb, tq, sgl, end, 0, addr);
1332 skb_orphan(skb);
1333
1334 last_desc = tq->pidx + ndesc - 1;
1335 if (last_desc >= tq->size)
1336 last_desc -= tq->size;
1337 tq->sdesc[last_desc].skb = skb;
1338 tq->sdesc[last_desc].sgl = sgl;
1339 }
1340
1341 /*
1342 * Advance our internal TX Queue state, tell the hardware about
1343 * the new TX descriptors and return success.
1344 */
1345 txq_advance(&txq->q, ndesc);
1346 dev->trans_start = jiffies;
1347 ring_tx_db(adapter, &txq->q, ndesc);
1348 return NETDEV_TX_OK;
1349
1350out_free:
1351 /*
1352 * An error of some sort happened. Free the TX skb and tell the
1353 * OS that we've "dealt" with the packet ...
1354 */
1355 dev_kfree_skb(skb);
1356 return NETDEV_TX_OK;
1357}
1358
1359/**
Casey Leedomeb6c5032010-11-11 09:06:50 +00001360 * t4vf_pktgl_to_skb - build an sk_buff from a packet gather list
1361 * @gl: the gather list
1362 * @skb_len: size of sk_buff main body if it carries fragments
1363 * @pull_len: amount of data to move to the sk_buff's main body
1364 *
1365 * Builds an sk_buff from the given packet gather list. Returns the
1366 * sk_buff or %NULL if sk_buff allocation failed.
1367 */
1368struct sk_buff *t4vf_pktgl_to_skb(const struct pkt_gl *gl,
1369 unsigned int skb_len, unsigned int pull_len)
1370{
1371 struct sk_buff *skb;
1372 struct skb_shared_info *ssi;
1373
1374 /*
1375 * If the ingress packet is small enough, allocate an skb large enough
1376 * for all of the data and copy it inline. Otherwise, allocate an skb
1377 * with enough room to pull in the header and reference the rest of
1378 * the data via the skb fragment list.
1379 *
1380 * Below we rely on RX_COPY_THRES being less than the smallest Rx
1381 * buff! size, which is expected since buffers are at least
1382 * PAGE_SIZEd. In this case packets up to RX_COPY_THRES have only one
1383 * fragment.
1384 */
1385 if (gl->tot_len <= RX_COPY_THRES) {
1386 /* small packets have only one fragment */
1387 skb = alloc_skb(gl->tot_len, GFP_ATOMIC);
1388 if (unlikely(!skb))
1389 goto out;
1390 __skb_put(skb, gl->tot_len);
1391 skb_copy_to_linear_data(skb, gl->va, gl->tot_len);
1392 } else {
1393 skb = alloc_skb(skb_len, GFP_ATOMIC);
1394 if (unlikely(!skb))
1395 goto out;
1396 __skb_put(skb, pull_len);
1397 skb_copy_to_linear_data(skb, gl->va, pull_len);
1398
1399 ssi = skb_shinfo(skb);
1400 ssi->frags[0].page = gl->frags[0].page;
1401 ssi->frags[0].page_offset = gl->frags[0].page_offset + pull_len;
1402 ssi->frags[0].size = gl->frags[0].size - pull_len;
1403 if (gl->nfrags > 1)
1404 memcpy(&ssi->frags[1], &gl->frags[1],
1405 (gl->nfrags-1) * sizeof(skb_frag_t));
1406 ssi->nr_frags = gl->nfrags;
1407
1408 skb->len = gl->tot_len;
1409 skb->data_len = skb->len - pull_len;
1410 skb->truesize += skb->data_len;
1411
1412 /* Get a reference for the last page, we don't own it */
1413 get_page(gl->frags[gl->nfrags - 1].page);
1414 }
1415
1416out:
1417 return skb;
1418}
1419
1420/**
Casey Leedomc6e0d912010-06-25 12:13:28 +00001421 * t4vf_pktgl_free - free a packet gather list
1422 * @gl: the gather list
1423 *
1424 * Releases the pages of a packet gather list. We do not own the last
1425 * page on the list and do not free it.
1426 */
1427void t4vf_pktgl_free(const struct pkt_gl *gl)
1428{
1429 int frag;
1430
1431 frag = gl->nfrags - 1;
1432 while (frag--)
1433 put_page(gl->frags[frag].page);
1434}
1435
1436/**
1437 * copy_frags - copy fragments from gather list into skb_shared_info
1438 * @si: destination skb shared info structure
1439 * @gl: source internal packet gather list
1440 * @offset: packet start offset in first page
1441 *
1442 * Copy an internal packet gather list into a Linux skb_shared_info
1443 * structure.
1444 */
1445static inline void copy_frags(struct skb_shared_info *si,
1446 const struct pkt_gl *gl,
1447 unsigned int offset)
1448{
1449 unsigned int n;
1450
1451 /* usually there's just one frag */
1452 si->frags[0].page = gl->frags[0].page;
1453 si->frags[0].page_offset = gl->frags[0].page_offset + offset;
1454 si->frags[0].size = gl->frags[0].size - offset;
1455 si->nr_frags = gl->nfrags;
1456
1457 n = gl->nfrags - 1;
1458 if (n)
1459 memcpy(&si->frags[1], &gl->frags[1], n * sizeof(skb_frag_t));
1460
1461 /* get a reference to the last page, we don't own it */
1462 get_page(gl->frags[n].page);
1463}
1464
1465/**
1466 * do_gro - perform Generic Receive Offload ingress packet processing
1467 * @rxq: ingress RX Ethernet Queue
1468 * @gl: gather list for ingress packet
1469 * @pkt: CPL header for last packet fragment
1470 *
1471 * Perform Generic Receive Offload (GRO) ingress packet processing.
1472 * We use the standard Linux GRO interfaces for this.
1473 */
1474static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
1475 const struct cpl_rx_pkt *pkt)
1476{
1477 int ret;
1478 struct sk_buff *skb;
1479
1480 skb = napi_get_frags(&rxq->rspq.napi);
1481 if (unlikely(!skb)) {
1482 t4vf_pktgl_free(gl);
1483 rxq->stats.rx_drops++;
1484 return;
1485 }
1486
1487 copy_frags(skb_shinfo(skb), gl, PKTSHIFT);
1488 skb->len = gl->tot_len - PKTSHIFT;
1489 skb->data_len = skb->len;
1490 skb->truesize += skb->data_len;
1491 skb->ip_summed = CHECKSUM_UNNECESSARY;
1492 skb_record_rx_queue(skb, rxq->rspq.idx);
1493
1494 if (unlikely(pkt->vlan_ex)) {
1495 struct port_info *pi = netdev_priv(rxq->rspq.netdev);
1496 struct vlan_group *grp = pi->vlan_grp;
1497
1498 rxq->stats.vlan_ex++;
1499 if (likely(grp)) {
1500 ret = vlan_gro_frags(&rxq->rspq.napi, grp,
1501 be16_to_cpu(pkt->vlan));
1502 goto stats;
1503 }
1504 }
1505 ret = napi_gro_frags(&rxq->rspq.napi);
1506
1507stats:
1508 if (ret == GRO_HELD)
1509 rxq->stats.lro_pkts++;
1510 else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE)
1511 rxq->stats.lro_merged++;
1512 rxq->stats.pkts++;
1513 rxq->stats.rx_cso++;
1514}
1515
1516/**
1517 * t4vf_ethrx_handler - process an ingress ethernet packet
1518 * @rspq: the response queue that received the packet
1519 * @rsp: the response queue descriptor holding the RX_PKT message
1520 * @gl: the gather list of packet fragments
1521 *
1522 * Process an ingress ethernet packet and deliver it to the stack.
1523 */
1524int t4vf_ethrx_handler(struct sge_rspq *rspq, const __be64 *rsp,
1525 const struct pkt_gl *gl)
1526{
1527 struct sk_buff *skb;
1528 struct port_info *pi;
Casey Leedomc6e0d912010-06-25 12:13:28 +00001529 const struct cpl_rx_pkt *pkt = (void *)&rsp[1];
1530 bool csum_ok = pkt->csum_calc && !pkt->err_vec;
Casey Leedomc6e0d912010-06-25 12:13:28 +00001531 struct sge_eth_rxq *rxq = container_of(rspq, struct sge_eth_rxq, rspq);
1532
1533 /*
1534 * If this is a good TCP packet and we have Generic Receive Offload
1535 * enabled, handle the packet in the GRO path.
1536 */
1537 if ((pkt->l2info & cpu_to_be32(RXF_TCP)) &&
1538 (rspq->netdev->features & NETIF_F_GRO) && csum_ok &&
1539 !pkt->ip_frag) {
1540 do_gro(rxq, gl, pkt);
1541 return 0;
1542 }
1543
1544 /*
Casey Leedomeb6c5032010-11-11 09:06:50 +00001545 * Convert the Packet Gather List into an skb.
Casey Leedomc6e0d912010-06-25 12:13:28 +00001546 */
Casey Leedomeb6c5032010-11-11 09:06:50 +00001547 skb = t4vf_pktgl_to_skb(gl, RX_SKB_LEN, RX_PULL_LEN);
1548 if (unlikely(!skb)) {
1549 t4vf_pktgl_free(gl);
1550 rxq->stats.rx_drops++;
1551 return 0;
Casey Leedomc6e0d912010-06-25 12:13:28 +00001552 }
Casey Leedomc6e0d912010-06-25 12:13:28 +00001553 __skb_pull(skb, PKTSHIFT);
1554 skb->protocol = eth_type_trans(skb, rspq->netdev);
1555 skb_record_rx_queue(skb, rspq->idx);
Casey Leedomc6e0d912010-06-25 12:13:28 +00001556 pi = netdev_priv(skb->dev);
1557 rxq->stats.pkts++;
1558
Michał Mirosław2ed28ba2011-04-16 13:05:08 +00001559 if (csum_ok && (rspq->netdev->features & NETIF_F_RXCSUM) &&
1560 !pkt->err_vec && (be32_to_cpu(pkt->l2info) & (RXF_UDP|RXF_TCP))) {
Casey Leedomc6e0d912010-06-25 12:13:28 +00001561 if (!pkt->ip_frag)
1562 skb->ip_summed = CHECKSUM_UNNECESSARY;
1563 else {
1564 __sum16 c = (__force __sum16)pkt->csum;
1565 skb->csum = csum_unfold(c);
1566 skb->ip_summed = CHECKSUM_COMPLETE;
1567 }
1568 rxq->stats.rx_cso++;
1569 } else
Eric Dumazetbc8acf22010-09-02 13:07:41 -07001570 skb_checksum_none_assert(skb);
Casey Leedomc6e0d912010-06-25 12:13:28 +00001571
Casey Leedomcaedda32010-11-11 09:30:40 +00001572 /*
1573 * Deliver the packet to the stack.
1574 */
Casey Leedomc6e0d912010-06-25 12:13:28 +00001575 if (unlikely(pkt->vlan_ex)) {
1576 struct vlan_group *grp = pi->vlan_grp;
1577
1578 rxq->stats.vlan_ex++;
1579 if (likely(grp))
1580 vlan_hwaccel_receive_skb(skb, grp,
1581 be16_to_cpu(pkt->vlan));
1582 else
1583 dev_kfree_skb_any(skb);
1584 } else
1585 netif_receive_skb(skb);
1586
1587 return 0;
Casey Leedomc6e0d912010-06-25 12:13:28 +00001588}
1589
1590/**
1591 * is_new_response - check if a response is newly written
1592 * @rc: the response control descriptor
1593 * @rspq: the response queue
1594 *
1595 * Returns true if a response descriptor contains a yet unprocessed
1596 * response.
1597 */
1598static inline bool is_new_response(const struct rsp_ctrl *rc,
1599 const struct sge_rspq *rspq)
1600{
1601 return RSPD_GEN(rc->type_gen) == rspq->gen;
1602}
1603
1604/**
1605 * restore_rx_bufs - put back a packet's RX buffers
1606 * @gl: the packet gather list
1607 * @fl: the SGE Free List
1608 * @nfrags: how many fragments in @si
1609 *
1610 * Called when we find out that the current packet, @si, can't be
1611 * processed right away for some reason. This is a very rare event and
1612 * there's no effort to make this suspension/resumption process
1613 * particularly efficient.
1614 *
1615 * We implement the suspension by putting all of the RX buffers associated
1616 * with the current packet back on the original Free List. The buffers
1617 * have already been unmapped and are left unmapped, we mark them as
1618 * unmapped in order to prevent further unmapping attempts. (Effectively
1619 * this function undoes the series of @unmap_rx_buf calls which were done
1620 * to create the current packet's gather list.) This leaves us ready to
1621 * restart processing of the packet the next time we start processing the
1622 * RX Queue ...
1623 */
1624static void restore_rx_bufs(const struct pkt_gl *gl, struct sge_fl *fl,
1625 int frags)
1626{
1627 struct rx_sw_desc *sdesc;
1628
1629 while (frags--) {
1630 if (fl->cidx == 0)
1631 fl->cidx = fl->size - 1;
1632 else
1633 fl->cidx--;
1634 sdesc = &fl->sdesc[fl->cidx];
1635 sdesc->page = gl->frags[frags].page;
1636 sdesc->dma_addr |= RX_UNMAPPED_BUF;
1637 fl->avail++;
1638 }
1639}
1640
1641/**
1642 * rspq_next - advance to the next entry in a response queue
1643 * @rspq: the queue
1644 *
1645 * Updates the state of a response queue to advance it to the next entry.
1646 */
1647static inline void rspq_next(struct sge_rspq *rspq)
1648{
1649 rspq->cur_desc = (void *)rspq->cur_desc + rspq->iqe_len;
1650 if (unlikely(++rspq->cidx == rspq->size)) {
1651 rspq->cidx = 0;
1652 rspq->gen ^= 1;
1653 rspq->cur_desc = rspq->desc;
1654 }
1655}
1656
1657/**
1658 * process_responses - process responses from an SGE response queue
1659 * @rspq: the ingress response queue to process
1660 * @budget: how many responses can be processed in this round
1661 *
1662 * Process responses from a Scatter Gather Engine response queue up to
1663 * the supplied budget. Responses include received packets as well as
1664 * control messages from firmware or hardware.
1665 *
1666 * Additionally choose the interrupt holdoff time for the next interrupt
1667 * on this queue. If the system is under memory shortage use a fairly
1668 * long delay to help recovery.
1669 */
1670int process_responses(struct sge_rspq *rspq, int budget)
1671{
1672 struct sge_eth_rxq *rxq = container_of(rspq, struct sge_eth_rxq, rspq);
1673 int budget_left = budget;
1674
1675 while (likely(budget_left)) {
1676 int ret, rsp_type;
1677 const struct rsp_ctrl *rc;
1678
1679 rc = (void *)rspq->cur_desc + (rspq->iqe_len - sizeof(*rc));
1680 if (!is_new_response(rc, rspq))
1681 break;
1682
1683 /*
1684 * Figure out what kind of response we've received from the
1685 * SGE.
1686 */
1687 rmb();
1688 rsp_type = RSPD_TYPE(rc->type_gen);
1689 if (likely(rsp_type == RSP_TYPE_FLBUF)) {
1690 skb_frag_t *fp;
1691 struct pkt_gl gl;
1692 const struct rx_sw_desc *sdesc;
1693 u32 bufsz, frag;
1694 u32 len = be32_to_cpu(rc->pldbuflen_qid);
1695
1696 /*
1697 * If we get a "new buffer" message from the SGE we
1698 * need to move on to the next Free List buffer.
1699 */
1700 if (len & RSPD_NEWBUF) {
1701 /*
1702 * We get one "new buffer" message when we
1703 * first start up a queue so we need to ignore
1704 * it when our offset into the buffer is 0.
1705 */
1706 if (likely(rspq->offset > 0)) {
1707 free_rx_bufs(rspq->adapter, &rxq->fl,
1708 1);
1709 rspq->offset = 0;
1710 }
1711 len = RSPD_LEN(len);
1712 }
Casey Leedomb94e72e2010-11-11 09:06:49 +00001713 gl.tot_len = len;
Casey Leedomc6e0d912010-06-25 12:13:28 +00001714
1715 /*
1716 * Gather packet fragments.
1717 */
1718 for (frag = 0, fp = gl.frags; /**/; frag++, fp++) {
1719 BUG_ON(frag >= MAX_SKB_FRAGS);
1720 BUG_ON(rxq->fl.avail == 0);
1721 sdesc = &rxq->fl.sdesc[rxq->fl.cidx];
1722 bufsz = get_buf_size(sdesc);
1723 fp->page = sdesc->page;
1724 fp->page_offset = rspq->offset;
1725 fp->size = min(bufsz, len);
1726 len -= fp->size;
1727 if (!len)
1728 break;
1729 unmap_rx_buf(rspq->adapter, &rxq->fl);
1730 }
1731 gl.nfrags = frag+1;
1732
1733 /*
1734 * Last buffer remains mapped so explicitly make it
1735 * coherent for CPU access and start preloading first
1736 * cache line ...
1737 */
1738 dma_sync_single_for_cpu(rspq->adapter->pdev_dev,
1739 get_buf_addr(sdesc),
1740 fp->size, DMA_FROM_DEVICE);
1741 gl.va = (page_address(gl.frags[0].page) +
1742 gl.frags[0].page_offset);
1743 prefetch(gl.va);
1744
1745 /*
1746 * Hand the new ingress packet to the handler for
1747 * this Response Queue.
1748 */
1749 ret = rspq->handler(rspq, rspq->cur_desc, &gl);
1750 if (likely(ret == 0))
1751 rspq->offset += ALIGN(fp->size, FL_ALIGN);
1752 else
1753 restore_rx_bufs(&gl, &rxq->fl, frag);
1754 } else if (likely(rsp_type == RSP_TYPE_CPL)) {
1755 ret = rspq->handler(rspq, rspq->cur_desc, NULL);
1756 } else {
1757 WARN_ON(rsp_type > RSP_TYPE_CPL);
1758 ret = 0;
1759 }
1760
1761 if (unlikely(ret)) {
1762 /*
1763 * Couldn't process descriptor, back off for recovery.
1764 * We use the SGE's last timer which has the longest
1765 * interrupt coalescing value ...
1766 */
1767 const int NOMEM_TIMER_IDX = SGE_NTIMERS-1;
1768 rspq->next_intr_params =
1769 QINTR_TIMER_IDX(NOMEM_TIMER_IDX);
1770 break;
1771 }
1772
1773 rspq_next(rspq);
1774 budget_left--;
1775 }
1776
1777 /*
1778 * If this is a Response Queue with an associated Free List and
1779 * at least two Egress Queue units available in the Free List
1780 * for new buffer pointers, refill the Free List.
1781 */
1782 if (rspq->offset >= 0 &&
1783 rxq->fl.size - rxq->fl.avail >= 2*FL_PER_EQ_UNIT)
1784 __refill_fl(rspq->adapter, &rxq->fl);
1785 return budget - budget_left;
1786}
1787
1788/**
1789 * napi_rx_handler - the NAPI handler for RX processing
1790 * @napi: the napi instance
1791 * @budget: how many packets we can process in this round
1792 *
1793 * Handler for new data events when using NAPI. This does not need any
1794 * locking or protection from interrupts as data interrupts are off at
1795 * this point and other adapter interrupts do not interfere (the latter
1796 * in not a concern at all with MSI-X as non-data interrupts then have
1797 * a separate handler).
1798 */
1799static int napi_rx_handler(struct napi_struct *napi, int budget)
1800{
1801 unsigned int intr_params;
1802 struct sge_rspq *rspq = container_of(napi, struct sge_rspq, napi);
1803 int work_done = process_responses(rspq, budget);
1804
1805 if (likely(work_done < budget)) {
1806 napi_complete(napi);
1807 intr_params = rspq->next_intr_params;
1808 rspq->next_intr_params = rspq->intr_params;
1809 } else
1810 intr_params = QINTR_TIMER_IDX(SGE_TIMER_UPD_CIDX);
1811
Casey Leedom68dc9d32010-07-08 10:05:48 -07001812 if (unlikely(work_done == 0))
1813 rspq->unhandled_irqs++;
1814
Casey Leedomc6e0d912010-06-25 12:13:28 +00001815 t4_write_reg(rspq->adapter,
1816 T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
1817 CIDXINC(work_done) |
1818 INGRESSQID((u32)rspq->cntxt_id) |
1819 SEINTARM(intr_params));
1820 return work_done;
1821}
1822
1823/*
1824 * The MSI-X interrupt handler for an SGE response queue for the NAPI case
1825 * (i.e., response queue serviced by NAPI polling).
1826 */
1827irqreturn_t t4vf_sge_intr_msix(int irq, void *cookie)
1828{
1829 struct sge_rspq *rspq = cookie;
1830
1831 napi_schedule(&rspq->napi);
1832 return IRQ_HANDLED;
1833}
1834
1835/*
1836 * Process the indirect interrupt entries in the interrupt queue and kick off
1837 * NAPI for each queue that has generated an entry.
1838 */
1839static unsigned int process_intrq(struct adapter *adapter)
1840{
1841 struct sge *s = &adapter->sge;
1842 struct sge_rspq *intrq = &s->intrq;
1843 unsigned int work_done;
1844
1845 spin_lock(&adapter->sge.intrq_lock);
1846 for (work_done = 0; ; work_done++) {
1847 const struct rsp_ctrl *rc;
1848 unsigned int qid, iq_idx;
1849 struct sge_rspq *rspq;
1850
1851 /*
1852 * Grab the next response from the interrupt queue and bail
1853 * out if it's not a new response.
1854 */
1855 rc = (void *)intrq->cur_desc + (intrq->iqe_len - sizeof(*rc));
1856 if (!is_new_response(rc, intrq))
1857 break;
1858
1859 /*
1860 * If the response isn't a forwarded interrupt message issue a
1861 * error and go on to the next response message. This should
1862 * never happen ...
1863 */
1864 rmb();
1865 if (unlikely(RSPD_TYPE(rc->type_gen) != RSP_TYPE_INTR)) {
1866 dev_err(adapter->pdev_dev,
1867 "Unexpected INTRQ response type %d\n",
1868 RSPD_TYPE(rc->type_gen));
1869 continue;
1870 }
1871
1872 /*
1873 * Extract the Queue ID from the interrupt message and perform
1874 * sanity checking to make sure it really refers to one of our
1875 * Ingress Queues which is active and matches the queue's ID.
1876 * None of these error conditions should ever happen so we may
1877 * want to either make them fatal and/or conditionalized under
1878 * DEBUG.
1879 */
1880 qid = RSPD_QID(be32_to_cpu(rc->pldbuflen_qid));
1881 iq_idx = IQ_IDX(s, qid);
1882 if (unlikely(iq_idx >= MAX_INGQ)) {
1883 dev_err(adapter->pdev_dev,
1884 "Ingress QID %d out of range\n", qid);
1885 continue;
1886 }
1887 rspq = s->ingr_map[iq_idx];
1888 if (unlikely(rspq == NULL)) {
1889 dev_err(adapter->pdev_dev,
1890 "Ingress QID %d RSPQ=NULL\n", qid);
1891 continue;
1892 }
1893 if (unlikely(rspq->abs_id != qid)) {
1894 dev_err(adapter->pdev_dev,
1895 "Ingress QID %d refers to RSPQ %d\n",
1896 qid, rspq->abs_id);
1897 continue;
1898 }
1899
1900 /*
1901 * Schedule NAPI processing on the indicated Response Queue
1902 * and move on to the next entry in the Forwarded Interrupt
1903 * Queue.
1904 */
1905 napi_schedule(&rspq->napi);
1906 rspq_next(intrq);
1907 }
1908
1909 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
1910 CIDXINC(work_done) |
1911 INGRESSQID(intrq->cntxt_id) |
1912 SEINTARM(intrq->intr_params));
1913
1914 spin_unlock(&adapter->sge.intrq_lock);
1915
1916 return work_done;
1917}
1918
1919/*
1920 * The MSI interrupt handler handles data events from SGE response queues as
1921 * well as error and other async events as they all use the same MSI vector.
1922 */
1923irqreturn_t t4vf_intr_msi(int irq, void *cookie)
1924{
1925 struct adapter *adapter = cookie;
1926
1927 process_intrq(adapter);
1928 return IRQ_HANDLED;
1929}
1930
1931/**
1932 * t4vf_intr_handler - select the top-level interrupt handler
1933 * @adapter: the adapter
1934 *
1935 * Selects the top-level interrupt handler based on the type of interrupts
1936 * (MSI-X or MSI).
1937 */
1938irq_handler_t t4vf_intr_handler(struct adapter *adapter)
1939{
1940 BUG_ON((adapter->flags & (USING_MSIX|USING_MSI)) == 0);
1941 if (adapter->flags & USING_MSIX)
1942 return t4vf_sge_intr_msix;
1943 else
1944 return t4vf_intr_msi;
1945}
1946
1947/**
1948 * sge_rx_timer_cb - perform periodic maintenance of SGE RX queues
1949 * @data: the adapter
1950 *
1951 * Runs periodically from a timer to perform maintenance of SGE RX queues.
1952 *
1953 * a) Replenishes RX queues that have run out due to memory shortage.
1954 * Normally new RX buffers are added when existing ones are consumed but
1955 * when out of memory a queue can become empty. We schedule NAPI to do
1956 * the actual refill.
1957 */
1958static void sge_rx_timer_cb(unsigned long data)
1959{
1960 struct adapter *adapter = (struct adapter *)data;
1961 struct sge *s = &adapter->sge;
1962 unsigned int i;
1963
1964 /*
1965 * Scan the "Starving Free Lists" flag array looking for any Free
1966 * Lists in need of more free buffers. If we find one and it's not
1967 * being actively polled, then bump its "starving" counter and attempt
1968 * to refill it. If we're successful in adding enough buffers to push
1969 * the Free List over the starving threshold, then we can clear its
1970 * "starving" status.
1971 */
1972 for (i = 0; i < ARRAY_SIZE(s->starving_fl); i++) {
1973 unsigned long m;
1974
1975 for (m = s->starving_fl[i]; m; m &= m - 1) {
1976 unsigned int id = __ffs(m) + i * BITS_PER_LONG;
1977 struct sge_fl *fl = s->egr_map[id];
1978
1979 clear_bit(id, s->starving_fl);
1980 smp_mb__after_clear_bit();
1981
1982 /*
1983 * Since we are accessing fl without a lock there's a
1984 * small probability of a false positive where we
1985 * schedule napi but the FL is no longer starving.
1986 * No biggie.
1987 */
1988 if (fl_starving(fl)) {
1989 struct sge_eth_rxq *rxq;
1990
1991 rxq = container_of(fl, struct sge_eth_rxq, fl);
1992 if (napi_reschedule(&rxq->rspq.napi))
1993 fl->starving++;
1994 else
1995 set_bit(id, s->starving_fl);
1996 }
1997 }
1998 }
1999
2000 /*
2001 * Reschedule the next scan for starving Free Lists ...
2002 */
2003 mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
2004}
2005
2006/**
2007 * sge_tx_timer_cb - perform periodic maintenance of SGE Tx queues
2008 * @data: the adapter
2009 *
2010 * Runs periodically from a timer to perform maintenance of SGE TX queues.
2011 *
2012 * b) Reclaims completed Tx packets for the Ethernet queues. Normally
2013 * packets are cleaned up by new Tx packets, this timer cleans up packets
2014 * when no new packets are being submitted. This is essential for pktgen,
2015 * at least.
2016 */
2017static void sge_tx_timer_cb(unsigned long data)
2018{
2019 struct adapter *adapter = (struct adapter *)data;
2020 struct sge *s = &adapter->sge;
2021 unsigned int i, budget;
2022
2023 budget = MAX_TIMER_TX_RECLAIM;
2024 i = s->ethtxq_rover;
2025 do {
2026 struct sge_eth_txq *txq = &s->ethtxq[i];
2027
2028 if (reclaimable(&txq->q) && __netif_tx_trylock(txq->txq)) {
2029 int avail = reclaimable(&txq->q);
2030
2031 if (avail > budget)
2032 avail = budget;
2033
2034 free_tx_desc(adapter, &txq->q, avail, true);
2035 txq->q.in_use -= avail;
2036 __netif_tx_unlock(txq->txq);
2037
2038 budget -= avail;
2039 if (!budget)
2040 break;
2041 }
2042
2043 i++;
2044 if (i >= s->ethqsets)
2045 i = 0;
2046 } while (i != s->ethtxq_rover);
2047 s->ethtxq_rover = i;
2048
2049 /*
2050 * If we found too many reclaimable packets schedule a timer in the
2051 * near future to continue where we left off. Otherwise the next timer
2052 * will be at its normal interval.
2053 */
2054 mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2));
2055}
2056
2057/**
2058 * t4vf_sge_alloc_rxq - allocate an SGE RX Queue
2059 * @adapter: the adapter
2060 * @rspq: pointer to to the new rxq's Response Queue to be filled in
2061 * @iqasynch: if 0, a normal rspq; if 1, an asynchronous event queue
2062 * @dev: the network device associated with the new rspq
2063 * @intr_dest: MSI-X vector index (overriden in MSI mode)
2064 * @fl: pointer to the new rxq's Free List to be filled in
2065 * @hnd: the interrupt handler to invoke for the rspq
2066 */
2067int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
2068 bool iqasynch, struct net_device *dev,
2069 int intr_dest,
2070 struct sge_fl *fl, rspq_handler_t hnd)
2071{
2072 struct port_info *pi = netdev_priv(dev);
2073 struct fw_iq_cmd cmd, rpl;
2074 int ret, iqandst, flsz = 0;
2075
2076 /*
2077 * If we're using MSI interrupts and we're not initializing the
2078 * Forwarded Interrupt Queue itself, then set up this queue for
2079 * indirect interrupts to the Forwarded Interrupt Queue. Obviously
2080 * the Forwarded Interrupt Queue must be set up before any other
2081 * ingress queue ...
2082 */
2083 if ((adapter->flags & USING_MSI) && rspq != &adapter->sge.intrq) {
2084 iqandst = SGE_INTRDST_IQ;
2085 intr_dest = adapter->sge.intrq.abs_id;
2086 } else
2087 iqandst = SGE_INTRDST_PCI;
2088
2089 /*
2090 * Allocate the hardware ring for the Response Queue. The size needs
2091 * to be a multiple of 16 which includes the mandatory status entry
2092 * (regardless of whether the Status Page capabilities are enabled or
2093 * not).
2094 */
2095 rspq->size = roundup(rspq->size, 16);
2096 rspq->desc = alloc_ring(adapter->pdev_dev, rspq->size, rspq->iqe_len,
2097 0, &rspq->phys_addr, NULL, 0);
2098 if (!rspq->desc)
2099 return -ENOMEM;
2100
2101 /*
2102 * Fill in the Ingress Queue Command. Note: Ideally this code would
2103 * be in t4vf_hw.c but there are so many parameters and dependencies
2104 * on our Linux SGE state that we would end up having to pass tons of
2105 * parameters. We'll have to think about how this might be migrated
2106 * into OS-independent common code ...
2107 */
2108 memset(&cmd, 0, sizeof(cmd));
2109 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_IQ_CMD) |
2110 FW_CMD_REQUEST |
2111 FW_CMD_WRITE |
2112 FW_CMD_EXEC);
2113 cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_ALLOC |
2114 FW_IQ_CMD_IQSTART(1) |
2115 FW_LEN16(cmd));
2116 cmd.type_to_iqandstindex =
2117 cpu_to_be32(FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2118 FW_IQ_CMD_IQASYNCH(iqasynch) |
2119 FW_IQ_CMD_VIID(pi->viid) |
2120 FW_IQ_CMD_IQANDST(iqandst) |
2121 FW_IQ_CMD_IQANUS(1) |
2122 FW_IQ_CMD_IQANUD(SGE_UPDATEDEL_INTR) |
2123 FW_IQ_CMD_IQANDSTINDEX(intr_dest));
2124 cmd.iqdroprss_to_iqesize =
2125 cpu_to_be16(FW_IQ_CMD_IQPCIECH(pi->port_id) |
2126 FW_IQ_CMD_IQGTSMODE |
2127 FW_IQ_CMD_IQINTCNTTHRESH(rspq->pktcnt_idx) |
2128 FW_IQ_CMD_IQESIZE(ilog2(rspq->iqe_len) - 4));
2129 cmd.iqsize = cpu_to_be16(rspq->size);
2130 cmd.iqaddr = cpu_to_be64(rspq->phys_addr);
2131
2132 if (fl) {
2133 /*
2134 * Allocate the ring for the hardware free list (with space
2135 * for its status page) along with the associated software
2136 * descriptor ring. The free list size needs to be a multiple
2137 * of the Egress Queue Unit.
2138 */
2139 fl->size = roundup(fl->size, FL_PER_EQ_UNIT);
2140 fl->desc = alloc_ring(adapter->pdev_dev, fl->size,
2141 sizeof(__be64), sizeof(struct rx_sw_desc),
2142 &fl->addr, &fl->sdesc, STAT_LEN);
2143 if (!fl->desc) {
2144 ret = -ENOMEM;
2145 goto err;
2146 }
2147
2148 /*
2149 * Calculate the size of the hardware free list ring plus
Casey Leedomcaedda32010-11-11 09:30:40 +00002150 * Status Page (which the SGE will place after the end of the
Casey Leedomc6e0d912010-06-25 12:13:28 +00002151 * free list ring) in Egress Queue Units.
2152 */
2153 flsz = (fl->size / FL_PER_EQ_UNIT +
2154 STAT_LEN / EQ_UNIT);
2155
2156 /*
2157 * Fill in all the relevant firmware Ingress Queue Command
2158 * fields for the free list.
2159 */
2160 cmd.iqns_to_fl0congen =
2161 cpu_to_be32(
2162 FW_IQ_CMD_FL0HOSTFCMODE(SGE_HOSTFCMODE_NONE) |
2163 FW_IQ_CMD_FL0PACKEN |
2164 FW_IQ_CMD_FL0PADEN);
2165 cmd.fl0dcaen_to_fl0cidxfthresh =
2166 cpu_to_be16(
2167 FW_IQ_CMD_FL0FBMIN(SGE_FETCHBURSTMIN_64B) |
2168 FW_IQ_CMD_FL0FBMAX(SGE_FETCHBURSTMAX_512B));
2169 cmd.fl0size = cpu_to_be16(flsz);
2170 cmd.fl0addr = cpu_to_be64(fl->addr);
2171 }
2172
2173 /*
2174 * Issue the firmware Ingress Queue Command and extract the results if
2175 * it completes successfully.
2176 */
2177 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
2178 if (ret)
2179 goto err;
2180
2181 netif_napi_add(dev, &rspq->napi, napi_rx_handler, 64);
2182 rspq->cur_desc = rspq->desc;
2183 rspq->cidx = 0;
2184 rspq->gen = 1;
2185 rspq->next_intr_params = rspq->intr_params;
2186 rspq->cntxt_id = be16_to_cpu(rpl.iqid);
2187 rspq->abs_id = be16_to_cpu(rpl.physiqid);
2188 rspq->size--; /* subtract status entry */
2189 rspq->adapter = adapter;
2190 rspq->netdev = dev;
2191 rspq->handler = hnd;
2192
2193 /* set offset to -1 to distinguish ingress queues without FL */
2194 rspq->offset = fl ? 0 : -1;
2195
2196 if (fl) {
2197 fl->cntxt_id = be16_to_cpu(rpl.fl0id);
2198 fl->avail = 0;
2199 fl->pend_cred = 0;
2200 fl->pidx = 0;
2201 fl->cidx = 0;
2202 fl->alloc_failed = 0;
2203 fl->large_alloc_failed = 0;
2204 fl->starving = 0;
2205 refill_fl(adapter, fl, fl_cap(fl), GFP_KERNEL);
2206 }
2207
2208 return 0;
2209
2210err:
2211 /*
2212 * An error occurred. Clean up our partial allocation state and
2213 * return the error.
2214 */
2215 if (rspq->desc) {
2216 dma_free_coherent(adapter->pdev_dev, rspq->size * rspq->iqe_len,
2217 rspq->desc, rspq->phys_addr);
2218 rspq->desc = NULL;
2219 }
2220 if (fl && fl->desc) {
2221 kfree(fl->sdesc);
2222 fl->sdesc = NULL;
2223 dma_free_coherent(adapter->pdev_dev, flsz * EQ_UNIT,
2224 fl->desc, fl->addr);
2225 fl->desc = NULL;
2226 }
2227 return ret;
2228}
2229
2230/**
2231 * t4vf_sge_alloc_eth_txq - allocate an SGE Ethernet TX Queue
2232 * @adapter: the adapter
2233 * @txq: pointer to the new txq to be filled in
2234 * @devq: the network TX queue associated with the new txq
2235 * @iqid: the relative ingress queue ID to which events relating to
2236 * the new txq should be directed
2237 */
2238int t4vf_sge_alloc_eth_txq(struct adapter *adapter, struct sge_eth_txq *txq,
2239 struct net_device *dev, struct netdev_queue *devq,
2240 unsigned int iqid)
2241{
2242 int ret, nentries;
2243 struct fw_eq_eth_cmd cmd, rpl;
2244 struct port_info *pi = netdev_priv(dev);
2245
2246 /*
Casey Leedomcaedda32010-11-11 09:30:40 +00002247 * Calculate the size of the hardware TX Queue (including the Status
2248 * Page on the end of the TX Queue) in units of TX Descriptors.
Casey Leedomc6e0d912010-06-25 12:13:28 +00002249 */
2250 nentries = txq->q.size + STAT_LEN / sizeof(struct tx_desc);
2251
2252 /*
2253 * Allocate the hardware ring for the TX ring (with space for its
2254 * status page) along with the associated software descriptor ring.
2255 */
2256 txq->q.desc = alloc_ring(adapter->pdev_dev, txq->q.size,
2257 sizeof(struct tx_desc),
2258 sizeof(struct tx_sw_desc),
2259 &txq->q.phys_addr, &txq->q.sdesc, STAT_LEN);
2260 if (!txq->q.desc)
2261 return -ENOMEM;
2262
2263 /*
2264 * Fill in the Egress Queue Command. Note: As with the direct use of
2265 * the firmware Ingress Queue COmmand above in our RXQ allocation
2266 * routine, ideally, this code would be in t4vf_hw.c. Again, we'll
2267 * have to see if there's some reasonable way to parameterize it
2268 * into the common code ...
2269 */
2270 memset(&cmd, 0, sizeof(cmd));
2271 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_EQ_ETH_CMD) |
2272 FW_CMD_REQUEST |
2273 FW_CMD_WRITE |
2274 FW_CMD_EXEC);
2275 cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_ALLOC |
2276 FW_EQ_ETH_CMD_EQSTART |
2277 FW_LEN16(cmd));
2278 cmd.viid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_VIID(pi->viid));
2279 cmd.fetchszm_to_iqid =
2280 cpu_to_be32(FW_EQ_ETH_CMD_HOSTFCMODE(SGE_HOSTFCMODE_STPG) |
2281 FW_EQ_ETH_CMD_PCIECHN(pi->port_id) |
2282 FW_EQ_ETH_CMD_IQID(iqid));
2283 cmd.dcaen_to_eqsize =
2284 cpu_to_be32(FW_EQ_ETH_CMD_FBMIN(SGE_FETCHBURSTMIN_64B) |
2285 FW_EQ_ETH_CMD_FBMAX(SGE_FETCHBURSTMAX_512B) |
2286 FW_EQ_ETH_CMD_CIDXFTHRESH(SGE_CIDXFLUSHTHRESH_32) |
2287 FW_EQ_ETH_CMD_EQSIZE(nentries));
2288 cmd.eqaddr = cpu_to_be64(txq->q.phys_addr);
2289
2290 /*
2291 * Issue the firmware Egress Queue Command and extract the results if
2292 * it completes successfully.
2293 */
2294 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
2295 if (ret) {
2296 /*
2297 * The girmware Ingress Queue Command failed for some reason.
2298 * Free up our partial allocation state and return the error.
2299 */
2300 kfree(txq->q.sdesc);
2301 txq->q.sdesc = NULL;
2302 dma_free_coherent(adapter->pdev_dev,
2303 nentries * sizeof(struct tx_desc),
2304 txq->q.desc, txq->q.phys_addr);
2305 txq->q.desc = NULL;
2306 return ret;
2307 }
2308
2309 txq->q.in_use = 0;
2310 txq->q.cidx = 0;
2311 txq->q.pidx = 0;
2312 txq->q.stat = (void *)&txq->q.desc[txq->q.size];
2313 txq->q.cntxt_id = FW_EQ_ETH_CMD_EQID_GET(be32_to_cpu(rpl.eqid_pkd));
2314 txq->q.abs_id =
2315 FW_EQ_ETH_CMD_PHYSEQID_GET(be32_to_cpu(rpl.physeqid_pkd));
2316 txq->txq = devq;
2317 txq->tso = 0;
2318 txq->tx_cso = 0;
2319 txq->vlan_ins = 0;
2320 txq->q.stops = 0;
2321 txq->q.restarts = 0;
2322 txq->mapping_err = 0;
2323 return 0;
2324}
2325
2326/*
2327 * Free the DMA map resources associated with a TX queue.
2328 */
2329static void free_txq(struct adapter *adapter, struct sge_txq *tq)
2330{
2331 dma_free_coherent(adapter->pdev_dev,
2332 tq->size * sizeof(*tq->desc) + STAT_LEN,
2333 tq->desc, tq->phys_addr);
2334 tq->cntxt_id = 0;
2335 tq->sdesc = NULL;
2336 tq->desc = NULL;
2337}
2338
2339/*
2340 * Free the resources associated with a response queue (possibly including a
2341 * free list).
2342 */
2343static void free_rspq_fl(struct adapter *adapter, struct sge_rspq *rspq,
2344 struct sge_fl *fl)
2345{
2346 unsigned int flid = fl ? fl->cntxt_id : 0xffff;
2347
2348 t4vf_iq_free(adapter, FW_IQ_TYPE_FL_INT_CAP,
2349 rspq->cntxt_id, flid, 0xffff);
2350 dma_free_coherent(adapter->pdev_dev, (rspq->size + 1) * rspq->iqe_len,
2351 rspq->desc, rspq->phys_addr);
2352 netif_napi_del(&rspq->napi);
2353 rspq->netdev = NULL;
2354 rspq->cntxt_id = 0;
2355 rspq->abs_id = 0;
2356 rspq->desc = NULL;
2357
2358 if (fl) {
2359 free_rx_bufs(adapter, fl, fl->avail);
2360 dma_free_coherent(adapter->pdev_dev,
2361 fl->size * sizeof(*fl->desc) + STAT_LEN,
2362 fl->desc, fl->addr);
2363 kfree(fl->sdesc);
2364 fl->sdesc = NULL;
2365 fl->cntxt_id = 0;
2366 fl->desc = NULL;
2367 }
2368}
2369
2370/**
2371 * t4vf_free_sge_resources - free SGE resources
2372 * @adapter: the adapter
2373 *
2374 * Frees resources used by the SGE queue sets.
2375 */
2376void t4vf_free_sge_resources(struct adapter *adapter)
2377{
2378 struct sge *s = &adapter->sge;
2379 struct sge_eth_rxq *rxq = s->ethrxq;
2380 struct sge_eth_txq *txq = s->ethtxq;
2381 struct sge_rspq *evtq = &s->fw_evtq;
2382 struct sge_rspq *intrq = &s->intrq;
2383 int qs;
2384
Casey Leedomb97d13a2010-07-15 22:47:06 -07002385 for (qs = 0; qs < adapter->sge.ethqsets; qs++, rxq++, txq++) {
Casey Leedomc6e0d912010-06-25 12:13:28 +00002386 if (rxq->rspq.desc)
2387 free_rspq_fl(adapter, &rxq->rspq, &rxq->fl);
2388 if (txq->q.desc) {
2389 t4vf_eth_eq_free(adapter, txq->q.cntxt_id);
2390 free_tx_desc(adapter, &txq->q, txq->q.in_use, true);
2391 kfree(txq->q.sdesc);
2392 free_txq(adapter, &txq->q);
2393 }
2394 }
2395 if (evtq->desc)
2396 free_rspq_fl(adapter, evtq, NULL);
2397 if (intrq->desc)
2398 free_rspq_fl(adapter, intrq, NULL);
2399}
2400
2401/**
2402 * t4vf_sge_start - enable SGE operation
2403 * @adapter: the adapter
2404 *
2405 * Start tasklets and timers associated with the DMA engine.
2406 */
2407void t4vf_sge_start(struct adapter *adapter)
2408{
2409 adapter->sge.ethtxq_rover = 0;
2410 mod_timer(&adapter->sge.rx_timer, jiffies + RX_QCHECK_PERIOD);
2411 mod_timer(&adapter->sge.tx_timer, jiffies + TX_QCHECK_PERIOD);
2412}
2413
2414/**
2415 * t4vf_sge_stop - disable SGE operation
2416 * @adapter: the adapter
2417 *
2418 * Stop tasklets and timers associated with the DMA engine. Note that
2419 * this is effective only if measures have been taken to disable any HW
2420 * events that may restart them.
2421 */
2422void t4vf_sge_stop(struct adapter *adapter)
2423{
2424 struct sge *s = &adapter->sge;
2425
2426 if (s->rx_timer.function)
2427 del_timer_sync(&s->rx_timer);
2428 if (s->tx_timer.function)
2429 del_timer_sync(&s->tx_timer);
2430}
2431
2432/**
2433 * t4vf_sge_init - initialize SGE
2434 * @adapter: the adapter
2435 *
2436 * Performs SGE initialization needed every time after a chip reset.
2437 * We do not initialize any of the queue sets here, instead the driver
2438 * top-level must request those individually. We also do not enable DMA
2439 * here, that should be done after the queues have been set up.
2440 */
2441int t4vf_sge_init(struct adapter *adapter)
2442{
2443 struct sge_params *sge_params = &adapter->params.sge;
2444 u32 fl0 = sge_params->sge_fl_buffer_size[0];
2445 u32 fl1 = sge_params->sge_fl_buffer_size[1];
2446 struct sge *s = &adapter->sge;
2447
2448 /*
2449 * Start by vetting the basic SGE parameters which have been set up by
2450 * the Physical Function Driver. Ideally we should be able to deal
2451 * with _any_ configuration. Practice is different ...
2452 */
2453 if (fl0 != PAGE_SIZE || (fl1 != 0 && fl1 <= fl0)) {
2454 dev_err(adapter->pdev_dev, "bad SGE FL buffer sizes [%d, %d]\n",
2455 fl0, fl1);
2456 return -EINVAL;
2457 }
2458 if ((sge_params->sge_control & RXPKTCPLMODE) == 0) {
2459 dev_err(adapter->pdev_dev, "bad SGE CPL MODE\n");
2460 return -EINVAL;
2461 }
2462
2463 /*
2464 * Now translate the adapter parameters into our internal forms.
2465 */
2466 if (fl1)
2467 FL_PG_ORDER = ilog2(fl1) - PAGE_SHIFT;
2468 STAT_LEN = ((sge_params->sge_control & EGRSTATUSPAGESIZE) ? 128 : 64);
2469 PKTSHIFT = PKTSHIFT_GET(sge_params->sge_control);
2470 FL_ALIGN = 1 << (INGPADBOUNDARY_GET(sge_params->sge_control) +
Casey Leedomb3003be2010-06-29 12:54:12 +00002471 SGE_INGPADBOUNDARY_SHIFT);
Casey Leedomc6e0d912010-06-25 12:13:28 +00002472
2473 /*
2474 * Set up tasklet timers.
2475 */
2476 setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adapter);
2477 setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adapter);
2478
2479 /*
2480 * Initialize Forwarded Interrupt Queue lock.
2481 */
2482 spin_lock_init(&s->intrq_lock);
2483
2484 return 0;
2485}