Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include "drmP.h" |
| 27 | #include "drm_crtc_helper.h" |
| 28 | #include "radeon_drm.h" |
| 29 | #include "radeon.h" |
| 30 | #include "atom.h" |
| 31 | |
| 32 | extern int atom_debug; |
| 33 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 34 | /* evil but including atombios.h is much worse */ |
| 35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
| 36 | struct drm_display_mode *mode); |
| 37 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 38 | uint32_t |
| 39 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) |
| 40 | { |
| 41 | struct radeon_device *rdev = dev->dev_private; |
| 42 | uint32_t ret = 0; |
| 43 | |
| 44 | switch (supported_device) { |
| 45 | case ATOM_DEVICE_CRT1_SUPPORT: |
| 46 | case ATOM_DEVICE_TV1_SUPPORT: |
| 47 | case ATOM_DEVICE_TV2_SUPPORT: |
| 48 | case ATOM_DEVICE_CRT2_SUPPORT: |
| 49 | case ATOM_DEVICE_CV_SUPPORT: |
| 50 | switch (dac) { |
| 51 | case 1: /* dac a */ |
| 52 | if ((rdev->family == CHIP_RS300) || |
| 53 | (rdev->family == CHIP_RS400) || |
| 54 | (rdev->family == CHIP_RS480)) |
| 55 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; |
| 56 | else if (ASIC_IS_AVIVO(rdev)) |
| 57 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; |
| 58 | else |
| 59 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC1; |
| 60 | break; |
| 61 | case 2: /* dac b */ |
| 62 | if (ASIC_IS_AVIVO(rdev)) |
| 63 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; |
| 64 | else { |
| 65 | /*if (rdev->family == CHIP_R200) |
| 66 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
| 67 | else*/ |
| 68 | ret = ENCODER_OBJECT_ID_INTERNAL_DAC2; |
| 69 | } |
| 70 | break; |
| 71 | case 3: /* external dac */ |
| 72 | if (ASIC_IS_AVIVO(rdev)) |
| 73 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; |
| 74 | else |
| 75 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
| 76 | break; |
| 77 | } |
| 78 | break; |
| 79 | case ATOM_DEVICE_LCD1_SUPPORT: |
| 80 | if (ASIC_IS_AVIVO(rdev)) |
| 81 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; |
| 82 | else |
| 83 | ret = ENCODER_OBJECT_ID_INTERNAL_LVDS; |
| 84 | break; |
| 85 | case ATOM_DEVICE_DFP1_SUPPORT: |
| 86 | if ((rdev->family == CHIP_RS300) || |
| 87 | (rdev->family == CHIP_RS400) || |
| 88 | (rdev->family == CHIP_RS480)) |
| 89 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
| 90 | else if (ASIC_IS_AVIVO(rdev)) |
| 91 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; |
| 92 | else |
| 93 | ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1; |
| 94 | break; |
| 95 | case ATOM_DEVICE_LCD2_SUPPORT: |
| 96 | case ATOM_DEVICE_DFP2_SUPPORT: |
| 97 | if ((rdev->family == CHIP_RS600) || |
| 98 | (rdev->family == CHIP_RS690) || |
| 99 | (rdev->family == CHIP_RS740)) |
| 100 | ret = ENCODER_OBJECT_ID_INTERNAL_DDI; |
| 101 | else if (ASIC_IS_AVIVO(rdev)) |
| 102 | ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1; |
| 103 | else |
| 104 | ret = ENCODER_OBJECT_ID_INTERNAL_DVO1; |
| 105 | break; |
| 106 | case ATOM_DEVICE_DFP3_SUPPORT: |
| 107 | ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1; |
| 108 | break; |
| 109 | } |
| 110 | |
| 111 | return ret; |
| 112 | } |
| 113 | |
| 114 | void |
| 115 | radeon_link_encoder_connector(struct drm_device *dev) |
| 116 | { |
| 117 | struct drm_connector *connector; |
| 118 | struct radeon_connector *radeon_connector; |
| 119 | struct drm_encoder *encoder; |
| 120 | struct radeon_encoder *radeon_encoder; |
| 121 | |
| 122 | /* walk the list and link encoders to connectors */ |
| 123 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 124 | radeon_connector = to_radeon_connector(connector); |
| 125 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 126 | radeon_encoder = to_radeon_encoder(encoder); |
| 127 | if (radeon_encoder->devices & radeon_connector->devices) |
| 128 | drm_mode_connector_attach_encoder(connector, encoder); |
| 129 | } |
| 130 | } |
| 131 | } |
| 132 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 133 | void radeon_encoder_set_active_device(struct drm_encoder *encoder) |
| 134 | { |
| 135 | struct drm_device *dev = encoder->dev; |
| 136 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 137 | struct drm_connector *connector; |
| 138 | |
| 139 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 140 | if (connector->encoder == encoder) { |
| 141 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 142 | radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; |
Dave Airlie | f641e51 | 2009-09-08 11:17:38 +1000 | [diff] [blame] | 143 | DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n", |
| 144 | radeon_encoder->active_device, radeon_encoder->devices, |
| 145 | radeon_connector->devices, encoder->encoder_type); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 146 | } |
| 147 | } |
| 148 | } |
| 149 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 150 | static struct drm_connector * |
| 151 | radeon_get_connector_for_encoder(struct drm_encoder *encoder) |
| 152 | { |
| 153 | struct drm_device *dev = encoder->dev; |
| 154 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 155 | struct drm_connector *connector; |
| 156 | struct radeon_connector *radeon_connector; |
| 157 | |
| 158 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 159 | radeon_connector = to_radeon_connector(connector); |
| 160 | if (radeon_encoder->devices & radeon_connector->devices) |
| 161 | return connector; |
| 162 | } |
| 163 | return NULL; |
| 164 | } |
| 165 | |
| 166 | /* used for both atom and legacy */ |
| 167 | void radeon_rmx_mode_fixup(struct drm_encoder *encoder, |
| 168 | struct drm_display_mode *mode, |
| 169 | struct drm_display_mode *adjusted_mode) |
| 170 | { |
| 171 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 172 | struct drm_device *dev = encoder->dev; |
| 173 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 174 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 175 | |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 176 | if (mode->hdisplay < native_mode->hdisplay || |
| 177 | mode->vdisplay < native_mode->vdisplay) { |
Alex Deucher | fb06ca8 | 2009-10-12 11:25:05 -0400 | [diff] [blame] | 178 | int mode_id = adjusted_mode->base.id; |
Alex Deucher | de2103e | 2009-10-09 15:14:30 -0400 | [diff] [blame] | 179 | *adjusted_mode = *native_mode; |
| 180 | if (!ASIC_IS_AVIVO(rdev)) { |
| 181 | adjusted_mode->hdisplay = mode->hdisplay; |
| 182 | adjusted_mode->vdisplay = mode->vdisplay; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 183 | } |
Alex Deucher | fb06ca8 | 2009-10-12 11:25:05 -0400 | [diff] [blame] | 184 | adjusted_mode->base.id = mode_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 185 | } |
| 186 | } |
| 187 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 188 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 189 | static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, |
| 190 | struct drm_display_mode *mode, |
| 191 | struct drm_display_mode *adjusted_mode) |
| 192 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 193 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 194 | struct drm_device *dev = encoder->dev; |
| 195 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 196 | |
Alex Deucher | 8c2a6d7 | 2009-10-14 02:00:42 -0400 | [diff] [blame] | 197 | /* set the active encoder to connector routing */ |
| 198 | radeon_encoder_set_active_device(encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 199 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| 200 | |
| 201 | if (radeon_encoder->rmx_type != RMX_OFF) |
| 202 | radeon_rmx_mode_fixup(encoder, mode, adjusted_mode); |
| 203 | |
| 204 | /* hw bug */ |
| 205 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 206 | && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
| 207 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
| 208 | |
Alex Deucher | ceefedd | 2009-10-13 23:57:47 -0400 | [diff] [blame] | 209 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 210 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
| 211 | if (tv_dac) { |
| 212 | if (tv_dac->tv_std == TV_STD_NTSC || |
| 213 | tv_dac->tv_std == TV_STD_NTSC_J || |
| 214 | tv_dac->tv_std == TV_STD_PAL_M) |
| 215 | radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); |
| 216 | else |
| 217 | radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
| 218 | } |
| 219 | } |
| 220 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 221 | return true; |
| 222 | } |
| 223 | |
| 224 | static void |
| 225 | atombios_dac_setup(struct drm_encoder *encoder, int action) |
| 226 | { |
| 227 | struct drm_device *dev = encoder->dev; |
| 228 | struct radeon_device *rdev = dev->dev_private; |
| 229 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 230 | DAC_ENCODER_CONTROL_PS_ALLOCATION args; |
| 231 | int index = 0, num = 0; |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 232 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 233 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
| 234 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 235 | if (dac_info->tv_std) |
| 236 | tv_std = dac_info->tv_std; |
| 237 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 238 | memset(&args, 0, sizeof(args)); |
| 239 | |
| 240 | switch (radeon_encoder->encoder_id) { |
| 241 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 242 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 243 | index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); |
| 244 | num = 1; |
| 245 | break; |
| 246 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 247 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 248 | index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); |
| 249 | num = 2; |
| 250 | break; |
| 251 | } |
| 252 | |
| 253 | args.ucAction = action; |
| 254 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 255 | if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 256 | args.ucDacStandard = ATOM_DAC1_PS2; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 257 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 258 | args.ucDacStandard = ATOM_DAC1_CV; |
| 259 | else { |
| 260 | switch (tv_std) { |
| 261 | case TV_STD_PAL: |
| 262 | case TV_STD_PAL_M: |
| 263 | case TV_STD_SCART_PAL: |
| 264 | case TV_STD_SECAM: |
| 265 | case TV_STD_PAL_CN: |
| 266 | args.ucDacStandard = ATOM_DAC1_PAL; |
| 267 | break; |
| 268 | case TV_STD_NTSC: |
| 269 | case TV_STD_NTSC_J: |
| 270 | case TV_STD_PAL_60: |
| 271 | default: |
| 272 | args.ucDacStandard = ATOM_DAC1_NTSC; |
| 273 | break; |
| 274 | } |
| 275 | } |
| 276 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 277 | |
| 278 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 279 | |
| 280 | } |
| 281 | |
| 282 | static void |
| 283 | atombios_tv_setup(struct drm_encoder *encoder, int action) |
| 284 | { |
| 285 | struct drm_device *dev = encoder->dev; |
| 286 | struct radeon_device *rdev = dev->dev_private; |
| 287 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 288 | TV_ENCODER_CONTROL_PS_ALLOCATION args; |
| 289 | int index = 0; |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 290 | struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 291 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
| 292 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 293 | if (dac_info->tv_std) |
| 294 | tv_std = dac_info->tv_std; |
| 295 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 296 | memset(&args, 0, sizeof(args)); |
| 297 | |
| 298 | index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); |
| 299 | |
| 300 | args.sTVEncoder.ucAction = action; |
| 301 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 302 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 303 | args.sTVEncoder.ucTvStandard = ATOM_TV_CV; |
| 304 | else { |
| 305 | switch (tv_std) { |
| 306 | case TV_STD_NTSC: |
| 307 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
| 308 | break; |
| 309 | case TV_STD_PAL: |
| 310 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; |
| 311 | break; |
| 312 | case TV_STD_PAL_M: |
| 313 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; |
| 314 | break; |
| 315 | case TV_STD_PAL_60: |
| 316 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; |
| 317 | break; |
| 318 | case TV_STD_NTSC_J: |
| 319 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; |
| 320 | break; |
| 321 | case TV_STD_SCART_PAL: |
| 322 | args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ |
| 323 | break; |
| 324 | case TV_STD_SECAM: |
| 325 | args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; |
| 326 | break; |
| 327 | case TV_STD_PAL_CN: |
| 328 | args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; |
| 329 | break; |
| 330 | default: |
| 331 | args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; |
| 332 | break; |
| 333 | } |
| 334 | } |
| 335 | |
| 336 | args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 337 | |
| 338 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 339 | |
| 340 | } |
| 341 | |
| 342 | void |
| 343 | atombios_external_tmds_setup(struct drm_encoder *encoder, int action) |
| 344 | { |
| 345 | struct drm_device *dev = encoder->dev; |
| 346 | struct radeon_device *rdev = dev->dev_private; |
| 347 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 348 | ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args; |
| 349 | int index = 0; |
| 350 | |
| 351 | memset(&args, 0, sizeof(args)); |
| 352 | |
| 353 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
| 354 | |
| 355 | args.sXTmdsEncoder.ucEnable = action; |
| 356 | |
| 357 | if (radeon_encoder->pixel_clock > 165000) |
| 358 | args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL; |
| 359 | |
| 360 | /*if (pScrn->rgbBits == 8)*/ |
| 361 | args.sXTmdsEncoder.ucMisc |= (1 << 1); |
| 362 | |
| 363 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 364 | |
| 365 | } |
| 366 | |
| 367 | static void |
| 368 | atombios_ddia_setup(struct drm_encoder *encoder, int action) |
| 369 | { |
| 370 | struct drm_device *dev = encoder->dev; |
| 371 | struct radeon_device *rdev = dev->dev_private; |
| 372 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 373 | DVO_ENCODER_CONTROL_PS_ALLOCATION args; |
| 374 | int index = 0; |
| 375 | |
| 376 | memset(&args, 0, sizeof(args)); |
| 377 | |
| 378 | index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); |
| 379 | |
| 380 | args.sDVOEncoder.ucAction = action; |
| 381 | args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 382 | |
| 383 | if (radeon_encoder->pixel_clock > 165000) |
| 384 | args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL; |
| 385 | |
| 386 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 387 | |
| 388 | } |
| 389 | |
| 390 | union lvds_encoder_control { |
| 391 | LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; |
| 392 | LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; |
| 393 | }; |
| 394 | |
| 395 | static void |
| 396 | atombios_digital_setup(struct drm_encoder *encoder, int action) |
| 397 | { |
| 398 | struct drm_device *dev = encoder->dev; |
| 399 | struct radeon_device *rdev = dev->dev_private; |
| 400 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 401 | union lvds_encoder_control args; |
| 402 | int index = 0; |
| 403 | uint8_t frev, crev; |
| 404 | struct radeon_encoder_atom_dig *dig; |
| 405 | struct drm_connector *connector; |
| 406 | struct radeon_connector *radeon_connector; |
| 407 | struct radeon_connector_atom_dig *dig_connector; |
| 408 | |
| 409 | connector = radeon_get_connector_for_encoder(encoder); |
| 410 | if (!connector) |
| 411 | return; |
| 412 | |
| 413 | radeon_connector = to_radeon_connector(connector); |
| 414 | |
| 415 | if (!radeon_encoder->enc_priv) |
| 416 | return; |
| 417 | |
| 418 | dig = radeon_encoder->enc_priv; |
| 419 | |
| 420 | if (!radeon_connector->con_priv) |
| 421 | return; |
| 422 | |
| 423 | dig_connector = radeon_connector->con_priv; |
| 424 | |
| 425 | memset(&args, 0, sizeof(args)); |
| 426 | |
| 427 | switch (radeon_encoder->encoder_id) { |
| 428 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 429 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
| 430 | break; |
| 431 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 432 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 433 | index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); |
| 434 | break; |
| 435 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 436 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 437 | index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); |
| 438 | else |
| 439 | index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); |
| 440 | break; |
| 441 | } |
| 442 | |
| 443 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
| 444 | |
| 445 | switch (frev) { |
| 446 | case 1: |
| 447 | case 2: |
| 448 | switch (crev) { |
| 449 | case 1: |
| 450 | args.v1.ucMisc = 0; |
| 451 | args.v1.ucAction = action; |
Alex Deucher | 0294cf4f | 2009-10-15 16:16:35 -0400 | [diff] [blame] | 452 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 453 | args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
| 454 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 455 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 456 | if (dig->lvds_misc & (1 << 0)) |
| 457 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
| 458 | if (dig->lvds_misc & (1 << 1)) |
| 459 | args.v1.ucMisc |= (1 << 1); |
| 460 | } else { |
| 461 | if (dig_connector->linkb) |
| 462 | args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
| 463 | if (radeon_encoder->pixel_clock > 165000) |
| 464 | args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
| 465 | /*if (pScrn->rgbBits == 8) */ |
| 466 | args.v1.ucMisc |= (1 << 1); |
| 467 | } |
| 468 | break; |
| 469 | case 2: |
| 470 | case 3: |
| 471 | args.v2.ucMisc = 0; |
| 472 | args.v2.ucAction = action; |
| 473 | if (crev == 3) { |
| 474 | if (dig->coherent_mode) |
| 475 | args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; |
| 476 | } |
Alex Deucher | 0294cf4f | 2009-10-15 16:16:35 -0400 | [diff] [blame] | 477 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 478 | args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; |
| 479 | args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 480 | args.v2.ucTruncate = 0; |
| 481 | args.v2.ucSpatial = 0; |
| 482 | args.v2.ucTemporal = 0; |
| 483 | args.v2.ucFRC = 0; |
| 484 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 485 | if (dig->lvds_misc & (1 << 0)) |
| 486 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
| 487 | if (dig->lvds_misc & (1 << 5)) { |
| 488 | args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; |
| 489 | if (dig->lvds_misc & (1 << 1)) |
| 490 | args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; |
| 491 | } |
| 492 | if (dig->lvds_misc & (1 << 6)) { |
| 493 | args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; |
| 494 | if (dig->lvds_misc & (1 << 1)) |
| 495 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; |
| 496 | if (((dig->lvds_misc >> 2) & 0x3) == 2) |
| 497 | args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; |
| 498 | } |
| 499 | } else { |
| 500 | if (dig_connector->linkb) |
| 501 | args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; |
| 502 | if (radeon_encoder->pixel_clock > 165000) |
| 503 | args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; |
| 504 | } |
| 505 | break; |
| 506 | default: |
| 507 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
| 508 | break; |
| 509 | } |
| 510 | break; |
| 511 | default: |
| 512 | DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
| 513 | break; |
| 514 | } |
| 515 | |
| 516 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 517 | |
| 518 | } |
| 519 | |
| 520 | int |
| 521 | atombios_get_encoder_mode(struct drm_encoder *encoder) |
| 522 | { |
| 523 | struct drm_connector *connector; |
| 524 | struct radeon_connector *radeon_connector; |
| 525 | |
| 526 | connector = radeon_get_connector_for_encoder(encoder); |
| 527 | if (!connector) |
| 528 | return 0; |
| 529 | |
| 530 | radeon_connector = to_radeon_connector(connector); |
| 531 | |
| 532 | switch (connector->connector_type) { |
| 533 | case DRM_MODE_CONNECTOR_DVII: |
Alex Deucher | 705af9c | 2009-09-10 16:31:13 -0400 | [diff] [blame] | 534 | case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
Alex Deucher | 0294cf4f | 2009-10-15 16:16:35 -0400 | [diff] [blame] | 535 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 536 | return ATOM_ENCODER_MODE_HDMI; |
| 537 | else if (radeon_connector->use_digital) |
| 538 | return ATOM_ENCODER_MODE_DVI; |
| 539 | else |
| 540 | return ATOM_ENCODER_MODE_CRT; |
| 541 | break; |
| 542 | case DRM_MODE_CONNECTOR_DVID: |
| 543 | case DRM_MODE_CONNECTOR_HDMIA: |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 544 | default: |
Alex Deucher | 0294cf4f | 2009-10-15 16:16:35 -0400 | [diff] [blame] | 545 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 546 | return ATOM_ENCODER_MODE_HDMI; |
| 547 | else |
| 548 | return ATOM_ENCODER_MODE_DVI; |
| 549 | break; |
| 550 | case DRM_MODE_CONNECTOR_LVDS: |
| 551 | return ATOM_ENCODER_MODE_LVDS; |
| 552 | break; |
| 553 | case DRM_MODE_CONNECTOR_DisplayPort: |
| 554 | /*if (radeon_output->MonType == MT_DP) |
| 555 | return ATOM_ENCODER_MODE_DP; |
| 556 | else*/ |
Alex Deucher | 0294cf4f | 2009-10-15 16:16:35 -0400 | [diff] [blame] | 557 | if (drm_detect_hdmi_monitor(radeon_connector->edid)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 558 | return ATOM_ENCODER_MODE_HDMI; |
| 559 | else |
| 560 | return ATOM_ENCODER_MODE_DVI; |
| 561 | break; |
| 562 | case CONNECTOR_DVI_A: |
| 563 | case CONNECTOR_VGA: |
| 564 | return ATOM_ENCODER_MODE_CRT; |
| 565 | break; |
| 566 | case CONNECTOR_STV: |
| 567 | case CONNECTOR_CTV: |
| 568 | case CONNECTOR_DIN: |
| 569 | /* fix me */ |
| 570 | return ATOM_ENCODER_MODE_TV; |
| 571 | /*return ATOM_ENCODER_MODE_CV;*/ |
| 572 | break; |
| 573 | } |
| 574 | } |
| 575 | |
| 576 | static void |
| 577 | atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) |
| 578 | { |
| 579 | struct drm_device *dev = encoder->dev; |
| 580 | struct radeon_device *rdev = dev->dev_private; |
| 581 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 582 | DIG_ENCODER_CONTROL_PS_ALLOCATION args; |
| 583 | int index = 0, num = 0; |
| 584 | uint8_t frev, crev; |
| 585 | struct radeon_encoder_atom_dig *dig; |
| 586 | struct drm_connector *connector; |
| 587 | struct radeon_connector *radeon_connector; |
| 588 | struct radeon_connector_atom_dig *dig_connector; |
| 589 | |
| 590 | connector = radeon_get_connector_for_encoder(encoder); |
| 591 | if (!connector) |
| 592 | return; |
| 593 | |
| 594 | radeon_connector = to_radeon_connector(connector); |
| 595 | |
| 596 | if (!radeon_connector->con_priv) |
| 597 | return; |
| 598 | |
| 599 | dig_connector = radeon_connector->con_priv; |
| 600 | |
| 601 | if (!radeon_encoder->enc_priv) |
| 602 | return; |
| 603 | |
| 604 | dig = radeon_encoder->enc_priv; |
| 605 | |
| 606 | memset(&args, 0, sizeof(args)); |
| 607 | |
| 608 | if (ASIC_IS_DCE32(rdev)) { |
| 609 | if (dig->dig_block) |
| 610 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
| 611 | else |
| 612 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
| 613 | num = dig->dig_block + 1; |
| 614 | } else { |
| 615 | switch (radeon_encoder->encoder_id) { |
| 616 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 617 | index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); |
| 618 | num = 1; |
| 619 | break; |
| 620 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 621 | index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); |
| 622 | num = 2; |
| 623 | break; |
| 624 | } |
| 625 | } |
| 626 | |
| 627 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
| 628 | |
| 629 | args.ucAction = action; |
| 630 | args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 631 | |
| 632 | if (ASIC_IS_DCE32(rdev)) { |
| 633 | switch (radeon_encoder->encoder_id) { |
| 634 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 635 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; |
| 636 | break; |
| 637 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 638 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; |
| 639 | break; |
| 640 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 641 | args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; |
| 642 | break; |
| 643 | } |
| 644 | } else { |
| 645 | switch (radeon_encoder->encoder_id) { |
| 646 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 647 | args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; |
| 648 | break; |
| 649 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 650 | args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; |
| 651 | break; |
| 652 | } |
| 653 | } |
| 654 | |
| 655 | if (radeon_encoder->pixel_clock > 165000) { |
| 656 | args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B; |
| 657 | args.ucLaneNum = 8; |
| 658 | } else { |
| 659 | if (dig_connector->linkb) |
| 660 | args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; |
| 661 | else |
| 662 | args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; |
| 663 | args.ucLaneNum = 4; |
| 664 | } |
| 665 | |
| 666 | args.ucEncoderMode = atombios_get_encoder_mode(encoder); |
| 667 | |
| 668 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 669 | |
| 670 | } |
| 671 | |
| 672 | union dig_transmitter_control { |
| 673 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
| 674 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
| 675 | }; |
| 676 | |
| 677 | static void |
| 678 | atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action) |
| 679 | { |
| 680 | struct drm_device *dev = encoder->dev; |
| 681 | struct radeon_device *rdev = dev->dev_private; |
| 682 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 683 | union dig_transmitter_control args; |
| 684 | int index = 0, num = 0; |
| 685 | uint8_t frev, crev; |
| 686 | struct radeon_encoder_atom_dig *dig; |
| 687 | struct drm_connector *connector; |
| 688 | struct radeon_connector *radeon_connector; |
| 689 | struct radeon_connector_atom_dig *dig_connector; |
| 690 | |
| 691 | connector = radeon_get_connector_for_encoder(encoder); |
| 692 | if (!connector) |
| 693 | return; |
| 694 | |
| 695 | radeon_connector = to_radeon_connector(connector); |
| 696 | |
| 697 | if (!radeon_encoder->enc_priv) |
| 698 | return; |
| 699 | |
| 700 | dig = radeon_encoder->enc_priv; |
| 701 | |
| 702 | if (!radeon_connector->con_priv) |
| 703 | return; |
| 704 | |
| 705 | dig_connector = radeon_connector->con_priv; |
| 706 | |
| 707 | memset(&args, 0, sizeof(args)); |
| 708 | |
| 709 | if (ASIC_IS_DCE32(rdev)) |
| 710 | index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
| 711 | else { |
| 712 | switch (radeon_encoder->encoder_id) { |
| 713 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 714 | index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl); |
| 715 | break; |
| 716 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 717 | index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl); |
| 718 | break; |
| 719 | } |
| 720 | } |
| 721 | |
| 722 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
| 723 | |
| 724 | args.v1.ucAction = action; |
Alex Deucher | f95a9f0 | 2009-11-05 02:21:06 -0500 | [diff] [blame^] | 725 | if (action == ATOM_TRANSMITTER_ACTION_INIT) { |
| 726 | args.v1.usInitInfo = radeon_connector->connector_object_id; |
| 727 | } else { |
| 728 | if (radeon_encoder->pixel_clock > 165000) |
| 729 | args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
| 730 | else |
| 731 | args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
| 732 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 733 | if (ASIC_IS_DCE32(rdev)) { |
Alex Deucher | f95a9f0 | 2009-11-05 02:21:06 -0500 | [diff] [blame^] | 734 | if (radeon_encoder->pixel_clock > 165000) |
Alex Deucher | 4170a6c1 | 2009-11-05 01:16:23 -0500 | [diff] [blame] | 735 | args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 736 | if (dig->dig_block) |
| 737 | args.v2.acConfig.ucEncoderSel = 1; |
| 738 | |
| 739 | switch (radeon_encoder->encoder_id) { |
| 740 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 741 | args.v2.acConfig.ucTransmitterSel = 0; |
| 742 | num = 0; |
| 743 | break; |
| 744 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 745 | args.v2.acConfig.ucTransmitterSel = 1; |
| 746 | num = 1; |
| 747 | break; |
| 748 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 749 | args.v2.acConfig.ucTransmitterSel = 2; |
| 750 | num = 2; |
| 751 | break; |
| 752 | } |
| 753 | |
| 754 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 755 | if (dig->coherent_mode) |
| 756 | args.v2.acConfig.fCoherentMode = 1; |
| 757 | } |
| 758 | } else { |
| 759 | args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 760 | |
| 761 | switch (radeon_encoder->encoder_id) { |
| 762 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 763 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; |
| 764 | if (rdev->flags & RADEON_IS_IGP) { |
| 765 | if (radeon_encoder->pixel_clock > 165000) { |
| 766 | args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | |
| 767 | ATOM_TRANSMITTER_CONFIG_LINKA_B); |
| 768 | if (dig_connector->igp_lane_info & 0x3) |
| 769 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; |
| 770 | else if (dig_connector->igp_lane_info & 0xc) |
| 771 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; |
| 772 | } else { |
| 773 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; |
| 774 | if (dig_connector->igp_lane_info & 0x1) |
| 775 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
| 776 | else if (dig_connector->igp_lane_info & 0x2) |
| 777 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; |
| 778 | else if (dig_connector->igp_lane_info & 0x4) |
| 779 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; |
| 780 | else if (dig_connector->igp_lane_info & 0x8) |
| 781 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; |
| 782 | } |
| 783 | } else { |
| 784 | if (radeon_encoder->pixel_clock > 165000) |
| 785 | args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | |
| 786 | ATOM_TRANSMITTER_CONFIG_LINKA_B | |
| 787 | ATOM_TRANSMITTER_CONFIG_LANE_0_7); |
| 788 | else { |
| 789 | if (dig_connector->linkb) |
| 790 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
| 791 | else |
| 792 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
| 793 | } |
| 794 | } |
| 795 | break; |
| 796 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 797 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; |
| 798 | if (radeon_encoder->pixel_clock > 165000) |
| 799 | args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK | |
| 800 | ATOM_TRANSMITTER_CONFIG_LINKA_B | |
| 801 | ATOM_TRANSMITTER_CONFIG_LANE_0_7); |
| 802 | else { |
| 803 | if (dig_connector->linkb) |
| 804 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
| 805 | else |
| 806 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3; |
| 807 | } |
| 808 | break; |
| 809 | } |
| 810 | |
| 811 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 812 | if (dig->coherent_mode) |
| 813 | args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; |
| 814 | } |
| 815 | } |
| 816 | |
| 817 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 818 | |
| 819 | } |
| 820 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 821 | static void |
| 822 | atombios_yuv_setup(struct drm_encoder *encoder, bool enable) |
| 823 | { |
| 824 | struct drm_device *dev = encoder->dev; |
| 825 | struct radeon_device *rdev = dev->dev_private; |
| 826 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 827 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 828 | ENABLE_YUV_PS_ALLOCATION args; |
| 829 | int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); |
| 830 | uint32_t temp, reg; |
| 831 | |
| 832 | memset(&args, 0, sizeof(args)); |
| 833 | |
| 834 | if (rdev->family >= CHIP_R600) |
| 835 | reg = R600_BIOS_3_SCRATCH; |
| 836 | else |
| 837 | reg = RADEON_BIOS_3_SCRATCH; |
| 838 | |
| 839 | /* XXX: fix up scratch reg handling */ |
| 840 | temp = RREG32(reg); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 841 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 842 | WREG32(reg, (ATOM_S3_TV1_ACTIVE | |
| 843 | (radeon_crtc->crtc_id << 18))); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 844 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 845 | WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); |
| 846 | else |
| 847 | WREG32(reg, 0); |
| 848 | |
| 849 | if (enable) |
| 850 | args.ucEnable = ATOM_ENABLE; |
| 851 | args.ucCRTC = radeon_crtc->crtc_id; |
| 852 | |
| 853 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 854 | |
| 855 | WREG32(reg, temp); |
| 856 | } |
| 857 | |
| 858 | static void |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 859 | radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
| 860 | { |
| 861 | struct drm_device *dev = encoder->dev; |
| 862 | struct radeon_device *rdev = dev->dev_private; |
| 863 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 864 | DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; |
| 865 | int index = 0; |
| 866 | bool is_dig = false; |
| 867 | |
| 868 | memset(&args, 0, sizeof(args)); |
| 869 | |
Dave Airlie | f641e51 | 2009-09-08 11:17:38 +1000 | [diff] [blame] | 870 | DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
| 871 | radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
| 872 | radeon_encoder->active_device); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 873 | switch (radeon_encoder->encoder_id) { |
| 874 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 875 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 876 | index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); |
| 877 | break; |
| 878 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 879 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 880 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 881 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 882 | is_dig = true; |
| 883 | break; |
| 884 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 885 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 886 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 887 | index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); |
| 888 | break; |
| 889 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 890 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
| 891 | break; |
| 892 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 893 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 894 | index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); |
| 895 | else |
| 896 | index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); |
| 897 | break; |
| 898 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 899 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
Alex Deucher | 8c2a6d7 | 2009-10-14 02:00:42 -0400 | [diff] [blame] | 900 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 901 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
Alex Deucher | 8c2a6d7 | 2009-10-14 02:00:42 -0400 | [diff] [blame] | 902 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 903 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
| 904 | else |
| 905 | index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); |
| 906 | break; |
| 907 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 908 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
Alex Deucher | 8c2a6d7 | 2009-10-14 02:00:42 -0400 | [diff] [blame] | 909 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 910 | index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); |
Alex Deucher | 8c2a6d7 | 2009-10-14 02:00:42 -0400 | [diff] [blame] | 911 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 912 | index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); |
| 913 | else |
| 914 | index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); |
| 915 | break; |
| 916 | } |
| 917 | |
| 918 | if (is_dig) { |
| 919 | switch (mode) { |
| 920 | case DRM_MODE_DPMS_ON: |
| 921 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE); |
| 922 | break; |
| 923 | case DRM_MODE_DPMS_STANDBY: |
| 924 | case DRM_MODE_DPMS_SUSPEND: |
| 925 | case DRM_MODE_DPMS_OFF: |
| 926 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE); |
| 927 | break; |
| 928 | } |
| 929 | } else { |
| 930 | switch (mode) { |
| 931 | case DRM_MODE_DPMS_ON: |
| 932 | args.ucAction = ATOM_ENABLE; |
| 933 | break; |
| 934 | case DRM_MODE_DPMS_STANDBY: |
| 935 | case DRM_MODE_DPMS_SUSPEND: |
| 936 | case DRM_MODE_DPMS_OFF: |
| 937 | args.ucAction = ATOM_DISABLE; |
| 938 | break; |
| 939 | } |
| 940 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 941 | } |
| 942 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 943 | } |
| 944 | |
| 945 | union crtc_sourc_param { |
| 946 | SELECT_CRTC_SOURCE_PS_ALLOCATION v1; |
| 947 | SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; |
| 948 | }; |
| 949 | |
| 950 | static void |
| 951 | atombios_set_encoder_crtc_source(struct drm_encoder *encoder) |
| 952 | { |
| 953 | struct drm_device *dev = encoder->dev; |
| 954 | struct radeon_device *rdev = dev->dev_private; |
| 955 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 956 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 957 | union crtc_sourc_param args; |
| 958 | int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); |
| 959 | uint8_t frev, crev; |
| 960 | |
| 961 | memset(&args, 0, sizeof(args)); |
| 962 | |
| 963 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
| 964 | |
| 965 | switch (frev) { |
| 966 | case 1: |
| 967 | switch (crev) { |
| 968 | case 1: |
| 969 | default: |
| 970 | if (ASIC_IS_AVIVO(rdev)) |
| 971 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
| 972 | else { |
| 973 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { |
| 974 | args.v1.ucCRTC = radeon_crtc->crtc_id; |
| 975 | } else { |
| 976 | args.v1.ucCRTC = radeon_crtc->crtc_id << 2; |
| 977 | } |
| 978 | } |
| 979 | switch (radeon_encoder->encoder_id) { |
| 980 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 981 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 982 | args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; |
| 983 | break; |
| 984 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 985 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 986 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) |
| 987 | args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; |
| 988 | else |
| 989 | args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; |
| 990 | break; |
| 991 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 992 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 993 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 994 | args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; |
| 995 | break; |
| 996 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 997 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 998 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 999 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1000 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1001 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
| 1002 | else |
| 1003 | args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; |
| 1004 | break; |
| 1005 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1006 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1007 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1008 | args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1009 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1010 | args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; |
| 1011 | else |
| 1012 | args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; |
| 1013 | break; |
| 1014 | } |
| 1015 | break; |
| 1016 | case 2: |
| 1017 | args.v2.ucCRTC = radeon_crtc->crtc_id; |
| 1018 | args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
| 1019 | switch (radeon_encoder->encoder_id) { |
| 1020 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1021 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1022 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 1023 | if (ASIC_IS_DCE32(rdev)) { |
| 1024 | if (radeon_crtc->crtc_id) |
| 1025 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
| 1026 | else |
| 1027 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
| 1028 | } else |
| 1029 | args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; |
| 1030 | break; |
| 1031 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 1032 | args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; |
| 1033 | break; |
| 1034 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 1035 | args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; |
| 1036 | break; |
| 1037 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1038 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1039 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1040 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1041 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
| 1042 | else |
| 1043 | args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; |
| 1044 | break; |
| 1045 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1046 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1047 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1048 | else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1049 | args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; |
| 1050 | else |
| 1051 | args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; |
| 1052 | break; |
| 1053 | } |
| 1054 | break; |
| 1055 | } |
| 1056 | break; |
| 1057 | default: |
| 1058 | DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); |
| 1059 | break; |
| 1060 | } |
| 1061 | |
| 1062 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1063 | |
| 1064 | } |
| 1065 | |
| 1066 | static void |
| 1067 | atombios_apply_encoder_quirks(struct drm_encoder *encoder, |
| 1068 | struct drm_display_mode *mode) |
| 1069 | { |
| 1070 | struct drm_device *dev = encoder->dev; |
| 1071 | struct radeon_device *rdev = dev->dev_private; |
| 1072 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1073 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 1074 | |
| 1075 | /* Funky macbooks */ |
| 1076 | if ((dev->pdev->device == 0x71C5) && |
| 1077 | (dev->pdev->subsystem_vendor == 0x106b) && |
| 1078 | (dev->pdev->subsystem_device == 0x0080)) { |
| 1079 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
| 1080 | uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); |
| 1081 | |
| 1082 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
| 1083 | lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
| 1084 | |
| 1085 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); |
| 1086 | } |
| 1087 | } |
| 1088 | |
| 1089 | /* set scaler clears this on some chips */ |
Alex Deucher | ceefedd | 2009-10-13 23:57:47 -0400 | [diff] [blame] | 1090 | if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { |
| 1091 | if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) |
| 1092 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
| 1093 | AVIVO_D1MODE_INTERLEAVE_EN); |
| 1094 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1095 | } |
| 1096 | |
| 1097 | static void |
| 1098 | radeon_atom_encoder_mode_set(struct drm_encoder *encoder, |
| 1099 | struct drm_display_mode *mode, |
| 1100 | struct drm_display_mode *adjusted_mode) |
| 1101 | { |
| 1102 | struct drm_device *dev = encoder->dev; |
| 1103 | struct radeon_device *rdev = dev->dev_private; |
| 1104 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1105 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 1106 | |
| 1107 | if (radeon_encoder->enc_priv) { |
| 1108 | struct radeon_encoder_atom_dig *dig; |
| 1109 | |
| 1110 | dig = radeon_encoder->enc_priv; |
| 1111 | dig->dig_block = radeon_crtc->crtc_id; |
| 1112 | } |
| 1113 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
| 1114 | |
| 1115 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1116 | atombios_set_encoder_crtc_source(encoder); |
| 1117 | |
| 1118 | if (ASIC_IS_AVIVO(rdev)) { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1119 | if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1120 | atombios_yuv_setup(encoder, true); |
| 1121 | else |
| 1122 | atombios_yuv_setup(encoder, false); |
| 1123 | } |
| 1124 | |
| 1125 | switch (radeon_encoder->encoder_id) { |
| 1126 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 1127 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 1128 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 1129 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 1130 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
| 1131 | break; |
| 1132 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1133 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1134 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 1135 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 1136 | /* disable the encoder and transmitter */ |
| 1137 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE); |
| 1138 | atombios_dig_encoder_setup(encoder, ATOM_DISABLE); |
| 1139 | |
| 1140 | /* setup and enable the encoder and transmitter */ |
| 1141 | atombios_dig_encoder_setup(encoder, ATOM_ENABLE); |
Alex Deucher | f95a9f0 | 2009-11-05 02:21:06 -0500 | [diff] [blame^] | 1142 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1143 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP); |
| 1144 | atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE); |
| 1145 | break; |
| 1146 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 1147 | atombios_ddia_setup(encoder, ATOM_ENABLE); |
| 1148 | break; |
| 1149 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 1150 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 1151 | atombios_external_tmds_setup(encoder, ATOM_ENABLE); |
| 1152 | break; |
| 1153 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 1154 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 1155 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1156 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 1157 | atombios_dac_setup(encoder, ATOM_ENABLE); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1158 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1159 | atombios_tv_setup(encoder, ATOM_ENABLE); |
| 1160 | break; |
| 1161 | } |
| 1162 | atombios_apply_encoder_quirks(encoder, adjusted_mode); |
| 1163 | } |
| 1164 | |
| 1165 | static bool |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1166 | atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1167 | { |
| 1168 | struct drm_device *dev = encoder->dev; |
| 1169 | struct radeon_device *rdev = dev->dev_private; |
| 1170 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1171 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1172 | |
| 1173 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | |
| 1174 | ATOM_DEVICE_CV_SUPPORT | |
| 1175 | ATOM_DEVICE_CRT_SUPPORT)) { |
| 1176 | DAC_LOAD_DETECTION_PS_ALLOCATION args; |
| 1177 | int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); |
| 1178 | uint8_t frev, crev; |
| 1179 | |
| 1180 | memset(&args, 0, sizeof(args)); |
| 1181 | |
| 1182 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); |
| 1183 | |
| 1184 | args.sDacload.ucMisc = 0; |
| 1185 | |
| 1186 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || |
| 1187 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) |
| 1188 | args.sDacload.ucDacType = ATOM_DAC_A; |
| 1189 | else |
| 1190 | args.sDacload.ucDacType = ATOM_DAC_B; |
| 1191 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1192 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1193 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1194 | else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1195 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1196 | else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1197 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); |
| 1198 | if (crev >= 3) |
| 1199 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1200 | } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1201 | args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); |
| 1202 | if (crev >= 3) |
| 1203 | args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; |
| 1204 | } |
| 1205 | |
| 1206 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 1207 | |
| 1208 | return true; |
| 1209 | } else |
| 1210 | return false; |
| 1211 | } |
| 1212 | |
| 1213 | static enum drm_connector_status |
| 1214 | radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
| 1215 | { |
| 1216 | struct drm_device *dev = encoder->dev; |
| 1217 | struct radeon_device *rdev = dev->dev_private; |
| 1218 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1219 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1220 | uint32_t bios_0_scratch; |
| 1221 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1222 | if (!atombios_dac_load_detect(encoder, connector)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1223 | DRM_DEBUG("detect returned false \n"); |
| 1224 | return connector_status_unknown; |
| 1225 | } |
| 1226 | |
| 1227 | if (rdev->family >= CHIP_R600) |
| 1228 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
| 1229 | else |
| 1230 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
| 1231 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1232 | DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); |
| 1233 | if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1234 | if (bios_0_scratch & ATOM_S0_CRT1_MASK) |
| 1235 | return connector_status_connected; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1236 | } |
| 1237 | if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1238 | if (bios_0_scratch & ATOM_S0_CRT2_MASK) |
| 1239 | return connector_status_connected; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1240 | } |
| 1241 | if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1242 | if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) |
| 1243 | return connector_status_connected; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1244 | } |
| 1245 | if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1246 | if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) |
| 1247 | return connector_status_connected; /* CTV */ |
| 1248 | else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) |
| 1249 | return connector_status_connected; /* STV */ |
| 1250 | } |
| 1251 | return connector_status_disconnected; |
| 1252 | } |
| 1253 | |
| 1254 | static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) |
| 1255 | { |
| 1256 | radeon_atom_output_lock(encoder, true); |
| 1257 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 1258 | } |
| 1259 | |
| 1260 | static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
| 1261 | { |
| 1262 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
| 1263 | radeon_atom_output_lock(encoder, false); |
| 1264 | } |
| 1265 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1266 | static void radeon_atom_encoder_disable(struct drm_encoder *encoder) |
| 1267 | { |
| 1268 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1269 | radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1270 | radeon_encoder->active_device = 0; |
| 1271 | } |
| 1272 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1273 | static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { |
| 1274 | .dpms = radeon_atom_encoder_dpms, |
| 1275 | .mode_fixup = radeon_atom_mode_fixup, |
| 1276 | .prepare = radeon_atom_encoder_prepare, |
| 1277 | .mode_set = radeon_atom_encoder_mode_set, |
| 1278 | .commit = radeon_atom_encoder_commit, |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1279 | .disable = radeon_atom_encoder_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1280 | /* no detect for TMDS/LVDS yet */ |
| 1281 | }; |
| 1282 | |
| 1283 | static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { |
| 1284 | .dpms = radeon_atom_encoder_dpms, |
| 1285 | .mode_fixup = radeon_atom_mode_fixup, |
| 1286 | .prepare = radeon_atom_encoder_prepare, |
| 1287 | .mode_set = radeon_atom_encoder_mode_set, |
| 1288 | .commit = radeon_atom_encoder_commit, |
| 1289 | .detect = radeon_atom_dac_detect, |
| 1290 | }; |
| 1291 | |
| 1292 | void radeon_enc_destroy(struct drm_encoder *encoder) |
| 1293 | { |
| 1294 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1295 | kfree(radeon_encoder->enc_priv); |
| 1296 | drm_encoder_cleanup(encoder); |
| 1297 | kfree(radeon_encoder); |
| 1298 | } |
| 1299 | |
| 1300 | static const struct drm_encoder_funcs radeon_atom_enc_funcs = { |
| 1301 | .destroy = radeon_enc_destroy, |
| 1302 | }; |
| 1303 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1304 | struct radeon_encoder_atom_dac * |
| 1305 | radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) |
| 1306 | { |
| 1307 | struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); |
| 1308 | |
| 1309 | if (!dac) |
| 1310 | return NULL; |
| 1311 | |
| 1312 | dac->tv_std = TV_STD_NTSC; |
| 1313 | return dac; |
| 1314 | } |
| 1315 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1316 | struct radeon_encoder_atom_dig * |
| 1317 | radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) |
| 1318 | { |
| 1319 | struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
| 1320 | |
| 1321 | if (!dig) |
| 1322 | return NULL; |
| 1323 | |
| 1324 | /* coherent mode by default */ |
| 1325 | dig->coherent_mode = true; |
| 1326 | |
| 1327 | return dig; |
| 1328 | } |
| 1329 | |
| 1330 | void |
| 1331 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) |
| 1332 | { |
Dave Airlie | dfee561 | 2009-10-02 09:19:09 +1000 | [diff] [blame] | 1333 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1334 | struct drm_encoder *encoder; |
| 1335 | struct radeon_encoder *radeon_encoder; |
| 1336 | |
| 1337 | /* see if we already added it */ |
| 1338 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 1339 | radeon_encoder = to_radeon_encoder(encoder); |
| 1340 | if (radeon_encoder->encoder_id == encoder_id) { |
| 1341 | radeon_encoder->devices |= supported_device; |
| 1342 | return; |
| 1343 | } |
| 1344 | |
| 1345 | } |
| 1346 | |
| 1347 | /* add a new one */ |
| 1348 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
| 1349 | if (!radeon_encoder) |
| 1350 | return; |
| 1351 | |
| 1352 | encoder = &radeon_encoder->base; |
Dave Airlie | dfee561 | 2009-10-02 09:19:09 +1000 | [diff] [blame] | 1353 | if (rdev->flags & RADEON_SINGLE_CRTC) |
| 1354 | encoder->possible_crtcs = 0x1; |
| 1355 | else |
| 1356 | encoder->possible_crtcs = 0x3; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1357 | encoder->possible_clones = 0; |
| 1358 | |
| 1359 | radeon_encoder->enc_priv = NULL; |
| 1360 | |
| 1361 | radeon_encoder->encoder_id = encoder_id; |
| 1362 | radeon_encoder->devices = supported_device; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1363 | radeon_encoder->rmx_type = RMX_OFF; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1364 | |
| 1365 | switch (radeon_encoder->encoder_id) { |
| 1366 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
| 1367 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 1368 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 1369 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 1370 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 1371 | radeon_encoder->rmx_type = RMX_FULL; |
| 1372 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
| 1373 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
| 1374 | } else { |
| 1375 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
| 1376 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
| 1377 | } |
| 1378 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
| 1379 | break; |
| 1380 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 1381 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); |
| 1382 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
| 1383 | break; |
| 1384 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1385 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 1386 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 1387 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1388 | radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1389 | drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); |
| 1390 | break; |
| 1391 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 1392 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 1393 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 1394 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 1395 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
| 1396 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 1397 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
Alex Deucher | 60d15f5 | 2009-09-08 14:22:45 -0400 | [diff] [blame] | 1398 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 1399 | radeon_encoder->rmx_type = RMX_FULL; |
| 1400 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |
| 1401 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
| 1402 | } else { |
| 1403 | drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); |
| 1404 | radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); |
| 1405 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1406 | drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); |
| 1407 | break; |
| 1408 | } |
| 1409 | } |