Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / f99b1649dbb6342d618307faef1f214fd54928b9 / . / arch / mips / cavium-octeon / Kconfig
blob: 227705d9d5ae8fffacd336683d64851cca557cbe [file] [log] [blame]
David Daney23a271e2011-02-17 18:23:32 -0800[diff] [blame]1if CPU_CAVIUM_OCTEON
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]2
David Daneyc9941152010-10-07 16:03:53 -0700[diff] [blame]3config CAVIUM_CN63XXP1
4 bool "Enable CN63XXP1 errata worarounds"
David Daneyc9941152010-10-07 16:03:53 -0700[diff] [blame]5 default "n"
6 help
7 The CN63XXP1 chip requires build time workarounds to
8 function reliably, select this option to enable them. These
9 workarounds will cause a slight decrease in performance on
10 non-CN63XXP1 hardware, so it is recommended to select "n"
11 unless it is known the workarounds are needed.
12
David Daney9ddebc42013-05-22 15:10:46 +0000[diff] [blame]13endif # CPU_CAVIUM_OCTEON
14
15if CAVIUM_OCTEON_SOC
16
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]17config CAVIUM_OCTEON_2ND_KERNEL
18 bool "Build the kernel to be used as a 2nd kernel on the same chip"
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]19 default "n"
20 help
21 This option configures this kernel to be linked at a different
22 address and use the 2nd uart for output. This allows a kernel built
23 with this option to be run at the same time as one built without this
24 option.
25
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]26config CAVIUM_OCTEON_CVMSEG_SIZE
27 int "Number of L1 cache lines reserved for CVMSEG memory"
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]28 range 0 54
29 default 1
30 help
31 CVMSEG LM is a segment that accesses portions of the dcache as a
32 local memory; the larger CVMSEG is, the smaller the cache is.
33 This selects the size of CVMSEG LM, which is in cache blocks. The
34 legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
35 between zero and 6192 bytes).
36
37config CAVIUM_OCTEON_LOCK_L2
38 bool "Lock often used kernel code in the L2"
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]39 default "y"
40 help
41 Enable locking parts of the kernel into the L2 cache.
42
43config CAVIUM_OCTEON_LOCK_L2_TLB
44 bool "Lock the TLB handler in L2"
45 depends on CAVIUM_OCTEON_LOCK_L2
46 default "y"
47 help
48 Lock the low level TLB fast path into L2.
49
50config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
51 bool "Lock the exception handler in L2"
52 depends on CAVIUM_OCTEON_LOCK_L2
53 default "y"
54 help
55 Lock the low level exception handler into L2.
56
57config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
58 bool "Lock the interrupt handler in L2"
59 depends on CAVIUM_OCTEON_LOCK_L2
60 default "y"
61 help
62 Lock the low level interrupt handler into L2.
63
64config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
65 bool "Lock the 2nd level interrupt handler in L2"
66 depends on CAVIUM_OCTEON_LOCK_L2
67 default "y"
68 help
69 Lock the 2nd level interrupt handler in L2.
70
71config CAVIUM_OCTEON_LOCK_L2_MEMCPY
72 bool "Lock memcpy() in L2"
73 depends on CAVIUM_OCTEON_LOCK_L2
74 default "y"
75 help
76 Lock the kernel's implementation of memcpy() into L2.
77
David Daneyb93b2ab2010-10-01 13:27:34 -0700[diff] [blame]78config IOMMU_HELPER
79 bool
80
81config NEED_SG_DMA_LENGTH
82 bool
83
84config SWIOTLB
85 def_bool y
David Daneyb93b2ab2010-10-01 13:27:34 -0700[diff] [blame]86 select IOMMU_HELPER
87 select NEED_SG_DMA_LENGTH
David Daney23a271e2011-02-17 18:23:32 -0800[diff] [blame]88
89
Venkat Subbiah0e49caf2012-12-02 00:51:26 +0000[diff] [blame]90config OCTEON_ILM
91 tristate "Module to measure interrupt latency using Octeon CIU Timer"
92 help
93 This driver is a module to measure interrupt latency using the
94 the CIU Timers on Octeon.
95
96 To compile this driver as a module, choose M here. The module
97 will be called octeon-ilm
98
David Daney9ddebc42013-05-22 15:10:46 +0000[diff] [blame]99endif # CAVIUM_OCTEON_SOC