blob: 307cd142f06a325c273b099a1419332d6b5aa677 [file] [log] [blame]
Sascha Hauer1f1846c2010-10-06 10:25:55 +02001/*
2 * drivers/dma/imx-dma.c
3 *
4 * This file contains a driver for the Freescale i.MX DMA engine
5 * found on i.MX1/21/27
6 *
7 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
Javier Martin9e15db72012-03-02 09:28:47 +01008 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
Sascha Hauer1f1846c2010-10-06 10:25:55 +02009 *
10 * The code contained herein is licensed under the GNU General Public
11 * License. You may obtain a copy of the GNU General Public License
12 * Version 2 or later at the following locations:
13 *
14 * http://www.opensource.org/licenses/gpl-license.html
15 * http://www.gnu.org/copyleft/gpl.html
16 */
17#include <linux/init.h>
Axel Linf8de8f42011-08-30 15:08:24 +080018#include <linux/module.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020019#include <linux/types.h>
20#include <linux/mm.h>
21#include <linux/interrupt.h>
22#include <linux/spinlock.h>
23#include <linux/device.h>
24#include <linux/dma-mapping.h>
25#include <linux/slab.h>
26#include <linux/platform_device.h>
Javier Martin6bd08122012-03-22 14:54:01 +010027#include <linux/clk.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020028#include <linux/dmaengine.h>
Vinod Koul5170c052012-03-09 14:55:25 +053029#include <linux/module.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020030
31#include <asm/irq.h>
Javier Martin6bd08122012-03-22 14:54:01 +010032#include <mach/dma.h>
Sascha Hauer1f1846c2010-10-06 10:25:55 +020033#include <mach/hardware.h>
34
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000035#include "dmaengine.h"
Javier Martin9e15db72012-03-02 09:28:47 +010036#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
Javier Martin6bd08122012-03-22 14:54:01 +010037#define IMX_DMA_CHANNELS 16
38
Javier Martin6bd08122012-03-22 14:54:01 +010039#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
40#define IMX_DMA_MEMSIZE_32 (0 << 4)
41#define IMX_DMA_MEMSIZE_8 (1 << 4)
42#define IMX_DMA_MEMSIZE_16 (2 << 4)
43#define IMX_DMA_TYPE_LINEAR (0 << 10)
44#define IMX_DMA_TYPE_2D (1 << 10)
45#define IMX_DMA_TYPE_FIFO (2 << 10)
46
47#define IMX_DMA_ERR_BURST (1 << 0)
48#define IMX_DMA_ERR_REQUEST (1 << 1)
49#define IMX_DMA_ERR_TRANSFER (1 << 2)
50#define IMX_DMA_ERR_BUFFER (1 << 3)
51#define IMX_DMA_ERR_TIMEOUT (1 << 4)
52
53#define DMA_DCR 0x00 /* Control Register */
54#define DMA_DISR 0x04 /* Interrupt status Register */
55#define DMA_DIMR 0x08 /* Interrupt mask Register */
56#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
57#define DMA_DRTOSR 0x10 /* Request timeout Register */
58#define DMA_DSESR 0x14 /* Transfer Error Status Register */
59#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
60#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
61#define DMA_WSRA 0x40 /* W-Size Register A */
62#define DMA_XSRA 0x44 /* X-Size Register A */
63#define DMA_YSRA 0x48 /* Y-Size Register A */
64#define DMA_WSRB 0x4c /* W-Size Register B */
65#define DMA_XSRB 0x50 /* X-Size Register B */
66#define DMA_YSRB 0x54 /* Y-Size Register B */
67#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
68#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
69#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
70#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
71#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
72#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
73#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
74#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
75#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
76
77#define DCR_DRST (1<<1)
78#define DCR_DEN (1<<0)
79#define DBTOCR_EN (1<<15)
80#define DBTOCR_CNT(x) ((x) & 0x7fff)
81#define CNTR_CNT(x) ((x) & 0xffffff)
82#define CCR_ACRPT (1<<14)
83#define CCR_DMOD_LINEAR (0x0 << 12)
84#define CCR_DMOD_2D (0x1 << 12)
85#define CCR_DMOD_FIFO (0x2 << 12)
86#define CCR_DMOD_EOBFIFO (0x3 << 12)
87#define CCR_SMOD_LINEAR (0x0 << 10)
88#define CCR_SMOD_2D (0x1 << 10)
89#define CCR_SMOD_FIFO (0x2 << 10)
90#define CCR_SMOD_EOBFIFO (0x3 << 10)
91#define CCR_MDIR_DEC (1<<9)
92#define CCR_MSEL_B (1<<8)
93#define CCR_DSIZ_32 (0x0 << 6)
94#define CCR_DSIZ_8 (0x1 << 6)
95#define CCR_DSIZ_16 (0x2 << 6)
96#define CCR_SSIZ_32 (0x0 << 4)
97#define CCR_SSIZ_8 (0x1 << 4)
98#define CCR_SSIZ_16 (0x2 << 4)
99#define CCR_REN (1<<3)
100#define CCR_RPT (1<<2)
101#define CCR_FRC (1<<1)
102#define CCR_CEN (1<<0)
103#define RTOR_EN (1<<15)
104#define RTOR_CLK (1<<14)
105#define RTOR_PSC (1<<13)
Javier Martin9e15db72012-03-02 09:28:47 +0100106
107enum imxdma_prep_type {
108 IMXDMA_DESC_MEMCPY,
109 IMXDMA_DESC_INTERLEAVED,
110 IMXDMA_DESC_SLAVE_SG,
111 IMXDMA_DESC_CYCLIC,
112};
113
114struct imxdma_desc {
115 struct list_head node;
116 struct dma_async_tx_descriptor desc;
117 enum dma_status status;
118 dma_addr_t src;
119 dma_addr_t dest;
120 size_t len;
Javier Martin2efc3442012-03-22 14:54:03 +0100121 enum dma_transfer_direction direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100122 enum imxdma_prep_type type;
123 /* For memcpy and interleaved */
124 unsigned int config_port;
125 unsigned int config_mem;
126 /* For interleaved transfers */
127 unsigned int x;
128 unsigned int y;
129 unsigned int w;
130 /* For slave sg and cyclic */
131 struct scatterlist *sg;
132 unsigned int sgcount;
133};
134
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200135struct imxdma_channel {
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100136 int hw_chaining;
137 struct timer_list watchdog;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200138 struct imxdma_engine *imxdma;
139 unsigned int channel;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200140
Javier Martin9e15db72012-03-02 09:28:47 +0100141 struct tasklet_struct dma_tasklet;
142 struct list_head ld_free;
143 struct list_head ld_queue;
144 struct list_head ld_active;
145 int descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200146 enum dma_slave_buswidth word_size;
147 dma_addr_t per_address;
148 u32 watermark_level;
149 struct dma_chan chan;
150 spinlock_t lock;
151 struct dma_async_tx_descriptor desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200152 enum dma_status status;
153 int dma_request;
154 struct scatterlist *sg_list;
Javier Martin359291a2012-03-22 14:54:06 +0100155 u32 ccr_from_device;
156 u32 ccr_to_device;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200157};
158
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200159struct imxdma_engine {
160 struct device *dev;
Sascha Hauer1e070a62011-01-12 13:14:37 +0100161 struct device_dma_parameters dma_parms;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200162 struct dma_device dma_device;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100163 void __iomem *base;
164 struct clk *dma_clk;
Javier Martin6bd08122012-03-22 14:54:01 +0100165 struct imxdma_channel channel[IMX_DMA_CHANNELS];
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200166};
167
168static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
169{
170 return container_of(chan, struct imxdma_channel, chan);
171}
172
Javier Martin9e15db72012-03-02 09:28:47 +0100173static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200174{
Javier Martin9e15db72012-03-02 09:28:47 +0100175 struct imxdma_desc *desc;
176
177 if (!list_empty(&imxdmac->ld_active)) {
178 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
179 node);
180 if (desc->type == IMXDMA_DESC_CYCLIC)
181 return true;
182 }
183 return false;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200184}
185
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200186
Javier Martincd5cf9d2012-03-22 14:54:12 +0100187
188static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
189 unsigned offset)
Javier Martin6bd08122012-03-22 14:54:01 +0100190{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100191 __raw_writel(val, imxdma->base + offset);
Javier Martin6bd08122012-03-22 14:54:01 +0100192}
193
Javier Martincd5cf9d2012-03-22 14:54:12 +0100194static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
Javier Martin6bd08122012-03-22 14:54:01 +0100195{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100196 return __raw_readl(imxdma->base + offset);
Javier Martin6bd08122012-03-22 14:54:01 +0100197}
198
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100199static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
Javier Martin6bd08122012-03-22 14:54:01 +0100200{
201 if (cpu_is_mx27())
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100202 return imxdmac->hw_chaining;
Javier Martin6bd08122012-03-22 14:54:01 +0100203 else
204 return 0;
205}
206
207/*
208 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
209 */
Javier Martina6cbb2d2012-03-22 14:54:11 +0100210static inline int imxdma_sg_next(struct imxdma_desc *d)
Javier Martin6bd08122012-03-22 14:54:01 +0100211{
Javier Martin2efc3442012-03-22 14:54:03 +0100212 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100213 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martina6cbb2d2012-03-22 14:54:11 +0100214 struct scatterlist *sg = d->sg;
Javier Martin6bd08122012-03-22 14:54:01 +0100215 unsigned long now;
216
Javier Martin6b0e2f52012-03-22 14:54:09 +0100217 now = min(d->len, sg->length);
218 if (d->len != IMX_DMA_LENGTH_LOOP)
219 d->len -= now;
Javier Martin6bd08122012-03-22 14:54:01 +0100220
Javier Martin2efc3442012-03-22 14:54:03 +0100221 if (d->direction == DMA_DEV_TO_MEM)
Javier Martincd5cf9d2012-03-22 14:54:12 +0100222 imx_dmav1_writel(imxdma, sg->dma_address,
223 DMA_DAR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100224 else
Javier Martincd5cf9d2012-03-22 14:54:12 +0100225 imx_dmav1_writel(imxdma, sg->dma_address,
226 DMA_SAR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100227
Javier Martincd5cf9d2012-03-22 14:54:12 +0100228 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100229
Javier Martinf9b283a2012-03-22 14:54:13 +0100230 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
231 "size 0x%08x\n", __func__, imxdmac->channel,
Javier Martincd5cf9d2012-03-22 14:54:12 +0100232 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
233 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
234 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
Javier Martin6bd08122012-03-22 14:54:01 +0100235
236 return now;
237}
238
Javier Martin2efc3442012-03-22 14:54:03 +0100239static void imxdma_enable_hw(struct imxdma_desc *d)
Javier Martin6bd08122012-03-22 14:54:01 +0100240{
Javier Martin2efc3442012-03-22 14:54:03 +0100241 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100242 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100243 int channel = imxdmac->channel;
244 unsigned long flags;
245
Javier Martinf9b283a2012-03-22 14:54:13 +0100246 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100247
Javier Martin6bd08122012-03-22 14:54:01 +0100248 local_irq_save(flags);
249
Javier Martincd5cf9d2012-03-22 14:54:12 +0100250 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
251 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
252 ~(1 << channel), DMA_DIMR);
253 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
254 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100255
256 if ((cpu_is_mx21() || cpu_is_mx27()) &&
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100257 d->sg && imxdma_hw_chain(imxdmac)) {
Javier Martin833bc032012-03-22 14:54:07 +0100258 d->sg = sg_next(d->sg);
259 if (d->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100260 u32 tmp;
Javier Martina6cbb2d2012-03-22 14:54:11 +0100261 imxdma_sg_next(d);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100262 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
263 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
264 DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100265 }
266 }
Javier Martin6bd08122012-03-22 14:54:01 +0100267
268 local_irq_restore(flags);
269}
270
271static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
272{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100273 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100274 int channel = imxdmac->channel;
275 unsigned long flags;
276
Javier Martinf9b283a2012-03-22 14:54:13 +0100277 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100278
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100279 if (imxdma_hw_chain(imxdmac))
280 del_timer(&imxdmac->watchdog);
Javier Martin6bd08122012-03-22 14:54:01 +0100281
282 local_irq_save(flags);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100283 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
284 (1 << channel), DMA_DIMR);
285 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
286 ~CCR_CEN, DMA_CCR(channel));
287 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100288 local_irq_restore(flags);
289}
290
Javier Martin6bd08122012-03-22 14:54:01 +0100291static void imxdma_watchdog(unsigned long data)
292{
293 struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100294 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100295 int channel = imxdmac->channel;
296
Javier Martincd5cf9d2012-03-22 14:54:12 +0100297 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
Javier Martin6bd08122012-03-22 14:54:01 +0100298
299 /* Tasklet watchdog error handler */
300 tasklet_schedule(&imxdmac->dma_tasklet);
Javier Martinf9b283a2012-03-22 14:54:13 +0100301 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
302 imxdmac->channel);
Javier Martin6bd08122012-03-22 14:54:01 +0100303}
304
305static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
306{
307 struct imxdma_engine *imxdma = dev_id;
Javier Martin6bd08122012-03-22 14:54:01 +0100308 unsigned int err_mask;
309 int i, disr;
310 int errcode;
311
Javier Martincd5cf9d2012-03-22 14:54:12 +0100312 disr = imx_dmav1_readl(imxdma, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100313
Javier Martincd5cf9d2012-03-22 14:54:12 +0100314 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
315 imx_dmav1_readl(imxdma, DMA_DRTOSR) |
316 imx_dmav1_readl(imxdma, DMA_DSESR) |
317 imx_dmav1_readl(imxdma, DMA_DBOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100318
319 if (!err_mask)
320 return IRQ_HANDLED;
321
Javier Martincd5cf9d2012-03-22 14:54:12 +0100322 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100323
324 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
325 if (!(err_mask & (1 << i)))
326 continue;
Javier Martin6bd08122012-03-22 14:54:01 +0100327 errcode = 0;
328
Javier Martincd5cf9d2012-03-22 14:54:12 +0100329 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
330 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100331 errcode |= IMX_DMA_ERR_BURST;
332 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100333 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
334 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100335 errcode |= IMX_DMA_ERR_REQUEST;
336 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100337 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
338 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
Javier Martin6bd08122012-03-22 14:54:01 +0100339 errcode |= IMX_DMA_ERR_TRANSFER;
340 }
Javier Martincd5cf9d2012-03-22 14:54:12 +0100341 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
342 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
Javier Martin6bd08122012-03-22 14:54:01 +0100343 errcode |= IMX_DMA_ERR_BUFFER;
344 }
345 /* Tasklet error handler */
346 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
347
348 printk(KERN_WARNING
349 "DMA timeout on channel %d -%s%s%s%s\n", i,
350 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
351 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
352 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
353 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
354 }
355 return IRQ_HANDLED;
356}
357
358static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
359{
Javier Martincd5cf9d2012-03-22 14:54:12 +0100360 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin6bd08122012-03-22 14:54:01 +0100361 int chno = imxdmac->channel;
Javier Martin2efc3442012-03-22 14:54:03 +0100362 struct imxdma_desc *desc;
Javier Martin6bd08122012-03-22 14:54:01 +0100363
Javier Martin833bc032012-03-22 14:54:07 +0100364 spin_lock(&imxdmac->lock);
365 if (list_empty(&imxdmac->ld_active)) {
366 spin_unlock(&imxdmac->lock);
367 goto out;
368 }
369
370 desc = list_first_entry(&imxdmac->ld_active,
371 struct imxdma_desc,
372 node);
373 spin_unlock(&imxdmac->lock);
374
375 if (desc->sg) {
Javier Martin6bd08122012-03-22 14:54:01 +0100376 u32 tmp;
Javier Martin833bc032012-03-22 14:54:07 +0100377 desc->sg = sg_next(desc->sg);
Javier Martin6bd08122012-03-22 14:54:01 +0100378
Javier Martin833bc032012-03-22 14:54:07 +0100379 if (desc->sg) {
Javier Martina6cbb2d2012-03-22 14:54:11 +0100380 imxdma_sg_next(desc);
Javier Martin6bd08122012-03-22 14:54:01 +0100381
Javier Martincd5cf9d2012-03-22 14:54:12 +0100382 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100383
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100384 if (imxdma_hw_chain(imxdmac)) {
Javier Martin6bd08122012-03-22 14:54:01 +0100385 /* FIXME: The timeout should probably be
386 * configurable
387 */
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100388 mod_timer(&imxdmac->watchdog,
Javier Martin6bd08122012-03-22 14:54:01 +0100389 jiffies + msecs_to_jiffies(500));
390
391 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100392 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100393 } else {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100394 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
395 DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100396 tmp |= CCR_CEN;
397 }
398
Javier Martincd5cf9d2012-03-22 14:54:12 +0100399 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100400
401 if (imxdma_chan_is_doing_cyclic(imxdmac))
402 /* Tasklet progression */
403 tasklet_schedule(&imxdmac->dma_tasklet);
404
405 return;
406 }
407
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100408 if (imxdma_hw_chain(imxdmac)) {
409 del_timer(&imxdmac->watchdog);
Javier Martin6bd08122012-03-22 14:54:01 +0100410 return;
411 }
412 }
413
Javier Martin2efc3442012-03-22 14:54:03 +0100414out:
Javier Martincd5cf9d2012-03-22 14:54:12 +0100415 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
Javier Martin6bd08122012-03-22 14:54:01 +0100416 /* Tasklet irq */
Javier Martin9e15db72012-03-02 09:28:47 +0100417 tasklet_schedule(&imxdmac->dma_tasklet);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200418}
419
Javier Martin6bd08122012-03-22 14:54:01 +0100420static irqreturn_t dma_irq_handler(int irq, void *dev_id)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200421{
Javier Martin6bd08122012-03-22 14:54:01 +0100422 struct imxdma_engine *imxdma = dev_id;
Javier Martin6bd08122012-03-22 14:54:01 +0100423 int i, disr;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200424
Javier Martin6bd08122012-03-22 14:54:01 +0100425 if (cpu_is_mx21() || cpu_is_mx27())
426 imxdma_err_handler(irq, dev_id);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200427
Javier Martincd5cf9d2012-03-22 14:54:12 +0100428 disr = imx_dmav1_readl(imxdma, DMA_DISR);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200429
Javier Martinf9b283a2012-03-22 14:54:13 +0100430 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
Javier Martin6bd08122012-03-22 14:54:01 +0100431
Javier Martincd5cf9d2012-03-22 14:54:12 +0100432 imx_dmav1_writel(imxdma, disr, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100433 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100434 if (disr & (1 << i))
Javier Martin6bd08122012-03-22 14:54:01 +0100435 dma_irq_handle_channel(&imxdma->channel[i]);
Javier Martin6bd08122012-03-22 14:54:01 +0100436 }
437
438 return IRQ_HANDLED;
Javier Martin9e15db72012-03-02 09:28:47 +0100439}
440
441static int imxdma_xfer_desc(struct imxdma_desc *d)
442{
443 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
Javier Martin3b4b6df2012-03-22 14:54:04 +0100444 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100445
446 /* Configure and enable */
447 switch (d->type) {
448 case IMXDMA_DESC_MEMCPY:
Javier Martincd5cf9d2012-03-22 14:54:12 +0100449 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
450 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
451 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
Javier Martin3b4b6df2012-03-22 14:54:04 +0100452 DMA_CCR(imxdmac->channel));
453
Javier Martincd5cf9d2012-03-22 14:54:12 +0100454 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
Javier Martin3b4b6df2012-03-22 14:54:04 +0100455
456 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
457 "dma_length=%d\n", __func__, imxdmac->channel,
458 d->dest, d->src, d->len);
459
460 break;
Javier Martin6bd08122012-03-22 14:54:01 +0100461 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
Javier Martin9e15db72012-03-02 09:28:47 +0100462 case IMXDMA_DESC_CYCLIC:
Javier Martin9e15db72012-03-02 09:28:47 +0100463 case IMXDMA_DESC_SLAVE_SG:
Javier Martin359291a2012-03-22 14:54:06 +0100464 if (d->direction == DMA_DEV_TO_MEM) {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100465 imx_dmav1_writel(imxdma, imxdmac->per_address,
Javier Martin359291a2012-03-22 14:54:06 +0100466 DMA_SAR(imxdmac->channel));
Javier Martincd5cf9d2012-03-22 14:54:12 +0100467 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
Javier Martin359291a2012-03-22 14:54:06 +0100468 DMA_CCR(imxdmac->channel));
469
470 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
471 "total length=%d dev_addr=0x%08x (dev2mem)\n",
472 __func__, imxdmac->channel, d->sg, d->sgcount,
473 d->len, imxdmac->per_address);
474 } else if (d->direction == DMA_MEM_TO_DEV) {
Javier Martincd5cf9d2012-03-22 14:54:12 +0100475 imx_dmav1_writel(imxdma, imxdmac->per_address,
Javier Martin359291a2012-03-22 14:54:06 +0100476 DMA_DAR(imxdmac->channel));
Javier Martincd5cf9d2012-03-22 14:54:12 +0100477 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
Javier Martin359291a2012-03-22 14:54:06 +0100478 DMA_CCR(imxdmac->channel));
479
480 dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
481 "total length=%d dev_addr=0x%08x (mem2dev)\n",
482 __func__, imxdmac->channel, d->sg, d->sgcount,
483 d->len, imxdmac->per_address);
484 } else {
485 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
486 __func__, imxdmac->channel);
487 return -EINVAL;
488 }
489
Javier Martina6cbb2d2012-03-22 14:54:11 +0100490 imxdma_sg_next(d);
Javier Martin359291a2012-03-22 14:54:06 +0100491
Javier Martin9e15db72012-03-02 09:28:47 +0100492 break;
493 default:
494 return -EINVAL;
495 }
Javier Martin2efc3442012-03-22 14:54:03 +0100496 imxdma_enable_hw(d);
Javier Martin9e15db72012-03-02 09:28:47 +0100497 return 0;
498}
499
500static void imxdma_tasklet(unsigned long data)
501{
502 struct imxdma_channel *imxdmac = (void *)data;
503 struct imxdma_engine *imxdma = imxdmac->imxdma;
504 struct imxdma_desc *desc;
505
506 spin_lock(&imxdmac->lock);
507
508 if (list_empty(&imxdmac->ld_active)) {
509 /* Someone might have called terminate all */
510 goto out;
511 }
512 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
513
514 if (desc->desc.callback)
515 desc->desc.callback(desc->desc.callback_param);
516
Vinod Koul1f3d6dc2012-03-13 12:39:49 +0530517 dma_cookie_complete(&desc->desc);
Javier Martin9e15db72012-03-02 09:28:47 +0100518
519 /* If we are dealing with a cyclic descriptor keep it on ld_active */
520 if (imxdma_chan_is_doing_cyclic(imxdmac))
521 goto out;
522
523 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
524
525 if (!list_empty(&imxdmac->ld_queue)) {
526 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
527 node);
528 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
529 if (imxdma_xfer_desc(desc) < 0)
530 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
531 __func__, imxdmac->channel);
532 }
533out:
534 spin_unlock(&imxdmac->lock);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200535}
536
537static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
538 unsigned long arg)
539{
540 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
541 struct dma_slave_config *dmaengine_cfg = (void *)arg;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100542 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100543 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200544 unsigned int mode = 0;
545
546 switch (cmd) {
547 case DMA_TERMINATE_ALL:
Javier Martin6bd08122012-03-22 14:54:01 +0100548 imxdma_disable_hw(imxdmac);
Javier Martin9e15db72012-03-02 09:28:47 +0100549
550 spin_lock_irqsave(&imxdmac->lock, flags);
551 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
552 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
553 spin_unlock_irqrestore(&imxdmac->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200554 return 0;
555 case DMA_SLAVE_CONFIG:
Vinod Kouldb8196d2011-10-13 22:34:23 +0530556 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200557 imxdmac->per_address = dmaengine_cfg->src_addr;
558 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
559 imxdmac->word_size = dmaengine_cfg->src_addr_width;
560 } else {
561 imxdmac->per_address = dmaengine_cfg->dst_addr;
562 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
563 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
564 }
565
566 switch (imxdmac->word_size) {
567 case DMA_SLAVE_BUSWIDTH_1_BYTE:
568 mode = IMX_DMA_MEMSIZE_8;
569 break;
570 case DMA_SLAVE_BUSWIDTH_2_BYTES:
571 mode = IMX_DMA_MEMSIZE_16;
572 break;
573 default:
574 case DMA_SLAVE_BUSWIDTH_4_BYTES:
575 mode = IMX_DMA_MEMSIZE_32;
576 break;
577 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200578
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100579 imxdmac->hw_chaining = 1;
580 if (!imxdma_hw_chain(imxdmac))
Javier Martinbdc0c752012-03-22 14:54:05 +0100581 return -EINVAL;
Javier Martin359291a2012-03-22 14:54:06 +0100582 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
Javier Martinbdc0c752012-03-22 14:54:05 +0100583 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
584 CCR_REN;
Javier Martin359291a2012-03-22 14:54:06 +0100585 imxdmac->ccr_to_device =
Javier Martinbdc0c752012-03-22 14:54:05 +0100586 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
587 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
Javier Martincd5cf9d2012-03-22 14:54:12 +0100588 imx_dmav1_writel(imxdma, imxdmac->dma_request,
Javier Martinbdc0c752012-03-22 14:54:05 +0100589 DMA_RSSR(imxdmac->channel));
590
Javier Martin6bd08122012-03-22 14:54:01 +0100591 /* Set burst length */
Javier Martincd5cf9d2012-03-22 14:54:12 +0100592 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
593 imxdmac->word_size, DMA_BLR(imxdmac->channel));
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200594
595 return 0;
596 default:
597 return -ENOSYS;
598 }
599
600 return -EINVAL;
601}
602
603static enum dma_status imxdma_tx_status(struct dma_chan *chan,
604 dma_cookie_t cookie,
605 struct dma_tx_state *txstate)
606{
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +0000607 return dma_cookie_status(chan, cookie, txstate);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200608}
609
610static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
611{
612 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
613 dma_cookie_t cookie;
Javier Martin9e15db72012-03-02 09:28:47 +0100614 unsigned long flags;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200615
Javier Martin9e15db72012-03-02 09:28:47 +0100616 spin_lock_irqsave(&imxdmac->lock, flags);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000617 cookie = dma_cookie_assign(tx);
Javier Martin9e15db72012-03-02 09:28:47 +0100618 spin_unlock_irqrestore(&imxdmac->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200619
620 return cookie;
621}
622
623static int imxdma_alloc_chan_resources(struct dma_chan *chan)
624{
625 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
626 struct imx_dma_data *data = chan->private;
627
Javier Martin6c05f092012-02-28 17:08:17 +0100628 if (data != NULL)
629 imxdmac->dma_request = data->dma_request;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200630
Javier Martin9e15db72012-03-02 09:28:47 +0100631 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
632 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200633
Javier Martin9e15db72012-03-02 09:28:47 +0100634 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
635 if (!desc)
636 break;
637 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
638 dma_async_tx_descriptor_init(&desc->desc, chan);
639 desc->desc.tx_submit = imxdma_tx_submit;
640 /* txd.flags will be overwritten in prep funcs */
641 desc->desc.flags = DMA_CTRL_ACK;
642 desc->status = DMA_SUCCESS;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200643
Javier Martin9e15db72012-03-02 09:28:47 +0100644 list_add_tail(&desc->node, &imxdmac->ld_free);
645 imxdmac->descs_allocated++;
646 }
647
648 if (!imxdmac->descs_allocated)
649 return -ENOMEM;
650
651 return imxdmac->descs_allocated;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200652}
653
654static void imxdma_free_chan_resources(struct dma_chan *chan)
655{
656 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martin9e15db72012-03-02 09:28:47 +0100657 struct imxdma_desc *desc, *_desc;
658 unsigned long flags;
659
660 spin_lock_irqsave(&imxdmac->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200661
Javier Martin6bd08122012-03-22 14:54:01 +0100662 imxdma_disable_hw(imxdmac);
Javier Martin9e15db72012-03-02 09:28:47 +0100663 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
664 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
665
666 spin_unlock_irqrestore(&imxdmac->lock, flags);
667
668 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
669 kfree(desc);
670 imxdmac->descs_allocated--;
671 }
672 INIT_LIST_HEAD(&imxdmac->ld_free);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200673
674 if (imxdmac->sg_list) {
675 kfree(imxdmac->sg_list);
676 imxdmac->sg_list = NULL;
677 }
678}
679
680static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
681 struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530682 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500683 unsigned long flags, void *context)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200684{
685 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
686 struct scatterlist *sg;
Javier Martin9e15db72012-03-02 09:28:47 +0100687 int i, dma_length = 0;
688 struct imxdma_desc *desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200689
Javier Martin9e15db72012-03-02 09:28:47 +0100690 if (list_empty(&imxdmac->ld_free) ||
691 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200692 return NULL;
693
Javier Martin9e15db72012-03-02 09:28:47 +0100694 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200695
696 for_each_sg(sgl, sg, sg_len, i) {
697 dma_length += sg->length;
698 }
699
Sascha Hauerd07102a2011-01-12 14:13:23 +0100700 switch (imxdmac->word_size) {
701 case DMA_SLAVE_BUSWIDTH_4_BYTES:
702 if (sgl->length & 3 || sgl->dma_address & 3)
703 return NULL;
704 break;
705 case DMA_SLAVE_BUSWIDTH_2_BYTES:
706 if (sgl->length & 1 || sgl->dma_address & 1)
707 return NULL;
708 break;
709 case DMA_SLAVE_BUSWIDTH_1_BYTE:
710 break;
711 default:
712 return NULL;
713 }
714
Javier Martin9e15db72012-03-02 09:28:47 +0100715 desc->type = IMXDMA_DESC_SLAVE_SG;
716 desc->sg = sgl;
717 desc->sgcount = sg_len;
718 desc->len = dma_length;
Javier Martin2efc3442012-03-22 14:54:03 +0100719 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100720 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100721 desc->src = imxdmac->per_address;
722 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100723 desc->dest = imxdmac->per_address;
724 }
725 desc->desc.callback = NULL;
726 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200727
Javier Martin9e15db72012-03-02 09:28:47 +0100728 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200729}
730
731static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
732 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500733 size_t period_len, enum dma_transfer_direction direction,
734 void *context)
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200735{
736 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
737 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100738 struct imxdma_desc *desc;
739 int i;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200740 unsigned int periods = buf_len / period_len;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200741
742 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
743 __func__, imxdmac->channel, buf_len, period_len);
744
Javier Martin9e15db72012-03-02 09:28:47 +0100745 if (list_empty(&imxdmac->ld_free) ||
746 imxdma_chan_is_doing_cyclic(imxdmac))
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200747 return NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200748
Javier Martin9e15db72012-03-02 09:28:47 +0100749 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200750
751 if (imxdmac->sg_list)
752 kfree(imxdmac->sg_list);
753
754 imxdmac->sg_list = kcalloc(periods + 1,
755 sizeof(struct scatterlist), GFP_KERNEL);
756 if (!imxdmac->sg_list)
757 return NULL;
758
759 sg_init_table(imxdmac->sg_list, periods);
760
761 for (i = 0; i < periods; i++) {
762 imxdmac->sg_list[i].page_link = 0;
763 imxdmac->sg_list[i].offset = 0;
764 imxdmac->sg_list[i].dma_address = dma_addr;
765 imxdmac->sg_list[i].length = period_len;
766 dma_addr += period_len;
767 }
768
769 /* close the loop */
770 imxdmac->sg_list[periods].offset = 0;
771 imxdmac->sg_list[periods].length = 0;
772 imxdmac->sg_list[periods].page_link =
773 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
774
Javier Martin9e15db72012-03-02 09:28:47 +0100775 desc->type = IMXDMA_DESC_CYCLIC;
776 desc->sg = imxdmac->sg_list;
777 desc->sgcount = periods;
778 desc->len = IMX_DMA_LENGTH_LOOP;
Javier Martin2efc3442012-03-22 14:54:03 +0100779 desc->direction = direction;
Javier Martin9e15db72012-03-02 09:28:47 +0100780 if (direction == DMA_DEV_TO_MEM) {
Javier Martin9e15db72012-03-02 09:28:47 +0100781 desc->src = imxdmac->per_address;
782 } else {
Javier Martin9e15db72012-03-02 09:28:47 +0100783 desc->dest = imxdmac->per_address;
784 }
785 desc->desc.callback = NULL;
786 desc->desc.callback_param = NULL;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200787
Javier Martin9e15db72012-03-02 09:28:47 +0100788 return &desc->desc;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200789}
790
Javier Martin6c05f092012-02-28 17:08:17 +0100791static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
792 struct dma_chan *chan, dma_addr_t dest,
793 dma_addr_t src, size_t len, unsigned long flags)
794{
795 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
796 struct imxdma_engine *imxdma = imxdmac->imxdma;
Javier Martin9e15db72012-03-02 09:28:47 +0100797 struct imxdma_desc *desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100798
799 dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
800 __func__, imxdmac->channel, src, dest, len);
801
Javier Martin9e15db72012-03-02 09:28:47 +0100802 if (list_empty(&imxdmac->ld_free) ||
803 imxdma_chan_is_doing_cyclic(imxdmac))
Javier Martin6c05f092012-02-28 17:08:17 +0100804 return NULL;
805
Javier Martin9e15db72012-03-02 09:28:47 +0100806 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
Javier Martin6c05f092012-02-28 17:08:17 +0100807
Javier Martin9e15db72012-03-02 09:28:47 +0100808 desc->type = IMXDMA_DESC_MEMCPY;
809 desc->src = src;
810 desc->dest = dest;
811 desc->len = len;
Javier Martin2efc3442012-03-22 14:54:03 +0100812 desc->direction = DMA_MEM_TO_MEM;
Javier Martin9e15db72012-03-02 09:28:47 +0100813 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
814 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
815 desc->desc.callback = NULL;
816 desc->desc.callback_param = NULL;
817
818 return &desc->desc;
Javier Martin6c05f092012-02-28 17:08:17 +0100819}
820
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200821static void imxdma_issue_pending(struct dma_chan *chan)
822{
Sascha Hauer5b316872012-01-09 10:32:49 +0100823 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
Javier Martin9e15db72012-03-02 09:28:47 +0100824 struct imxdma_engine *imxdma = imxdmac->imxdma;
825 struct imxdma_desc *desc;
826 unsigned long flags;
Sascha Hauer5b316872012-01-09 10:32:49 +0100827
Javier Martin9e15db72012-03-02 09:28:47 +0100828 spin_lock_irqsave(&imxdmac->lock, flags);
829 if (list_empty(&imxdmac->ld_active) &&
830 !list_empty(&imxdmac->ld_queue)) {
831 desc = list_first_entry(&imxdmac->ld_queue,
832 struct imxdma_desc, node);
833
834 if (imxdma_xfer_desc(desc) < 0) {
835 dev_warn(imxdma->dev,
836 "%s: channel: %d couldn't issue DMA xfer\n",
837 __func__, imxdmac->channel);
838 } else {
839 list_move_tail(imxdmac->ld_queue.next,
840 &imxdmac->ld_active);
841 }
842 }
843 spin_unlock_irqrestore(&imxdmac->lock, flags);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200844}
845
846static int __init imxdma_probe(struct platform_device *pdev)
Javier Martin6bd08122012-03-22 14:54:01 +0100847 {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200848 struct imxdma_engine *imxdma;
849 int ret, i;
850
Javier Martin6bd08122012-03-22 14:54:01 +0100851
Javier Martincd5cf9d2012-03-22 14:54:12 +0100852 imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
853 if (!imxdma)
854 return -ENOMEM;
855
856 if (cpu_is_mx1()) {
857 imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
858 } else if (cpu_is_mx21()) {
859 imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
860 } else if (cpu_is_mx27()) {
861 imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
862 } else {
863 kfree(imxdma);
864 return 0;
865 }
866
867 imxdma->dma_clk = clk_get(NULL, "dma");
868 if (IS_ERR(imxdma->dma_clk))
869 return PTR_ERR(imxdma->dma_clk);
870 clk_enable(imxdma->dma_clk);
Javier Martin6bd08122012-03-22 14:54:01 +0100871
872 /* reset DMA module */
Javier Martincd5cf9d2012-03-22 14:54:12 +0100873 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
Javier Martin6bd08122012-03-22 14:54:01 +0100874
875 if (cpu_is_mx1()) {
876 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
877 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +0100878 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
Javier Martincd5cf9d2012-03-22 14:54:12 +0100879 kfree(imxdma);
Javier Martin6bd08122012-03-22 14:54:01 +0100880 return ret;
881 }
882
883 ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
884 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +0100885 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
Javier Martin6bd08122012-03-22 14:54:01 +0100886 free_irq(MX1_DMA_INT, NULL);
Javier Martincd5cf9d2012-03-22 14:54:12 +0100887 kfree(imxdma);
Javier Martin6bd08122012-03-22 14:54:01 +0100888 return ret;
889 }
890 }
891
892 /* enable DMA module */
Javier Martincd5cf9d2012-03-22 14:54:12 +0100893 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
Javier Martin6bd08122012-03-22 14:54:01 +0100894
895 /* clear all interrupts */
Javier Martincd5cf9d2012-03-22 14:54:12 +0100896 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
Javier Martin6bd08122012-03-22 14:54:01 +0100897
898 /* disable interrupts */
Javier Martincd5cf9d2012-03-22 14:54:12 +0100899 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200900
901 INIT_LIST_HEAD(&imxdma->dma_device.channels);
902
Sascha Hauerf8a356f2011-01-31 11:35:59 +0100903 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
904 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
Javier Martin6c05f092012-02-28 17:08:17 +0100905 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
Sascha Hauerf8a356f2011-01-31 11:35:59 +0100906
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200907 /* Initialize channel parameters */
Javier Martin6bd08122012-03-22 14:54:01 +0100908 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200909 struct imxdma_channel *imxdmac = &imxdma->channel[i];
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100910
Javier Martin6bd08122012-03-22 14:54:01 +0100911 if (cpu_is_mx21() || cpu_is_mx27()) {
912 ret = request_irq(MX2x_INT_DMACH0 + i,
913 dma_irq_handler, 0, "DMA", imxdma);
914 if (ret) {
Javier Martinf9b283a2012-03-22 14:54:13 +0100915 dev_warn(imxdma->dev, "Can't register IRQ %d "
916 "for DMA channel %d\n",
917 MX2x_INT_DMACH0 + i, i);
Javier Martin6bd08122012-03-22 14:54:01 +0100918 goto err_init;
919 }
Javier Martin2d9c2fc2012-03-22 14:54:10 +0100920 init_timer(&imxdmac->watchdog);
921 imxdmac->watchdog.function = &imxdma_watchdog;
922 imxdmac->watchdog.data = (unsigned long)imxdmac;
Sascha Hauer8267f162010-10-20 08:37:19 +0200923 }
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200924
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200925 imxdmac->imxdma = imxdma;
926 spin_lock_init(&imxdmac->lock);
927
Javier Martin9e15db72012-03-02 09:28:47 +0100928 INIT_LIST_HEAD(&imxdmac->ld_queue);
929 INIT_LIST_HEAD(&imxdmac->ld_free);
930 INIT_LIST_HEAD(&imxdmac->ld_active);
931
932 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
933 (unsigned long)imxdmac);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200934 imxdmac->chan.device = &imxdma->dma_device;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +0000935 dma_cookie_init(&imxdmac->chan);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200936 imxdmac->channel = i;
937
938 /* Add the channel to the DMAC list */
Javier Martin9e15db72012-03-02 09:28:47 +0100939 list_add_tail(&imxdmac->chan.device_node,
940 &imxdma->dma_device.channels);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200941 }
942
943 imxdma->dev = &pdev->dev;
944 imxdma->dma_device.dev = &pdev->dev;
945
946 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
947 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
948 imxdma->dma_device.device_tx_status = imxdma_tx_status;
949 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
950 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
Javier Martin6c05f092012-02-28 17:08:17 +0100951 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200952 imxdma->dma_device.device_control = imxdma_control;
953 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
954
955 platform_set_drvdata(pdev, imxdma);
956
Javier Martin6c05f092012-02-28 17:08:17 +0100957 imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
Sascha Hauer1e070a62011-01-12 13:14:37 +0100958 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
959 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
960
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200961 ret = dma_async_device_register(&imxdma->dma_device);
962 if (ret) {
963 dev_err(&pdev->dev, "unable to register\n");
964 goto err_init;
965 }
966
967 return 0;
968
969err_init:
Javier Martin6bd08122012-03-22 14:54:01 +0100970
971 if (cpu_is_mx21() || cpu_is_mx27()) {
972 while (--i >= 0)
973 free_irq(MX2x_INT_DMACH0 + i, NULL);
974 } else if cpu_is_mx1() {
975 free_irq(MX1_DMA_INT, NULL);
976 free_irq(MX1_DMA_ERR, NULL);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200977 }
978
979 kfree(imxdma);
980 return ret;
981}
982
983static int __exit imxdma_remove(struct platform_device *pdev)
984{
985 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
986 int i;
987
988 dma_async_device_unregister(&imxdma->dma_device);
989
Javier Martin6bd08122012-03-22 14:54:01 +0100990 if (cpu_is_mx21() || cpu_is_mx27()) {
991 for (i = 0; i < IMX_DMA_CHANNELS; i++)
992 free_irq(MX2x_INT_DMACH0 + i, NULL);
993 } else if cpu_is_mx1() {
994 free_irq(MX1_DMA_INT, NULL);
995 free_irq(MX1_DMA_ERR, NULL);
Sascha Hauer1f1846c2010-10-06 10:25:55 +0200996 }
997
998 kfree(imxdma);
999
1000 return 0;
1001}
1002
1003static struct platform_driver imxdma_driver = {
1004 .driver = {
1005 .name = "imx-dma",
1006 },
1007 .remove = __exit_p(imxdma_remove),
1008};
1009
1010static int __init imxdma_module_init(void)
1011{
1012 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1013}
1014subsys_initcall(imxdma_module_init);
1015
1016MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1017MODULE_DESCRIPTION("i.MX dma driver");
1018MODULE_LICENSE("GPL");