blob: a2c8e76a46f796186bcbd8d6d5b7e024197d06e0 [file] [log] [blame]
Umang Chheda599b0962020-01-20 17:15:54 +05301/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
Fenglin Wu22e4cf12018-08-01 15:07:28 +080013#include <linux/debugfs.h>
Fenglin Wu3840f8e2018-04-27 13:48:43 +080014#include <linux/device.h>
15#include <linux/err.h>
Fenglin Wu22e4cf12018-08-01 15:07:28 +080016#include <linux/fs.h>
Fenglin Wu30f10b22018-06-15 07:49:23 +080017#include <linux/hrtimer.h>
Fenglin Wu3840f8e2018-04-27 13:48:43 +080018#include <linux/init.h>
19#include <linux/input.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/platform_device.h>
26#include <linux/pwm.h>
Umang Chheda599b0962020-01-20 17:15:54 +053027#include <linux/qpnp/qpnp-misc.h>
Fenglin Wu3840f8e2018-04-27 13:48:43 +080028#include <linux/regmap.h>
29#include <linux/regulator/consumer.h>
Fenglin Wu22e4cf12018-08-01 15:07:28 +080030#include <linux/slab.h>
Fenglin Wu3840f8e2018-04-27 13:48:43 +080031#include <linux/types.h>
Fenglin Wu22e4cf12018-08-01 15:07:28 +080032#include <linux/uaccess.h>
Fenglin Wu3840f8e2018-04-27 13:48:43 +080033
34enum actutor_type {
35 ACT_LRA,
36 ACT_ERM,
37};
38
39enum lra_res_sig_shape {
40 RES_SIG_SINE,
41 RES_SIG_SQUARE,
42};
43
44enum lra_auto_res_mode {
45 AUTO_RES_MODE_ZXD,
46 AUTO_RES_MODE_QWD,
47};
48
49enum wf_src {
50 INT_WF_VMAX,
51 INT_WF_BUFFER,
52 EXT_WF_AUDIO,
53 EXT_WF_PWM,
54};
55
56enum haptics_custom_effect_param {
57 CUSTOM_DATA_EFFECT_IDX,
58 CUSTOM_DATA_TIMEOUT_SEC_IDX,
59 CUSTOM_DATA_TIMEOUT_MSEC_IDX,
60 CUSTOM_DATA_LEN,
61};
62
63/* common definitions */
64#define HAP_BRAKE_PATTERN_MAX 4
65#define HAP_WAVEFORM_BUFFER_MAX 8
66#define HAP_VMAX_MV_DEFAULT 1800
67#define HAP_VMAX_MV_MAX 3596
68#define HAP_ILIM_MA_DEFAULT 400
69#define HAP_ILIM_MA_MAX 800
70#define HAP_PLAY_RATE_US_DEFAULT 5715
71#define HAP_PLAY_RATE_US_MAX 20475
72#define HAP_PLAY_RATE_US_LSB 5
73#define VMAX_MIN_PLAY_TIME_US 20000
74#define HAP_SC_DET_MAX_COUNT 5
75#define HAP_SC_DET_TIME_US 1000000
76#define FF_EFFECT_COUNT_MAX 32
Fenglin Wu802427a2018-08-31 16:07:59 +080077#define HAP_DISABLE_DELAY_USEC 1000
Fenglin Wu3840f8e2018-04-27 13:48:43 +080078
79/* haptics module register definitions */
80#define REG_HAP_STATUS1 0x0A
81#define HAP_SC_DET_BIT BIT(3)
82#define HAP_BUSY_BIT BIT(1)
83
84#define REG_HAP_EN_CTL1 0x46
85#define HAP_EN_BIT BIT(7)
86
87#define REG_HAP_EN_CTL2 0x48
88#define HAP_AUTO_STANDBY_EN_BIT BIT(1)
89#define HAP_BRAKE_EN_BIT BIT(0)
90
91#define REG_HAP_EN_CTL3 0x4A
92#define HAP_HBRIDGE_EN_BIT BIT(7)
93#define HAP_PWM_SIGNAL_EN_BIT BIT(6)
94#define HAP_ILIM_EN_BIT BIT(5)
95#define HAP_ILIM_CC_EN_BIT BIT(4)
96#define HAP_AUTO_RES_RBIAS_EN_BIT BIT(3)
97#define HAP_DAC_EN_BIT BIT(2)
98#define HAP_ZX_HYST_EN_BIT BIT(1)
99#define HAP_PWM_CTL_EN_BIT BIT(0)
100
101#define REG_HAP_AUTO_RES_CTRL 0x4B
102#define HAP_AUTO_RES_EN_BIT BIT(7)
103#define HAP_SEL_AUTO_RES_PERIOD BIT(6)
104#define HAP_AUTO_RES_CNT_ERR_DELTA_MASK GENMASK(5, 4)
105#define HAP_AUTO_RES_CNT_ERR_DELTA_SHIFT 4
106#define HAP_AUTO_RES_ERR_RECOVERY_BIT BIT(3)
107#define HAP_AUTO_RES_EN_DLY_MASK GENMASK(2, 0)
108#define AUTO_RES_CNT_ERR_DELTA(x) (x << HAP_AUTO_RES_CNT_ERR_DELTA_SHIFT)
109#define AUTO_RES_EN_DLY(x) x
110
111#define REG_HAP_CFG1 0x4C
112#define REG_HAP_CFG2 0x4D
113#define HAP_LRA_RES_TYPE_BIT BIT(0)
114
115#define REG_HAP_SEL 0x4E
116#define HAP_WF_SOURCE_MASK GENMASK(5, 4)
117#define HAP_WF_SOURCE_SHIFT 4
118#define HAP_WF_TRIGGER_BIT BIT(0)
119#define HAP_WF_SOURCE_VMAX (0 << HAP_WF_SOURCE_SHIFT)
120#define HAP_WF_SOURCE_BUFFER (1 << HAP_WF_SOURCE_SHIFT)
121#define HAP_WF_SOURCE_AUDIO (2 << HAP_WF_SOURCE_SHIFT)
122#define HAP_WF_SOURCE_PWM (3 << HAP_WF_SOURCE_SHIFT)
123
124#define REG_HAP_AUTO_RES_CFG 0x4F
125#define HAP_AUTO_RES_MODE_BIT BIT(7)
126#define HAP_AUTO_RES_MODE_SHIFT 7
127#define HAP_AUTO_RES_CAL_DURATON_MASK GENMASK(6, 5)
128#define HAP_CAL_EOP_EN_BIT BIT(3)
129#define HAP_CAL_PERIOD_MASK GENMASK(2, 0)
130#define HAP_CAL_OPT3_EVERY_8_PERIOD 2
131
132#define REG_HAP_SLEW_CFG 0x50
133#define REG_HAP_VMAX_CFG 0x51
134#define HAP_VMAX_SIGN_BIT BIT(7)
135#define HAP_VMAX_OVD_BIT BIT(6)
136#define HAP_VMAX_MV_MASK GENMASK(5, 1)
137#define HAP_VMAX_MV_SHIFT 1
138#define HAP_VMAX_MV_LSB 116
139
140#define REG_HAP_ILIM_CFG 0x52
141#define REG_HAP_SC_DEB_CFG 0x53
142#define REG_HAP_RATE_CFG1 0x54
143#define REG_HAP_RATE_CFG2 0x55
144#define REG_HAP_INTERNAL_PWM 0x56
145#define REG_HAP_EXTERNAL_PWM 0x57
146#define REG_HAP_PWM 0x58
147
148#define REG_HAP_SC_CLR 0x59
149#define HAP_SC_CLR_BIT BIT(0)
150
151#define REG_HAP_ZX_CFG 0x5A
152#define HAP_ZX_DET_DEB_MASK GENMASK(2, 0)
153#define ZX_DET_DEB_10US 0
154#define ZX_DET_DEB_20US 1
155#define ZX_DET_DEB_40US 2
156#define ZX_DET_DEB_80US 3
157
158#define REG_HAP_BRAKE 0x5C
159#define HAP_BRAKE_PATTERN_MASK 0x3
160#define HAP_BRAKE_PATTERN_SHIFT 2
161
162#define REG_HAP_WF_REPEAT 0x5E
163#define HAP_WF_REPEAT_MASK GENMASK(6, 4)
164#define HAP_WF_REPEAT_SHIFT 4
165#define HAP_WF_S_REPEAT_MASK GENMASK(1, 0)
166
167#define REG_HAP_WF_S1 0x60
168#define HAP_WF_SIGN_BIT BIT(7)
169#define HAP_WF_OVD_BIT BIT(6)
170#define HAP_WF_AMP_BIT GENMASK(5, 1)
171#define HAP_WF_AMP_SHIFT 1
172
173#define REG_HAP_PLAY 0x70
174#define HAP_PLAY_BIT BIT(7)
175
176#define REG_HAP_SEC_ACCESS 0xD0
Umang Chheda599b0962020-01-20 17:15:54 +0530177#define REG_HAP_PERPH_RESET_CTL3 0xDA
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800178
179struct qti_hap_effect {
180 int id;
181 u8 *pattern;
182 int pattern_length;
183 u16 play_rate_us;
Fenglin Wu659c0042018-07-18 11:02:43 +0800184 u16 vmax_mv;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800185 u8 wf_repeat_n;
186 u8 wf_s_repeat_n;
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800187 u8 brake[HAP_BRAKE_PATTERN_MAX];
188 int brake_pattern_length;
189 bool brake_en;
190 bool lra_auto_res_disable;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800191};
192
193struct qti_hap_play_info {
194 struct qti_hap_effect *effect;
195 u16 vmax_mv;
196 int length_us;
197 int playing_pos;
198 bool playing_pattern;
199};
200
201struct qti_hap_config {
202 enum actutor_type act_type;
203 enum lra_res_sig_shape lra_shape;
204 enum lra_auto_res_mode lra_auto_res_mode;
205 enum wf_src ext_src;
206 u16 vmax_mv;
207 u16 ilim_ma;
208 u16 play_rate_us;
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800209 bool lra_allow_variable_play_rate;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800210 bool use_ext_wf_src;
211};
212
213struct qti_hap_chip {
214 struct platform_device *pdev;
215 struct device *dev;
216 struct regmap *regmap;
217 struct input_dev *input_dev;
218 struct pwm_device *pwm_dev;
219 struct qti_hap_config config;
220 struct qti_hap_play_info play;
221 struct qti_hap_effect *predefined;
222 struct qti_hap_effect constant;
223 struct regulator *vdd_supply;
Fenglin Wu30f10b22018-06-15 07:49:23 +0800224 struct hrtimer stop_timer;
Fenglin Wu802427a2018-08-31 16:07:59 +0800225 struct hrtimer hap_disable_timer;
Fenglin Wu22e4cf12018-08-01 15:07:28 +0800226 struct dentry *hap_debugfs;
Umang Chheda599b0962020-01-20 17:15:54 +0530227 struct notifier_block twm_nb;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800228 spinlock_t bus_lock;
229 ktime_t last_sc_time;
230 int play_irq;
231 int sc_irq;
232 int effects_count;
233 int sc_det_count;
234 u16 reg_base;
235 bool perm_disable;
236 bool play_irq_en;
237 bool vdd_enabled;
Umang Chheda599b0962020-01-20 17:15:54 +0530238 bool twm_state;
239 bool haptics_ext_pin_twm;
240};
241
242struct hap_addr_val {
243 u16 addr;
244 u8 value;
245};
246
247static struct hap_addr_val twm_ext_cfg[] = {
248 {REG_HAP_PLAY, 0x00}, /* Stop playing haptics waveform */
249 {REG_HAP_PERPH_RESET_CTL3, 0x0D}, /* Disable SHUTDOWN1_RB reset */
250 {REG_HAP_SEL, 0x01}, /* Configure for external-pin mode */
251 {REG_HAP_EN_CTL1, 0x80}, /* Enable haptics driver */
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800252};
253
254static int wf_repeat[8] = {1, 2, 4, 8, 16, 32, 64, 128};
255static int wf_s_repeat[4] = {1, 2, 4, 8};
256
Anirudh Ghayal760e91d2020-04-13 15:33:39 +0530257static int twm_sys_enable;
258module_param_named(
259 haptics_twm, twm_sys_enable, int, 0600
260);
261
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800262static inline bool is_secure(u8 addr)
263{
264 return ((addr & 0xFF) > 0xD0);
265}
266
267static int qti_haptics_read(struct qti_hap_chip *chip,
268 u8 addr, u8 *val, int len)
269{
270 int rc = 0;
271 unsigned long flags;
272
273 spin_lock_irqsave(&chip->bus_lock, flags);
274
275 rc = regmap_bulk_read(chip->regmap, chip->reg_base + addr, val, len);
276 if (rc < 0)
277 dev_err(chip->dev, "Reading addr 0x%x failed, rc=%d\n",
278 addr, rc);
279 spin_unlock_irqrestore(&chip->bus_lock, flags);
280
281 return rc;
282}
283
284static int qti_haptics_write(struct qti_hap_chip *chip,
285 u8 addr, u8 *val, int len)
286{
287 int rc = 0, i;
288 unsigned long flags;
289
290 spin_lock_irqsave(&chip->bus_lock, flags);
291 if (is_secure(addr)) {
292 for (i = 0; i < len; i++) {
293 rc = regmap_write(chip->regmap,
294 chip->reg_base + REG_HAP_SEC_ACCESS,
295 0xA5);
296 if (rc < 0) {
297 dev_err(chip->dev, "write SEC_ACCESS failed, rc=%d\n",
298 rc);
299 goto unlock;
300 }
301
302 rc = regmap_write(chip->regmap,
303 chip->reg_base + addr + i, val[i]);
304 if (rc < 0) {
305 dev_err(chip->dev, "write val 0x%x to addr 0x%x failed, rc=%d\n",
306 val[i], addr + i, rc);
307 goto unlock;
308 }
309 }
310 } else {
311 if (len > 1)
312 rc = regmap_bulk_write(chip->regmap,
313 chip->reg_base + addr, val, len);
314 else
315 rc = regmap_write(chip->regmap,
316 chip->reg_base + addr, *val);
317
318 if (rc < 0)
319 dev_err(chip->dev, "write addr 0x%x failed, rc=%d\n",
320 addr, rc);
321 }
322
323 for (i = 0; i < len; i++)
324 dev_dbg(chip->dev, "Update addr 0x%x to val 0x%x\n",
325 addr + i, val[i]);
326
327unlock:
328 spin_unlock_irqrestore(&chip->bus_lock, flags);
329 return rc;
330}
331
332static int qti_haptics_masked_write(struct qti_hap_chip *chip, u8 addr,
333 u8 mask, u8 val)
334{
335 int rc;
336 unsigned long flags;
337
338 spin_lock_irqsave(&chip->bus_lock, flags);
339 if (is_secure(addr)) {
340 rc = regmap_write(chip->regmap,
341 chip->reg_base + REG_HAP_SEC_ACCESS,
342 0xA5);
343 if (rc < 0) {
344 dev_err(chip->dev, "write SEC_ACCESS failed, rc=%d\n",
345 rc);
346 goto unlock;
347 }
348 }
349
350 rc = regmap_update_bits(chip->regmap, chip->reg_base + addr, mask, val);
351 if (rc < 0)
352 dev_err(chip->dev, "Update addr 0x%x to val 0x%x with mask 0x%x failed, rc=%d\n",
353 addr, val, mask, rc);
354
355 dev_dbg(chip->dev, "Update addr 0x%x to val 0x%x with mask 0x%x\n",
356 addr, val, mask);
357unlock:
358 spin_unlock_irqrestore(&chip->bus_lock, flags);
359
360 return rc;
361}
362
363static void construct_constant_waveform_in_pattern(
364 struct qti_hap_play_info *play)
365{
366 struct qti_hap_chip *chip = container_of(play,
367 struct qti_hap_chip, play);
368 struct qti_hap_config *config = &chip->config;
369 struct qti_hap_effect *effect = play->effect;
370 int total_samples, samples, left, magnitude, i, j, k;
371 int delta = INT_MAX, delta_min = INT_MAX;
372
373 /* Using play_rate_us in config for constant waveform */
374 effect->play_rate_us = config->play_rate_us;
375 total_samples = play->length_us / effect->play_rate_us;
376 left = play->length_us % effect->play_rate_us;
377
378 if (total_samples <= HAP_WAVEFORM_BUFFER_MAX) {
379 effect->pattern_length = total_samples;
380 effect->wf_s_repeat_n = 0;
381 effect->wf_repeat_n = 0;
382 } else {
383 /*
384 * Find a closest setting to achieve the constant waveform
385 * with the required length by using buffer waveform source:
386 * play_length_us = pattern_length * wf_s_repeat_n
387 * * wf_repeat_n * play_rate_us
388 */
389 for (i = 0; i < ARRAY_SIZE(wf_repeat); i++) {
390 for (j = 0; j < ARRAY_SIZE(wf_s_repeat); j++) {
391 for (k = 1; k <= HAP_WAVEFORM_BUFFER_MAX; k++) {
392 samples = k * wf_s_repeat[j] *
393 wf_repeat[i];
394 delta = abs(total_samples - samples);
395 if (delta < delta_min) {
396 delta_min = delta;
397 effect->pattern_length = k;
398 effect->wf_s_repeat_n = j;
399 effect->wf_repeat_n = i;
400 }
401 if (samples > total_samples)
402 break;
403 }
404 }
405 }
406 }
407
408 if (left > 0 && effect->pattern_length < HAP_WAVEFORM_BUFFER_MAX)
409 effect->pattern_length++;
410
411 play->length_us = effect->pattern_length * effect->play_rate_us;
412 dev_dbg(chip->dev, "total_samples = %d, pattern_length = %d, wf_s_repeat = %d, wf_repeat = %d\n",
413 total_samples, effect->pattern_length,
414 wf_s_repeat[effect->wf_s_repeat_n],
415 wf_repeat[effect->wf_repeat_n]);
416
417 for (i = 0; i < effect->pattern_length; i++) {
418 magnitude = play->vmax_mv / HAP_VMAX_MV_LSB;
419 effect->pattern[i] = (u8)magnitude << HAP_WF_AMP_SHIFT;
420 }
421}
422
423static int qti_haptics_config_wf_buffer(struct qti_hap_chip *chip)
424{
425 struct qti_hap_play_info *play = &chip->play;
426 struct qti_hap_effect *effect = play->effect;
427 u8 addr, pattern[HAP_WAVEFORM_BUFFER_MAX] = {0};
428 int rc = 0;
429 size_t len;
430
431 if (play->playing_pos == effect->pattern_length) {
432 dev_dbg(chip->dev, "pattern playing done\n");
433 return 0;
434 }
435
436 if (effect->pattern_length - play->playing_pos
437 >= HAP_WAVEFORM_BUFFER_MAX)
438 len = HAP_WAVEFORM_BUFFER_MAX;
439 else
440 len = effect->pattern_length - play->playing_pos;
441
442 dev_dbg(chip->dev, "copy %d bytes start from %d\n",
443 (int)len, play->playing_pos);
444 memcpy(pattern, &effect->pattern[play->playing_pos], len);
445
446 play->playing_pos += len;
447
448 addr = REG_HAP_WF_S1;
449 rc = qti_haptics_write(chip, REG_HAP_WF_S1, pattern,
450 HAP_WAVEFORM_BUFFER_MAX);
451 if (rc < 0)
452 dev_err(chip->dev, "Program WF_SAMPLE failed, rc=%d\n", rc);
453
454 return rc;
455}
456
457static int qti_haptics_config_wf_repeat(struct qti_hap_chip *chip)
458{
459 struct qti_hap_effect *effect = chip->play.effect;
460 u8 addr, mask, val;
461 int rc = 0;
462
463 addr = REG_HAP_WF_REPEAT;
464 mask = HAP_WF_REPEAT_MASK | HAP_WF_S_REPEAT_MASK;
465 val = effect->wf_repeat_n << HAP_WF_REPEAT_SHIFT;
466 val |= effect->wf_s_repeat_n;
467 rc = qti_haptics_masked_write(chip, addr, mask, val);
468 if (rc < 0)
469 dev_err(chip->dev, "Program WF_REPEAT failed, rc=%d\n", rc);
470
471 return rc;
472}
473
474static int qti_haptics_play(struct qti_hap_chip *chip, bool play)
475{
476 int rc = 0;
477 u8 val = play ? HAP_PLAY_BIT : 0;
478
479 rc = qti_haptics_write(chip,
480 REG_HAP_PLAY, &val, 1);
481 if (rc < 0)
482 dev_err(chip->dev, "%s playing haptics failed, rc=%d\n",
483 play ? "start" : "stop", rc);
484
485 return rc;
486}
487
488static int qti_haptics_module_en(struct qti_hap_chip *chip, bool en)
489{
490 int rc = 0;
491 u8 val = en ? HAP_EN_BIT : 0;
492
493 rc = qti_haptics_write(chip,
494 REG_HAP_EN_CTL1, &val, 1);
495 if (rc < 0)
496 dev_err(chip->dev, "%s haptics failed, rc=%d\n",
497 en ? "enable" : "disable", rc);
498
499
500 return rc;
501}
502
503static int qti_haptics_config_vmax(struct qti_hap_chip *chip, int vmax_mv)
504{
505 u8 addr, mask, val;
506 int rc;
507
508 addr = REG_HAP_VMAX_CFG;
509 mask = HAP_VMAX_MV_MASK;
510 val = (vmax_mv / HAP_VMAX_MV_LSB) << HAP_VMAX_MV_SHIFT;
511 rc = qti_haptics_masked_write(chip, addr, mask, val);
512 if (rc < 0)
513 dev_err(chip->dev, "write VMAX_CFG failed, rc=%d\n",
514 rc);
515
516 return rc;
517}
518
519static int qti_haptics_config_wf_src(struct qti_hap_chip *chip,
520 enum wf_src src)
521{
522 u8 addr, mask, val = 0;
523 int rc;
524
525 addr = REG_HAP_SEL;
526 mask = HAP_WF_SOURCE_MASK | HAP_WF_TRIGGER_BIT;
527 val = src << HAP_WF_SOURCE_SHIFT;
528 if (src == EXT_WF_AUDIO || src == EXT_WF_PWM)
529 val |= HAP_WF_TRIGGER_BIT;
530
531 rc = qti_haptics_masked_write(chip, addr, mask, val);
532 if (rc < 0)
533 dev_err(chip->dev, "set HAP_SEL failed, rc=%d\n", rc);
534
535 return rc;
536}
537
538static int qti_haptics_config_play_rate_us(struct qti_hap_chip *chip,
539 int play_rate_us)
540{
541 u8 addr, val[2];
542 int tmp, rc;
543
544 addr = REG_HAP_RATE_CFG1;
545 tmp = play_rate_us / HAP_PLAY_RATE_US_LSB;
546 val[0] = tmp & 0xff;
547 val[1] = (tmp >> 8) & 0xf;
548 rc = qti_haptics_write(chip, addr, val, 2);
549 if (rc < 0)
550 dev_err(chip->dev, "write play_rate failed, rc=%d\n", rc);
551
552 return rc;
553}
554
Fenglin Wu802427a2018-08-31 16:07:59 +0800555static int qti_haptics_brake_enable(struct qti_hap_chip *chip, bool en)
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800556{
557 u8 addr, mask, val;
Fenglin Wu802427a2018-08-31 16:07:59 +0800558 int rc;
559
560 addr = REG_HAP_EN_CTL2;
561 mask = HAP_BRAKE_EN_BIT;
562 val = en ? HAP_BRAKE_EN_BIT : 0;
563 rc = qti_haptics_masked_write(chip, addr, mask, val);
564 if (rc < 0)
565 dev_err(chip->dev, "write BRAKE_EN failed, rc=%d\n", rc);
566
567 return rc;
568}
569
570static int qti_haptics_config_brake(struct qti_hap_chip *chip, u8 *brake)
571{
572 u8 addr, val;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800573 int i, rc;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800574
575 addr = REG_HAP_BRAKE;
576 for (val = 0, i = 0; i < HAP_BRAKE_PATTERN_MAX; i++)
577 val |= (brake[i] & HAP_BRAKE_PATTERN_MASK) <<
578 i * HAP_BRAKE_PATTERN_SHIFT;
579
580 rc = qti_haptics_write(chip, addr, &val, 1);
581 if (rc < 0) {
582 dev_err(chip->dev, "write brake pattern failed, rc=%d\n", rc);
583 return rc;
584 }
Fenglin Wuf3907c82018-07-27 09:06:32 +0800585 /*
586 * Set BRAKE_EN regardless of the brake pattern, this helps to stop
587 * playing immediately once the valid values in WF_Sx are played.
588 */
Fenglin Wu802427a2018-08-31 16:07:59 +0800589 rc = qti_haptics_brake_enable(chip, true);
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800590
591 return rc;
592}
593
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800594static int qti_haptics_lra_auto_res_enable(struct qti_hap_chip *chip, bool en)
595{
596 int rc;
597 u8 addr, val, mask;
598
599 addr = REG_HAP_AUTO_RES_CTRL;
600 mask = HAP_AUTO_RES_EN_BIT;
601 val = en ? HAP_AUTO_RES_EN_BIT : 0;
602 rc = qti_haptics_masked_write(chip, addr, mask, val);
603 if (rc < 0)
604 dev_err(chip->dev, "set AUTO_RES_CTRL failed, rc=%d\n", rc);
605
606 return rc;
607}
608
Fenglin Wu802427a2018-08-31 16:07:59 +0800609#define HAP_CLEAR_PLAYING_RATE_US 15
610static int qti_haptics_clear_settings(struct qti_hap_chip *chip)
611{
612 int rc;
613 u8 pattern[HAP_WAVEFORM_BUFFER_MAX] = {1, 0, 0, 0, 0, 0, 0, 0};
614
615 rc = qti_haptics_brake_enable(chip, false);
616 if (rc < 0)
617 return rc;
618
619 rc = qti_haptics_lra_auto_res_enable(chip, false);
620 if (rc < 0)
621 return rc;
622
623 rc = qti_haptics_config_play_rate_us(chip, HAP_CLEAR_PLAYING_RATE_US);
624 if (rc < 0)
625 return rc;
626
627 rc = qti_haptics_write(chip, REG_HAP_WF_S1, pattern,
628 HAP_WAVEFORM_BUFFER_MAX);
629 if (rc < 0)
630 return rc;
631
632 rc = qti_haptics_play(chip, true);
633 if (rc < 0)
634 return rc;
635
636 rc = qti_haptics_play(chip, false);
637 if (rc < 0)
638 return rc;
639
640 return 0;
641}
642
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800643static int qti_haptics_load_constant_waveform(struct qti_hap_chip *chip)
644{
645 struct qti_hap_play_info *play = &chip->play;
646 struct qti_hap_config *config = &chip->config;
647 int rc = 0;
648
Fenglin Wuf3907c82018-07-27 09:06:32 +0800649 rc = qti_haptics_config_play_rate_us(chip, config->play_rate_us);
650 if (rc < 0)
651 return rc;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800652 /*
653 * Using VMAX waveform source if playing length is >= 20ms,
654 * otherwise using buffer waveform source and calculate the
655 * pattern length and repeating times to achieve accurate
656 * playing time accuracy.
657 */
658 if (play->length_us >= VMAX_MIN_PLAY_TIME_US) {
659 rc = qti_haptics_config_vmax(chip, play->vmax_mv);
660 if (rc < 0)
661 return rc;
662
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800663 /* Enable Auto-Resonance when VMAX wf-src is selected */
664 if (config->act_type == ACT_LRA) {
665 rc = qti_haptics_lra_auto_res_enable(chip, true);
666 if (rc < 0)
667 return rc;
668 }
669
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800670 /* Set WF_SOURCE to VMAX */
671 rc = qti_haptics_config_wf_src(chip, INT_WF_VMAX);
672 if (rc < 0)
673 return rc;
674
675 play->playing_pattern = false;
Fenglin Wu802427a2018-08-31 16:07:59 +0800676 play->effect = NULL;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800677 } else {
678 rc = qti_haptics_config_vmax(chip, config->vmax_mv);
679 if (rc < 0)
680 return rc;
681
682 play->effect = &chip->constant;
683 play->playing_pos = 0;
684 /* Format and config waveform in patterns */
685 construct_constant_waveform_in_pattern(play);
686 rc = qti_haptics_config_wf_buffer(chip);
687 if (rc < 0)
688 return rc;
689
690 rc = qti_haptics_config_wf_repeat(chip);
691 if (rc < 0)
692 return rc;
693
694 /* Set WF_SOURCE to buffer */
695 rc = qti_haptics_config_wf_src(chip, INT_WF_BUFFER);
696 if (rc < 0)
697 return rc;
698
699 play->playing_pattern = true;
700 }
701
702 return 0;
703}
704
705static int qti_haptics_load_predefined_effect(struct qti_hap_chip *chip,
706 int effect_idx)
707{
708 struct qti_hap_play_info *play = &chip->play;
709 struct qti_hap_config *config = &chip->config;
710 int rc = 0;
711
712 if (effect_idx >= chip->effects_count)
713 return -EINVAL;
714
715 play->effect = &chip->predefined[effect_idx];
716 play->playing_pos = 0;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800717 rc = qti_haptics_config_vmax(chip, play->vmax_mv);
718 if (rc < 0)
719 return rc;
720
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800721 rc = qti_haptics_config_play_rate_us(chip, play->effect->play_rate_us);
722 if (rc < 0)
723 return rc;
724
725 if (config->act_type == ACT_LRA) {
726 rc = qti_haptics_lra_auto_res_enable(chip,
727 !play->effect->lra_auto_res_disable);
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800728 if (rc < 0)
729 return rc;
730 }
731
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800732 /* Set brake pattern in the effect */
733 rc = qti_haptics_config_brake(chip, play->effect->brake);
734 if (rc < 0)
735 return rc;
736
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800737 rc = qti_haptics_config_wf_buffer(chip);
738 if (rc < 0)
739 return rc;
740
741 rc = qti_haptics_config_wf_repeat(chip);
742 if (rc < 0)
743 return rc;
744
745 /* Set WF_SOURCE to buffer */
746 rc = qti_haptics_config_wf_src(chip, INT_WF_BUFFER);
747 if (rc < 0)
748 return rc;
749
750 play->playing_pattern = true;
751
752 return 0;
753}
754
755static irqreturn_t qti_haptics_play_irq_handler(int irq, void *data)
756{
757 struct qti_hap_chip *chip = (struct qti_hap_chip *)data;
758 struct qti_hap_play_info *play = &chip->play;
759 struct qti_hap_effect *effect = play->effect;
760 int rc;
761
762 dev_dbg(chip->dev, "play_irq triggered\n");
763 if (play->playing_pos == effect->pattern_length) {
764 dev_dbg(chip->dev, "waveform playing done\n");
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800765 if (chip->play_irq_en) {
766 disable_irq_nosync(chip->play_irq);
767 chip->play_irq_en = false;
768 }
769
770 goto handled;
771 }
772
773 /* Config to play remaining patterns */
774 rc = qti_haptics_config_wf_repeat(chip);
775 if (rc < 0)
776 goto handled;
777
778 rc = qti_haptics_config_wf_buffer(chip);
779 if (rc < 0)
780 goto handled;
781
782handled:
783 return IRQ_HANDLED;
784}
785
786static irqreturn_t qti_haptics_sc_irq_handler(int irq, void *data)
787{
788 struct qti_hap_chip *chip = (struct qti_hap_chip *)data;
789 u8 addr, val;
790 ktime_t temp;
791 s64 sc_delta_time_us;
792 int rc;
793
794 dev_dbg(chip->dev, "sc_irq triggered\n");
795 addr = REG_HAP_STATUS1;
796 rc = qti_haptics_read(chip, addr, &val, 1);
797 if (rc < 0) {
798 dev_err(chip->dev, "read HAP_STATUS1 failed, rc=%d\n", rc);
799 goto handled;
800 }
801
802 if (!(val & HAP_SC_DET_BIT))
803 goto handled;
804
805 temp = ktime_get();
806 sc_delta_time_us = ktime_us_delta(temp, chip->last_sc_time);
807 chip->last_sc_time = temp;
808
809 if (sc_delta_time_us > HAP_SC_DET_TIME_US)
810 chip->sc_det_count = 0;
811 else
812 chip->sc_det_count++;
813
814 addr = REG_HAP_SC_CLR;
815 val = HAP_SC_CLR_BIT;
816 rc = qti_haptics_write(chip, addr, &val, 1);
817 if (rc < 0) {
818 dev_err(chip->dev, "write SC_CLR failed, rc=%d\n", rc);
819 goto handled;
820 }
821
822 if (chip->sc_det_count > HAP_SC_DET_MAX_COUNT) {
823 rc = qti_haptics_module_en(chip, false);
824 if (rc < 0)
825 goto handled;
826
827 dev_crit(chip->dev, "Short circuit persists, disable haptics\n");
828 chip->perm_disable = true;
829 }
830
831handled:
832 return IRQ_HANDLED;
833}
834
835static inline void get_play_length(struct qti_hap_play_info *play,
836 int *length_us)
837{
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800838 struct qti_hap_effect *effect = play->effect;
839 int tmp;
840
841 tmp = effect->pattern_length * effect->play_rate_us;
842 tmp *= wf_s_repeat[effect->wf_s_repeat_n];
843 tmp *= wf_repeat[effect->wf_repeat_n];
Fenglin Wucf1a1b92018-06-11 07:39:44 +0800844 if (effect->brake_en)
845 tmp += effect->play_rate_us * effect->brake_pattern_length;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800846
847 *length_us = tmp;
848}
849
850static int qti_haptics_upload_effect(struct input_dev *dev,
851 struct ff_effect *effect, struct ff_effect *old)
852{
853 struct qti_hap_chip *chip = input_get_drvdata(dev);
854 struct qti_hap_config *config = &chip->config;
855 struct qti_hap_play_info *play = &chip->play;
856 int rc = 0, tmp, i;
857 s16 level, data[CUSTOM_DATA_LEN];
Fenglin Wu802427a2018-08-31 16:07:59 +0800858 ktime_t rem;
859 s64 time_us;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800860
Fenglin Wu802427a2018-08-31 16:07:59 +0800861 if (hrtimer_active(&chip->hap_disable_timer)) {
862 rem = hrtimer_get_remaining(&chip->hap_disable_timer);
863 time_us = ktime_to_us(rem);
864 dev_dbg(chip->dev, "waiting for playing clear sequence: %lld us\n",
865 time_us);
866 usleep_range(time_us, time_us + 100);
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800867 }
868
869 switch (effect->type) {
870 case FF_CONSTANT:
871 play->length_us = effect->replay.length * USEC_PER_MSEC;
872 level = effect->u.constant.level;
873 tmp = level * config->vmax_mv;
874 play->vmax_mv = tmp / 0x7fff;
875 dev_dbg(chip->dev, "upload constant effect, length = %dus, vmax_mv=%d\n",
876 play->length_us, play->vmax_mv);
877
878 rc = qti_haptics_load_constant_waveform(chip);
879 if (rc < 0) {
880 dev_err(chip->dev, "Play constant waveform failed, rc=%d\n",
881 rc);
Fenglin Wu802427a2018-08-31 16:07:59 +0800882 return rc;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800883 }
884 break;
885
886 case FF_PERIODIC:
Fenglin Wu802427a2018-08-31 16:07:59 +0800887 if (chip->effects_count == 0)
888 return -EINVAL;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800889
890 if (effect->u.periodic.waveform != FF_CUSTOM) {
891 dev_err(chip->dev, "Only accept custom waveforms\n");
Fenglin Wu802427a2018-08-31 16:07:59 +0800892 return -EINVAL;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800893 }
894
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800895 if (copy_from_user(data, effect->u.periodic.custom_data,
Fenglin Wu802427a2018-08-31 16:07:59 +0800896 sizeof(s16) * CUSTOM_DATA_LEN))
897 return -EFAULT;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800898
899 for (i = 0; i < chip->effects_count; i++)
900 if (chip->predefined[i].id ==
901 data[CUSTOM_DATA_EFFECT_IDX])
902 break;
903
904 if (i == chip->effects_count) {
905 dev_err(chip->dev, "predefined effect %d is NOT supported\n",
906 data[0]);
Fenglin Wu802427a2018-08-31 16:07:59 +0800907 return -EINVAL;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800908 }
909
Fenglin Wu659c0042018-07-18 11:02:43 +0800910 level = effect->u.periodic.magnitude;
911 tmp = level * chip->predefined[i].vmax_mv;
912 play->vmax_mv = tmp / 0x7fff;
913
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800914 dev_dbg(chip->dev, "upload effect %d, vmax_mv=%d\n",
915 chip->predefined[i].id, play->vmax_mv);
916 rc = qti_haptics_load_predefined_effect(chip, i);
917 if (rc < 0) {
918 dev_err(chip->dev, "Play predefined effect %d failed, rc=%d\n",
919 chip->predefined[i].id, rc);
Fenglin Wu802427a2018-08-31 16:07:59 +0800920 return rc;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800921 }
922
923 get_play_length(play, &play->length_us);
924 data[CUSTOM_DATA_TIMEOUT_SEC_IDX] =
925 play->length_us / USEC_PER_SEC;
926 data[CUSTOM_DATA_TIMEOUT_MSEC_IDX] =
927 (play->length_us % USEC_PER_SEC) / USEC_PER_MSEC;
928
929 /*
930 * Copy the custom data contains the play length back to
931 * userspace so that the userspace client can wait and
932 * send stop playing command after it's done.
933 */
934 if (copy_to_user(effect->u.periodic.custom_data, data,
Fenglin Wu802427a2018-08-31 16:07:59 +0800935 sizeof(s16) * CUSTOM_DATA_LEN))
936 return -EFAULT;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800937 break;
938
939 default:
940 dev_err(chip->dev, "Unsupported effect type: %d\n",
941 effect->type);
Fenglin Wu802427a2018-08-31 16:07:59 +0800942 return -EINVAL;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800943 }
944
Fenglin Wu802427a2018-08-31 16:07:59 +0800945 if (chip->vdd_supply && !chip->vdd_enabled) {
946 rc = regulator_enable(chip->vdd_supply);
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800947 if (rc < 0) {
Fenglin Wu802427a2018-08-31 16:07:59 +0800948 dev_err(chip->dev, "Enable VDD supply failed, rc=%d\n",
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800949 rc);
950 return rc;
951 }
Fenglin Wu802427a2018-08-31 16:07:59 +0800952 chip->vdd_enabled = true;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800953 }
Fenglin Wu802427a2018-08-31 16:07:59 +0800954
955 return 0;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800956}
957
958static int qti_haptics_playback(struct input_dev *dev, int effect_id, int val)
959{
960 struct qti_hap_chip *chip = input_get_drvdata(dev);
961 struct qti_hap_play_info *play = &chip->play;
Fenglin Wu30f10b22018-06-15 07:49:23 +0800962 s64 secs;
963 unsigned long nsecs;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800964 int rc = 0;
965
966 dev_dbg(chip->dev, "playback, val = %d\n", val);
967 if (!!val) {
Fenglin Wu802427a2018-08-31 16:07:59 +0800968 rc = qti_haptics_module_en(chip, true);
969 if (rc < 0)
970 return rc;
971
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800972 rc = qti_haptics_play(chip, true);
973 if (rc < 0)
974 return rc;
975
976 if (play->playing_pattern) {
977 if (!chip->play_irq_en) {
978 enable_irq(chip->play_irq);
979 chip->play_irq_en = true;
980 }
Fenglin Wuf3907c82018-07-27 09:06:32 +0800981 /* Toggle PLAY when playing pattern */
982 rc = qti_haptics_play(chip, false);
983 if (rc < 0)
984 return rc;
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800985 } else {
986 if (chip->play_irq_en) {
987 disable_irq_nosync(chip->play_irq);
988 chip->play_irq_en = false;
989 }
Fenglin Wu30f10b22018-06-15 07:49:23 +0800990 secs = play->length_us / USEC_PER_SEC;
991 nsecs = (play->length_us % USEC_PER_SEC) *
992 NSEC_PER_USEC;
993 hrtimer_start(&chip->stop_timer, ktime_set(secs, nsecs),
994 HRTIMER_MODE_REL);
Fenglin Wu3840f8e2018-04-27 13:48:43 +0800995 }
996 } else {
997 play->length_us = 0;
998 rc = qti_haptics_play(chip, false);
999 if (rc < 0)
1000 return rc;
1001
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001002 if (chip->play_irq_en) {
1003 disable_irq_nosync(chip->play_irq);
1004 chip->play_irq_en = false;
1005 }
1006 }
1007
1008 return rc;
1009}
1010
1011static int qti_haptics_erase(struct input_dev *dev, int effect_id)
1012{
1013 struct qti_hap_chip *chip = input_get_drvdata(dev);
Fenglin Wu802427a2018-08-31 16:07:59 +08001014 int delay_us, rc = 0;
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001015
1016 if (chip->vdd_supply && chip->vdd_enabled) {
1017 rc = regulator_disable(chip->vdd_supply);
1018 if (rc < 0) {
1019 dev_err(chip->dev, "Disable VDD supply failed, rc=%d\n",
1020 rc);
1021 return rc;
1022 }
1023 chip->vdd_enabled = false;
1024 }
1025
Fenglin Wu802427a2018-08-31 16:07:59 +08001026 rc = qti_haptics_clear_settings(chip);
1027 if (rc < 0) {
1028 dev_err(chip->dev, "clear setting failed, rc=%d\n", rc);
1029 return rc;
1030 }
1031
1032 if (chip->play.effect)
1033 delay_us = chip->play.effect->play_rate_us;
1034 else
1035 delay_us = chip->config.play_rate_us;
1036
1037 delay_us += HAP_DISABLE_DELAY_USEC;
1038 hrtimer_start(&chip->hap_disable_timer,
1039 ktime_set(0, delay_us * NSEC_PER_USEC),
1040 HRTIMER_MODE_REL);
1041
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001042 return rc;
1043}
1044
Fenglin Wud92ef742018-07-16 15:50:08 +08001045static void qti_haptics_set_gain(struct input_dev *dev, u16 gain)
1046{
1047 struct qti_hap_chip *chip = input_get_drvdata(dev);
1048 struct qti_hap_config *config = &chip->config;
1049 struct qti_hap_play_info *play = &chip->play;
1050
1051 if (gain == 0)
1052 return;
1053
1054 if (gain > 0x7fff)
1055 gain = 0x7fff;
1056
1057 play->vmax_mv = ((u32)(gain * config->vmax_mv)) / 0x7fff;
1058 qti_haptics_config_vmax(chip, play->vmax_mv);
1059}
1060
Umang Chheda599b0962020-01-20 17:15:54 +05301061static int qti_haptics_twm_config(struct qti_hap_chip *chip)
1062{
1063 int rc, i;
1064
1065 for (i = 0; i < ARRAY_SIZE(twm_ext_cfg); i++) {
1066 rc = qti_haptics_write(chip, twm_ext_cfg[i].addr,
1067 &twm_ext_cfg[i].value, 1);
1068 if (rc < 0) {
1069 dev_err(chip->dev, "Haptics TWM config failed, rc=%d\n",
1070 rc);
1071 return rc;
1072 }
1073 }
1074 pr_debug("Enabled haptics for TWM mode\n");
1075
1076 return 0;
1077}
1078
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001079static int qti_haptics_hw_init(struct qti_hap_chip *chip)
1080{
1081 struct qti_hap_config *config = &chip->config;
1082 u8 addr, val, mask;
1083 int rc = 0;
1084
1085 /* Config actuator type */
1086 addr = REG_HAP_CFG1;
1087 val = config->act_type;
1088 rc = qti_haptics_write(chip, addr, &val, 1);
1089 if (rc < 0) {
1090 dev_err(chip->dev, "write actuator type failed, rc=%d\n", rc);
1091 return rc;
1092 }
1093
1094 /* Config ilim_ma */
1095 addr = REG_HAP_ILIM_CFG;
1096 val = config->ilim_ma == 400 ? 0 : 1;
1097 rc = qti_haptics_write(chip, addr, &val, 1);
1098 if (rc < 0) {
1099 dev_err(chip->dev, "write ilim_ma failed, rc=%d\n", rc);
1100 return rc;
1101 }
1102
1103 /* Set HAP_EN_CTL3 */
1104 addr = REG_HAP_EN_CTL3;
1105 val = HAP_HBRIDGE_EN_BIT | HAP_PWM_SIGNAL_EN_BIT | HAP_ILIM_EN_BIT |
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001106 HAP_ILIM_CC_EN_BIT | HAP_AUTO_RES_RBIAS_EN_BIT |
1107 HAP_DAC_EN_BIT | HAP_PWM_CTL_EN_BIT;
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001108 rc = qti_haptics_write(chip, addr, &val, 1);
1109 if (rc < 0) {
1110 dev_err(chip->dev, "set EN_CTL3 failed, rc=%d\n", rc);
1111 return rc;
1112 }
1113
1114 /* Set ZX_CFG */
1115 addr = REG_HAP_ZX_CFG;
1116 mask = HAP_ZX_DET_DEB_MASK;
1117 val = ZX_DET_DEB_80US;
1118 rc = qti_haptics_masked_write(chip, addr, mask, val);
1119 if (rc < 0) {
1120 dev_err(chip->dev, "write ZX_CFG failed, rc=%d\n", rc);
1121 return rc;
1122 }
1123
1124 /*
1125 * Config play rate: this is the resonance period for LRA,
1126 * or the play duration of each waveform sample for ERM.
1127 */
1128 rc = qti_haptics_config_play_rate_us(chip, config->play_rate_us);
1129 if (rc < 0)
1130 return rc;
1131
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001132 /* Set external waveform source if it's used */
1133 if (config->use_ext_wf_src) {
1134 rc = qti_haptics_config_wf_src(chip, config->ext_src);
1135 if (rc < 0)
1136 return rc;
1137 }
1138
1139 /*
1140 * Skip configurations below for ERM actuator
1141 * as they're only for LRA actuators
1142 */
1143 if (config->act_type == ACT_ERM)
1144 return 0;
1145
1146 addr = REG_HAP_CFG2;
1147 val = config->lra_shape;
1148 rc = qti_haptics_write(chip, addr, &val, 1);
1149 if (rc < 0) {
1150 dev_err(chip->dev, "write lra_sig_shape failed, rc=%d\n", rc);
1151 return rc;
1152 }
1153
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001154 addr = REG_HAP_AUTO_RES_CFG;
1155 mask = HAP_AUTO_RES_MODE_BIT | HAP_CAL_EOP_EN_BIT | HAP_CAL_PERIOD_MASK;
1156 val = config->lra_auto_res_mode << HAP_AUTO_RES_MODE_SHIFT;
1157 val |= HAP_CAL_EOP_EN_BIT | HAP_CAL_OPT3_EVERY_8_PERIOD;
1158 rc = qti_haptics_masked_write(chip, addr, mask, val);
1159 if (rc < 0) {
1160 dev_err(chip->dev, "set AUTO_RES_CFG failed, rc=%d\n", rc);
1161 return rc;
1162 }
1163
1164 addr = REG_HAP_AUTO_RES_CTRL;
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001165 val = HAP_AUTO_RES_EN_BIT | HAP_SEL_AUTO_RES_PERIOD |
1166 AUTO_RES_CNT_ERR_DELTA(2) | HAP_AUTO_RES_ERR_RECOVERY_BIT |
1167 AUTO_RES_EN_DLY(4);
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001168 rc = qti_haptics_write(chip, addr, &val, 1);
1169 if (rc < 0) {
1170 dev_err(chip->dev, "set AUTO_RES_CTRL failed, rc=%d\n",
1171 rc);
1172 return rc;
1173 }
1174
1175 return 0;
1176}
1177
Fenglin Wu30f10b22018-06-15 07:49:23 +08001178static enum hrtimer_restart qti_hap_stop_timer(struct hrtimer *timer)
1179{
1180 struct qti_hap_chip *chip = container_of(timer, struct qti_hap_chip,
1181 stop_timer);
1182 int rc;
1183
1184 chip->play.length_us = 0;
1185 rc = qti_haptics_play(chip, false);
Fenglin Wu802427a2018-08-31 16:07:59 +08001186 if (rc < 0)
Fenglin Wu30f10b22018-06-15 07:49:23 +08001187 dev_err(chip->dev, "Stop playing failed, rc=%d\n", rc);
Fenglin Wu802427a2018-08-31 16:07:59 +08001188
1189 return HRTIMER_NORESTART;
1190}
1191
1192static enum hrtimer_restart qti_hap_disable_timer(struct hrtimer *timer)
1193{
1194 struct qti_hap_chip *chip = container_of(timer, struct qti_hap_chip,
1195 hap_disable_timer);
1196 int rc;
Fenglin Wu30f10b22018-06-15 07:49:23 +08001197
1198 rc = qti_haptics_module_en(chip, false);
1199 if (rc < 0)
Fenglin Wu802427a2018-08-31 16:07:59 +08001200 dev_err(chip->dev, "Disable haptics module failed, rc=%d\n",
1201 rc);
1202
Fenglin Wu30f10b22018-06-15 07:49:23 +08001203 return HRTIMER_NORESTART;
1204}
1205
Fenglin Wu22e4cf12018-08-01 15:07:28 +08001206static void verify_brake_setting(struct qti_hap_effect *effect)
1207{
1208 int i = effect->brake_pattern_length - 1;
1209 u8 val = 0;
1210
1211 for (; i >= 0; i--) {
1212 if (effect->brake[i] != 0)
1213 break;
1214
1215 effect->brake_pattern_length--;
1216 }
1217
1218 for (i = 0; i < effect->brake_pattern_length; i++) {
1219 effect->brake[i] &= HAP_BRAKE_PATTERN_MASK;
1220 val |= effect->brake[i] << (i * HAP_BRAKE_PATTERN_SHIFT);
1221 }
1222
1223 effect->brake_en = (val != 0);
1224}
1225
Umang Chheda599b0962020-01-20 17:15:54 +05301226static int twm_notifier_cb(struct notifier_block *nb,
1227 unsigned long action, void *data)
1228{
1229 struct qti_hap_chip *chip = container_of(nb,
1230 struct qti_hap_chip, twm_nb);
1231
1232 if (action != PMIC_TWM_CLEAR &&
1233 action != PMIC_TWM_ENABLE)
1234 pr_debug("Unsupported option %lu\n", action);
1235 else
1236 chip->twm_state = (u8)action;
1237
1238 return NOTIFY_OK;
1239}
1240
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001241static int qti_haptics_parse_dt(struct qti_hap_chip *chip)
1242{
1243 struct qti_hap_config *config = &chip->config;
1244 const struct device_node *node = chip->dev->of_node;
1245 struct device_node *child_node;
1246 struct qti_hap_effect *effect;
1247 const char *str;
Fenglin Wuf3907c82018-07-27 09:06:32 +08001248 int rc = 0, tmp, i = 0, j, m;
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001249
1250 rc = of_property_read_u32(node, "reg", &tmp);
1251 if (rc < 0) {
1252 dev_err(chip->dev, "Failed to reg base, rc=%d\n", rc);
1253 return rc;
1254 }
1255 chip->reg_base = (u16)tmp;
1256
1257 chip->sc_irq = platform_get_irq_byname(chip->pdev, "hap-sc-irq");
1258 if (chip->sc_irq < 0) {
1259 dev_err(chip->dev, "Failed to get hap-sc-irq\n");
1260 return chip->sc_irq;
1261 }
1262
1263 chip->play_irq = platform_get_irq_byname(chip->pdev, "hap-play-irq");
1264 if (chip->play_irq < 0) {
1265 dev_err(chip->dev, "Failed to get hap-play-irq\n");
1266 return chip->play_irq;
1267 }
1268
1269 config->act_type = ACT_LRA;
1270 rc = of_property_read_string(node, "qcom,actuator-type", &str);
1271 if (!rc) {
1272 if (strcmp(str, "erm") == 0) {
1273 config->act_type = ACT_ERM;
1274 } else if (strcmp(str, "lra") == 0) {
1275 config->act_type = ACT_LRA;
1276 } else {
1277 dev_err(chip->dev, "Invalid actuator type: %s\n",
1278 str);
1279 return -EINVAL;
1280 }
1281 }
1282
1283 config->vmax_mv = HAP_VMAX_MV_DEFAULT;
1284 rc = of_property_read_u32(node, "qcom,vmax-mv", &tmp);
1285 if (!rc)
1286 config->vmax_mv = (tmp > HAP_VMAX_MV_MAX) ?
1287 HAP_VMAX_MV_MAX : tmp;
1288
1289 config->ilim_ma = HAP_ILIM_MA_DEFAULT;
1290 rc = of_property_read_u32(node, "qcom,ilim-ma", &tmp);
1291 if (!rc)
1292 config->ilim_ma = (tmp >= HAP_ILIM_MA_MAX) ?
1293 HAP_ILIM_MA_MAX : HAP_ILIM_MA_DEFAULT;
1294
1295 config->play_rate_us = HAP_PLAY_RATE_US_DEFAULT;
1296 rc = of_property_read_u32(node, "qcom,play-rate-us", &tmp);
1297 if (!rc)
1298 config->play_rate_us = (tmp >= HAP_PLAY_RATE_US_MAX) ?
1299 HAP_PLAY_RATE_US_MAX : tmp;
1300
Umang Chheda599b0962020-01-20 17:15:54 +05301301 chip->haptics_ext_pin_twm = of_property_read_bool(node,
1302 "qcom,haptics-ext-pin-twm");
1303
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001304 if (of_find_property(node, "qcom,external-waveform-source", NULL)) {
1305 if (!of_property_read_string(node,
1306 "qcom,external-waveform-source", &str)) {
1307 if (strcmp(str, "audio") == 0) {
1308 config->ext_src = EXT_WF_AUDIO;
1309 } else if (strcmp(str, "pwm") == 0) {
1310 config->ext_src = EXT_WF_PWM;
1311 } else {
1312 dev_err(chip->dev, "Invalid external waveform source: %s\n",
1313 str);
1314 return -EINVAL;
1315 }
1316 }
1317 config->use_ext_wf_src = true;
1318 }
1319
1320 if (of_find_property(node, "vdd-supply", NULL)) {
1321 chip->vdd_supply = devm_regulator_get(chip->dev, "vdd");
1322 if (IS_ERR(chip->vdd_supply)) {
1323 rc = PTR_ERR(chip->vdd_supply);
1324 if (rc != -EPROBE_DEFER)
1325 dev_err(chip->dev, "Failed to get vdd regulator");
1326 return rc;
1327 }
1328 }
1329
1330 if (config->act_type == ACT_LRA) {
1331 config->lra_shape = RES_SIG_SINE;
1332 rc = of_property_read_string(node,
1333 "qcom,lra-resonance-sig-shape", &str);
1334 if (!rc) {
1335 if (strcmp(str, "sine") == 0) {
1336 config->lra_shape = RES_SIG_SINE;
1337 } else if (strcmp(str, "square") == 0) {
1338 config->lra_shape = RES_SIG_SQUARE;
1339 } else {
1340 dev_err(chip->dev, "Invalid resonance signal shape: %s\n",
1341 str);
1342 return -EINVAL;
1343 }
1344 }
1345
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001346 config->lra_allow_variable_play_rate = of_property_read_bool(
1347 node, "qcom,lra-allow-variable-play-rate");
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001348
1349 config->lra_auto_res_mode = AUTO_RES_MODE_ZXD;
1350 rc = of_property_read_string(node,
1351 "qcom,lra-auto-resonance-mode", &str);
1352 if (!rc) {
1353 if (strcmp(str, "zxd") == 0) {
1354 config->lra_auto_res_mode = AUTO_RES_MODE_ZXD;
1355 } else if (strcmp(str, "qwd") == 0) {
1356 config->lra_auto_res_mode = AUTO_RES_MODE_QWD;
1357 } else {
1358 dev_err(chip->dev, "Invalid auto resonance mode: %s\n",
1359 str);
1360 return -EINVAL;
1361 }
1362 }
1363 }
1364
1365 chip->constant.pattern = devm_kcalloc(chip->dev,
1366 HAP_WAVEFORM_BUFFER_MAX,
1367 sizeof(u8), GFP_KERNEL);
1368 if (!chip->constant.pattern)
1369 return -ENOMEM;
1370
1371 tmp = of_get_available_child_count(node);
1372 if (tmp == 0)
1373 return 0;
1374
1375 chip->predefined = devm_kcalloc(chip->dev, tmp,
1376 sizeof(*chip->predefined), GFP_KERNEL);
1377 if (!chip->predefined)
1378 return -ENOMEM;
1379
1380 chip->effects_count = tmp;
1381
1382 for_each_available_child_of_node(node, child_node) {
1383 effect = &chip->predefined[i++];
1384 rc = of_property_read_u32(child_node, "qcom,effect-id",
1385 &effect->id);
1386 if (rc < 0) {
1387 dev_err(chip->dev, "Read qcom,effect-id failed, rc=%d\n",
1388 rc);
1389 return rc;
1390 }
1391
Fenglin Wu659c0042018-07-18 11:02:43 +08001392 effect->vmax_mv = config->vmax_mv;
1393 rc = of_property_read_u32(child_node, "qcom,wf-vmax-mv", &tmp);
1394 if (rc < 0)
1395 dev_dbg(chip->dev, "Read qcom,wf-vmax-mv failed, rc=%d\n",
1396 rc);
1397 else
1398 effect->vmax_mv = (tmp > HAP_VMAX_MV_MAX) ?
1399 HAP_VMAX_MV_MAX : tmp;
1400
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001401 rc = of_property_count_elems_of_size(child_node,
1402 "qcom,wf-pattern", sizeof(u8));
1403 if (rc < 0) {
1404 dev_err(chip->dev, "Count qcom,wf-pattern property failed, rc=%d\n",
1405 rc);
1406 return rc;
1407 } else if (rc == 0) {
1408 dev_dbg(chip->dev, "qcom,wf-pattern has no data\n");
1409 return -EINVAL;
1410 }
1411
1412 effect->pattern_length = rc;
1413 effect->pattern = devm_kcalloc(chip->dev,
1414 effect->pattern_length, sizeof(u8), GFP_KERNEL);
1415 if (!effect->pattern)
1416 return -ENOMEM;
1417
1418 rc = of_property_read_u8_array(child_node, "qcom,wf-pattern",
1419 effect->pattern, effect->pattern_length);
1420 if (rc < 0) {
1421 dev_err(chip->dev, "Read qcom,wf-pattern property failed, rc=%d\n",
1422 rc);
1423 return rc;
1424 }
1425
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001426 effect->play_rate_us = config->play_rate_us;
1427 rc = of_property_read_u32(child_node, "qcom,wf-play-rate-us",
1428 &tmp);
1429 if (rc < 0)
1430 dev_dbg(chip->dev, "Read qcom,wf-play-rate-us failed, rc=%d\n",
1431 rc);
1432 else
1433 effect->play_rate_us = tmp;
1434
1435 if (config->act_type == ACT_LRA &&
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001436 !config->lra_allow_variable_play_rate &&
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001437 config->play_rate_us != effect->play_rate_us) {
1438 dev_warn(chip->dev, "play rate should match with LRA resonance frequency\n");
1439 effect->play_rate_us = config->play_rate_us;
1440 }
1441
1442 rc = of_property_read_u32(child_node, "qcom,wf-repeat-count",
1443 &tmp);
1444 if (rc < 0) {
1445 dev_dbg(chip->dev, "Read qcom,wf-repeat-count failed, rc=%d\n",
1446 rc);
1447 } else {
1448 for (j = 0; j < ARRAY_SIZE(wf_repeat); j++)
1449 if (tmp <= wf_repeat[j])
1450 break;
1451
1452 effect->wf_repeat_n = j;
1453 }
1454
1455 rc = of_property_read_u32(child_node, "qcom,wf-s-repeat-count",
1456 &tmp);
1457 if (rc < 0) {
1458 dev_dbg(chip->dev, "Read qcom,wf-s-repeat-count failed, rc=%d\n",
1459 rc);
1460 } else {
1461 for (j = 0; j < ARRAY_SIZE(wf_s_repeat); j++)
1462 if (tmp <= wf_s_repeat[j])
1463 break;
1464
1465 effect->wf_s_repeat_n = j;
1466 }
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001467
Fenglin Wuf3907c82018-07-27 09:06:32 +08001468 effect->lra_auto_res_disable = of_property_read_bool(child_node,
Fenglin Wucf1a1b92018-06-11 07:39:44 +08001469 "qcom,lra-auto-resonance-disable");
1470
1471 tmp = of_property_count_elems_of_size(child_node,
1472 "qcom,wf-brake-pattern", sizeof(u8));
1473 if (tmp <= 0)
1474 continue;
1475
1476 if (tmp > HAP_BRAKE_PATTERN_MAX) {
1477 dev_err(chip->dev, "wf-brake-pattern shouldn't be more than %d bytes\n",
1478 HAP_BRAKE_PATTERN_MAX);
1479 return -EINVAL;
1480 }
1481
1482 rc = of_property_read_u8_array(child_node,
1483 "qcom,wf-brake-pattern", effect->brake, tmp);
1484 if (rc < 0) {
1485 dev_err(chip->dev, "Failed to get wf-brake-pattern, rc=%d\n",
1486 rc);
1487 return rc;
1488 }
1489
1490 effect->brake_pattern_length = tmp;
Fenglin Wu22e4cf12018-08-01 15:07:28 +08001491 verify_brake_setting(effect);
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001492 }
1493
Fenglin Wuf3907c82018-07-27 09:06:32 +08001494 for (j = 0; j < i; j++) {
1495 dev_dbg(chip->dev, "effect: %d\n", chip->predefined[j].id);
1496 dev_dbg(chip->dev, " vmax: %d mv\n",
1497 chip->predefined[j].vmax_mv);
1498 dev_dbg(chip->dev, " play_rate: %d us\n",
1499 chip->predefined[j].play_rate_us);
1500 for (m = 0; m < chip->predefined[j].pattern_length; m++)
1501 dev_dbg(chip->dev, " pattern[%d]: 0x%x\n",
1502 m, chip->predefined[j].pattern[m]);
1503 for (m = 0; m < chip->predefined[j].brake_pattern_length; m++)
1504 dev_dbg(chip->dev, " brake_pattern[%d]: 0x%x\n",
1505 m, chip->predefined[j].brake[m]);
1506 dev_dbg(chip->dev, " brake_en: %d\n",
1507 chip->predefined[j].brake_en);
1508 dev_dbg(chip->dev, " wf_repeat_n: %d\n",
1509 chip->predefined[j].wf_repeat_n);
1510 dev_dbg(chip->dev, " wf_s_repeat_n: %d\n",
1511 chip->predefined[j].wf_s_repeat_n);
1512 dev_dbg(chip->dev, " lra_auto_res_disable: %d\n",
1513 chip->predefined[j].lra_auto_res_disable);
1514 }
1515
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001516 return 0;
1517}
1518
Fenglin Wu22e4cf12018-08-01 15:07:28 +08001519#ifdef CONFIG_DEBUG_FS
1520static int play_rate_dbgfs_read(void *data, u64 *val)
1521{
1522 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1523
1524 *val = effect->play_rate_us;
1525
1526 return 0;
1527}
1528
1529static int play_rate_dbgfs_write(void *data, u64 val)
1530{
1531 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1532
1533 if (val > HAP_PLAY_RATE_US_MAX)
1534 val = HAP_PLAY_RATE_US_MAX;
1535
1536 effect->play_rate_us = val;
1537
1538 return 0;
1539}
1540
1541static int vmax_dbgfs_read(void *data, u64 *val)
1542{
1543 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1544
1545 *val = effect->vmax_mv;
1546
1547 return 0;
1548}
1549
1550static int vmax_dbgfs_write(void *data, u64 val)
1551{
1552 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1553
1554 if (val > HAP_VMAX_MV_MAX)
1555 val = HAP_VMAX_MV_MAX;
1556
1557 effect->vmax_mv = val;
1558
1559 return 0;
1560}
1561
1562static int wf_repeat_n_dbgfs_read(void *data, u64 *val)
1563{
1564 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1565
1566 *val = wf_repeat[effect->wf_repeat_n];
1567
1568 return 0;
1569}
1570
1571static int wf_repeat_n_dbgfs_write(void *data, u64 val)
1572{
1573 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1574 int i;
1575
1576 for (i = 0; i < ARRAY_SIZE(wf_repeat); i++)
1577 if (val == wf_repeat[i])
1578 break;
1579
1580 if (i == ARRAY_SIZE(wf_repeat))
1581 pr_err("wf_repeat value %llu is invalid\n", val);
1582 else
1583 effect->wf_repeat_n = i;
1584
1585 return 0;
1586}
1587
1588static int wf_s_repeat_n_dbgfs_read(void *data, u64 *val)
1589{
1590 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1591
1592 *val = wf_s_repeat[effect->wf_s_repeat_n];
1593
1594 return 0;
1595}
1596
1597static int wf_s_repeat_n_dbgfs_write(void *data, u64 val)
1598{
1599 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1600 int i;
1601
1602 for (i = 0; i < ARRAY_SIZE(wf_s_repeat); i++)
1603 if (val == wf_s_repeat[i])
1604 break;
1605
1606 if (i == ARRAY_SIZE(wf_s_repeat))
1607 pr_err("wf_s_repeat value %llu is invalid\n", val);
1608 else
1609 effect->wf_s_repeat_n = i;
1610
1611 return 0;
1612}
1613
1614
1615static int auto_res_dbgfs_read(void *data, u64 *val)
1616{
1617 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1618
1619 *val = !effect->lra_auto_res_disable;
1620
1621 return 0;
1622}
1623
1624static int auto_res_dbgfs_write(void *data, u64 val)
1625{
1626 struct qti_hap_effect *effect = (struct qti_hap_effect *)data;
1627
1628 effect->lra_auto_res_disable = !val;
1629
1630 return 0;
1631}
1632
1633DEFINE_SIMPLE_ATTRIBUTE(play_rate_debugfs_ops, play_rate_dbgfs_read,
1634 play_rate_dbgfs_write, "%llu\n");
1635DEFINE_SIMPLE_ATTRIBUTE(vmax_debugfs_ops, vmax_dbgfs_read,
1636 vmax_dbgfs_write, "%llu\n");
1637DEFINE_SIMPLE_ATTRIBUTE(wf_repeat_n_debugfs_ops, wf_repeat_n_dbgfs_read,
1638 wf_repeat_n_dbgfs_write, "%llu\n");
1639DEFINE_SIMPLE_ATTRIBUTE(wf_s_repeat_n_debugfs_ops, wf_s_repeat_n_dbgfs_read,
1640 wf_s_repeat_n_dbgfs_write, "%llu\n");
1641DEFINE_SIMPLE_ATTRIBUTE(auto_res_debugfs_ops, auto_res_dbgfs_read,
1642 auto_res_dbgfs_write, "%llu\n");
1643
1644#define CHAR_PER_PATTERN 8
1645static ssize_t brake_pattern_dbgfs_read(struct file *filep,
1646 char __user *buf, size_t count, loff_t *ppos)
1647{
1648 struct qti_hap_effect *effect =
1649 (struct qti_hap_effect *)filep->private_data;
1650 char *kbuf, *tmp;
1651 int rc, length, i, len;
1652
1653 kbuf = kcalloc(CHAR_PER_PATTERN, HAP_BRAKE_PATTERN_MAX, GFP_KERNEL);
1654 if (!kbuf)
1655 return -ENOMEM;
1656
1657 tmp = kbuf;
1658 for (length = 0, i = 0; i < HAP_BRAKE_PATTERN_MAX; i++) {
1659 len = snprintf(tmp, CHAR_PER_PATTERN, "0x%x ",
1660 effect->brake[i]);
1661 tmp += len;
1662 length += len;
1663 }
1664
1665 kbuf[length++] = '\n';
1666 kbuf[length++] = '\0';
1667
1668 rc = simple_read_from_buffer(buf, count, ppos, kbuf, length);
1669
1670 kfree(kbuf);
1671 return rc;
1672}
1673
1674static ssize_t brake_pattern_dbgfs_write(struct file *filep,
1675 const char __user *buf, size_t count, loff_t *ppos)
1676{
1677 struct qti_hap_effect *effect =
1678 (struct qti_hap_effect *)filep->private_data;
1679 char *kbuf, *token;
1680 int rc = 0, i = 0, j;
1681 u32 val;
1682
1683 kbuf = kmalloc(count + 1, GFP_KERNEL);
1684 if (!kbuf)
1685 return -ENOMEM;
1686
1687 rc = copy_from_user(kbuf, buf, count);
1688 if (rc > 0) {
1689 rc = -EFAULT;
1690 goto err;
1691 }
1692
1693 kbuf[count] = '\0';
1694 *ppos += count;
1695
1696 while ((token = strsep(&kbuf, " ")) != NULL) {
1697 rc = kstrtouint(token, 0, &val);
1698 if (rc < 0) {
1699 rc = -EINVAL;
1700 goto err;
1701 }
1702
1703 effect->brake[i++] = val & HAP_BRAKE_PATTERN_MASK;
1704
1705 if (i >= HAP_BRAKE_PATTERN_MAX)
1706 break;
1707 }
1708
1709 for (j = i; j < HAP_BRAKE_PATTERN_MAX; j++)
1710 effect->brake[j] = 0;
1711
1712 effect->brake_pattern_length = i;
1713 verify_brake_setting(effect);
1714
1715 rc = count;
1716err:
1717 kfree(kbuf);
1718 return rc;
1719}
1720
1721static const struct file_operations brake_pattern_dbgfs_ops = {
1722 .read = brake_pattern_dbgfs_read,
1723 .write = brake_pattern_dbgfs_write,
1724 .owner = THIS_MODULE,
1725 .open = simple_open,
1726};
1727
1728static ssize_t pattern_dbgfs_read(struct file *filep,
1729 char __user *buf, size_t count, loff_t *ppos)
1730{
1731 struct qti_hap_effect *effect =
1732 (struct qti_hap_effect *)filep->private_data;
1733 char *kbuf, *tmp;
1734 int rc, length, i, len;
1735
1736 kbuf = kcalloc(CHAR_PER_PATTERN, effect->pattern_length, GFP_KERNEL);
1737 if (!kbuf)
1738 return -ENOMEM;
1739
1740 tmp = kbuf;
1741 for (length = 0, i = 0; i < effect->pattern_length; i++) {
1742 len = snprintf(tmp, CHAR_PER_PATTERN, "0x%x ",
1743 effect->pattern[i]);
1744 tmp += len;
1745 length += len;
1746 }
1747
1748 kbuf[length++] = '\n';
1749 kbuf[length++] = '\0';
1750
1751 rc = simple_read_from_buffer(buf, count, ppos, kbuf, length);
1752
1753 kfree(kbuf);
1754 return rc;
1755}
1756
1757static ssize_t pattern_dbgfs_write(struct file *filep,
1758 const char __user *buf, size_t count, loff_t *ppos)
1759{
1760 struct qti_hap_effect *effect =
1761 (struct qti_hap_effect *)filep->private_data;
1762 char *kbuf, *token;
1763 int rc = 0, i = 0, j;
1764 u32 val;
1765
1766 kbuf = kmalloc(count + 1, GFP_KERNEL);
1767 if (!kbuf)
1768 return -ENOMEM;
1769
1770 rc = copy_from_user(kbuf, buf, count);
1771 if (rc > 0) {
1772 rc = -EFAULT;
1773 goto err;
1774 }
1775
1776 kbuf[count] = '\0';
1777 *ppos += count;
1778
1779 while ((token = strsep(&kbuf, " ")) != NULL) {
1780 rc = kstrtouint(token, 0, &val);
1781 if (rc < 0) {
1782 rc = -EINVAL;
1783 goto err;
1784 }
1785
1786 effect->pattern[i++] = val & 0xff;
1787
1788 if (i >= effect->pattern_length)
1789 break;
1790 }
1791
1792 for (j = i; j < effect->pattern_length; j++)
1793 effect->pattern[j] = 0;
1794
1795 rc = count;
1796err:
1797 kfree(kbuf);
1798 return rc;
1799}
1800
1801static const struct file_operations pattern_dbgfs_ops = {
1802 .read = pattern_dbgfs_read,
1803 .write = pattern_dbgfs_write,
1804 .owner = THIS_MODULE,
1805 .open = simple_open,
1806};
1807
1808static int create_effect_debug_files(struct qti_hap_effect *effect,
1809 struct dentry *dir)
1810{
1811 struct dentry *file;
1812
1813 file = debugfs_create_file("play_rate_us", 0644, dir,
1814 effect, &play_rate_debugfs_ops);
1815 if (!file) {
1816 pr_err("create play-rate debugfs node failed\n");
1817 return -ENOMEM;
1818 }
1819
1820 file = debugfs_create_file("vmax_mv", 0644, dir,
1821 effect, &vmax_debugfs_ops);
1822 if (!file) {
1823 pr_err("create vmax debugfs node failed\n");
1824 return -ENOMEM;
1825 }
1826
1827 file = debugfs_create_file("wf_repeat_n", 0644, dir,
1828 effect, &wf_repeat_n_debugfs_ops);
1829 if (!file) {
1830 pr_err("create wf-repeat debugfs node failed\n");
1831 return -ENOMEM;
1832 }
1833
1834 file = debugfs_create_file("wf_s_repeat_n", 0644, dir,
1835 effect, &wf_s_repeat_n_debugfs_ops);
1836 if (!file) {
1837 pr_err("create wf-s-repeat debugfs node failed\n");
1838 return -ENOMEM;
1839 }
1840
1841 file = debugfs_create_file("lra_auto_res_en", 0644, dir,
1842 effect, &auto_res_debugfs_ops);
1843 if (!file) {
1844 pr_err("create lra-auto-res-en debugfs node failed\n");
1845 return -ENOMEM;
1846 }
1847
1848 file = debugfs_create_file("brake", 0644, dir,
1849 effect, &brake_pattern_dbgfs_ops);
1850 if (!file) {
1851 pr_err("create brake debugfs node failed\n");
1852 return -ENOMEM;
1853 }
1854
1855 file = debugfs_create_file("pattern", 0644, dir,
1856 effect, &pattern_dbgfs_ops);
1857 if (!file) {
1858 pr_err("create pattern debugfs node failed\n");
1859 return -ENOMEM;
1860 }
1861
1862 return 0;
1863}
1864
1865static int qti_haptics_add_debugfs(struct qti_hap_chip *chip)
1866{
1867 struct dentry *hap_dir, *effect_dir;
1868 char str[12] = {0};
1869 int i, rc = 0;
1870
1871 hap_dir = debugfs_create_dir("haptics", NULL);
1872 if (!hap_dir) {
1873 pr_err("create haptics debugfs directory failed\n");
1874 return -ENOMEM;
1875 }
1876
1877 for (i = 0; i < chip->effects_count; i++) {
1878 snprintf(str, ARRAY_SIZE(str), "effect%d", i);
1879 effect_dir = debugfs_create_dir(str, hap_dir);
1880 if (!effect_dir) {
1881 pr_err("create %s debugfs directory failed\n", str);
1882 rc = -ENOMEM;
1883 goto cleanup;
1884 }
1885
1886 rc = create_effect_debug_files(&chip->predefined[i],
1887 effect_dir);
1888 if (rc < 0) {
1889 rc = -ENOMEM;
1890 goto cleanup;
1891 }
1892 }
1893
1894 chip->hap_debugfs = hap_dir;
1895 return 0;
1896
1897cleanup:
1898 debugfs_remove_recursive(hap_dir);
1899 return rc;
1900}
1901#endif
1902
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001903static int qti_haptics_probe(struct platform_device *pdev)
1904{
1905 struct qti_hap_chip *chip;
1906 struct input_dev *input_dev;
1907 struct ff_device *ff;
1908 int rc = 0, effect_count_max;
1909
1910 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1911 if (!chip)
1912 return -ENOMEM;
1913
1914 input_dev = devm_input_allocate_device(&pdev->dev);
1915 if (!input_dev)
1916 return -ENOMEM;
1917
1918 chip->pdev = pdev;
1919 chip->dev = &pdev->dev;
1920 chip->regmap = dev_get_regmap(chip->dev->parent, NULL);
1921 if (!chip->regmap) {
1922 dev_err(chip->dev, "Failed to get regmap handle\n");
1923 return -ENXIO;
1924 }
1925
1926 rc = qti_haptics_parse_dt(chip);
1927 if (rc < 0) {
1928 dev_err(chip->dev, "parse device-tree failed, rc=%d\n", rc);
1929 return rc;
1930 }
1931
1932 spin_lock_init(&chip->bus_lock);
1933
1934 rc = qti_haptics_hw_init(chip);
1935 if (rc < 0) {
1936 dev_err(chip->dev, "parse device-tree failed, rc=%d\n", rc);
1937 return rc;
1938 }
1939
1940 rc = devm_request_threaded_irq(chip->dev, chip->play_irq, NULL,
1941 qti_haptics_play_irq_handler,
1942 IRQF_ONESHOT, "hap_play_irq", chip);
1943 if (rc < 0) {
1944 dev_err(chip->dev, "request play-irq failed, rc=%d\n", rc);
1945 return rc;
1946 }
1947
1948 disable_irq(chip->play_irq);
1949 chip->play_irq_en = false;
1950
1951 rc = devm_request_threaded_irq(chip->dev, chip->sc_irq, NULL,
1952 qti_haptics_sc_irq_handler,
1953 IRQF_ONESHOT, "hap_sc_irq", chip);
1954 if (rc < 0) {
1955 dev_err(chip->dev, "request sc-irq failed, rc=%d\n", rc);
1956 return rc;
1957 }
1958
Umang Chheda599b0962020-01-20 17:15:54 +05301959 chip->twm_nb.notifier_call = twm_notifier_cb;
1960 rc = qpnp_misc_twm_notifier_register(&chip->twm_nb);
1961 if (rc < 0)
1962 pr_err("Failed to register twm_notifier_cb rc=%d\n", rc);
1963
Fenglin Wu30f10b22018-06-15 07:49:23 +08001964 hrtimer_init(&chip->stop_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1965 chip->stop_timer.function = qti_hap_stop_timer;
Fenglin Wu802427a2018-08-31 16:07:59 +08001966 hrtimer_init(&chip->hap_disable_timer, CLOCK_MONOTONIC,
1967 HRTIMER_MODE_REL);
1968 chip->hap_disable_timer.function = qti_hap_disable_timer;
Fenglin Wu37aa3492018-07-10 10:58:49 +08001969 input_dev->name = "qti-haptics";
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001970 input_set_drvdata(input_dev, chip);
1971 chip->input_dev = input_dev;
1972
1973 input_set_capability(input_dev, EV_FF, FF_CONSTANT);
Fenglin Wud92ef742018-07-16 15:50:08 +08001974 input_set_capability(input_dev, EV_FF, FF_GAIN);
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001975 if (chip->effects_count != 0) {
1976 input_set_capability(input_dev, EV_FF, FF_PERIODIC);
1977 input_set_capability(input_dev, EV_FF, FF_CUSTOM);
1978 }
1979
1980 if (chip->effects_count + 1 > FF_EFFECT_COUNT_MAX)
1981 effect_count_max = chip->effects_count + 1;
1982 else
1983 effect_count_max = FF_EFFECT_COUNT_MAX;
1984 rc = input_ff_create(input_dev, effect_count_max);
1985 if (rc < 0) {
1986 dev_err(chip->dev, "create FF input device failed, rc=%d\n",
1987 rc);
1988 return rc;
1989 }
1990
1991 ff = input_dev->ff;
1992 ff->upload = qti_haptics_upload_effect;
1993 ff->playback = qti_haptics_playback;
1994 ff->erase = qti_haptics_erase;
Fenglin Wud92ef742018-07-16 15:50:08 +08001995 ff->set_gain = qti_haptics_set_gain;
Fenglin Wu3840f8e2018-04-27 13:48:43 +08001996
1997 rc = input_register_device(input_dev);
1998 if (rc < 0) {
1999 dev_err(chip->dev, "register input device failed, rc=%d\n",
2000 rc);
2001 goto destroy_ff;
2002 }
2003
2004 dev_set_drvdata(chip->dev, chip);
Fenglin Wu22e4cf12018-08-01 15:07:28 +08002005#ifdef CONFIG_DEBUG_FS
2006 rc = qti_haptics_add_debugfs(chip);
2007 if (rc < 0)
2008 dev_dbg(chip->dev, "create debugfs failed, rc=%d\n", rc);
2009#endif
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002010 return 0;
2011
2012destroy_ff:
2013 input_ff_destroy(chip->input_dev);
Umang Chheda599b0962020-01-20 17:15:54 +05302014 qpnp_misc_twm_notifier_unregister(&chip->twm_nb);
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002015 return rc;
2016}
2017
2018static int qti_haptics_remove(struct platform_device *pdev)
2019{
2020 struct qti_hap_chip *chip = dev_get_drvdata(&pdev->dev);
2021
Fenglin Wu22e4cf12018-08-01 15:07:28 +08002022#ifdef CONFIG_DEBUG_FS
2023 debugfs_remove_recursive(chip->hap_debugfs);
2024#endif
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002025 input_ff_destroy(chip->input_dev);
Umang Chheda599b0962020-01-20 17:15:54 +05302026 qpnp_misc_twm_notifier_unregister(&chip->twm_nb);
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002027 dev_set_drvdata(chip->dev, NULL);
2028
2029 return 0;
2030}
2031
Fenglin Wu802427a2018-08-31 16:07:59 +08002032static void qti_haptics_shutdown(struct platform_device *pdev)
2033{
2034 struct qti_hap_chip *chip = dev_get_drvdata(&pdev->dev);
2035 int rc;
Anirudh Ghayal760e91d2020-04-13 15:33:39 +05302036 bool enable_haptics_twm;
Fenglin Wu802427a2018-08-31 16:07:59 +08002037
2038 dev_dbg(chip->dev, "Shutdown!\n");
2039
2040 qti_haptics_module_en(chip, false);
2041
2042 if (chip->vdd_supply && chip->vdd_enabled) {
2043 rc = regulator_disable(chip->vdd_supply);
2044 if (rc < 0) {
2045 dev_err(chip->dev, "Disable VDD supply failed, rc=%d\n",
2046 rc);
2047 return;
2048 }
2049 chip->vdd_enabled = false;
2050 }
Umang Chheda599b0962020-01-20 17:15:54 +05302051
Anirudh Ghayal760e91d2020-04-13 15:33:39 +05302052 enable_haptics_twm = chip->haptics_ext_pin_twm && twm_sys_enable;
2053
2054 if (chip->twm_state == PMIC_TWM_ENABLE && enable_haptics_twm) {
Umang Chheda599b0962020-01-20 17:15:54 +05302055 rc = qti_haptics_twm_config(chip);
2056 if (rc < 0)
2057 pr_err("Haptics TWM config failed rc=%d\n", rc);
2058 }
Fenglin Wu802427a2018-08-31 16:07:59 +08002059}
2060
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002061static const struct of_device_id haptics_match_table[] = {
2062 { .compatible = "qcom,haptics" },
2063 { .compatible = "qcom,pm660-haptics" },
2064 { .compatible = "qcom,pm8150b-haptics" },
2065 {},
2066};
2067
2068static struct platform_driver qti_haptics_driver = {
2069 .driver = {
2070 .name = "qcom,haptics",
Fenglin Wu802427a2018-08-31 16:07:59 +08002071 .owner = THIS_MODULE,
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002072 .of_match_table = haptics_match_table,
2073 },
2074 .probe = qti_haptics_probe,
2075 .remove = qti_haptics_remove,
Fenglin Wu802427a2018-08-31 16:07:59 +08002076 .shutdown = qti_haptics_shutdown,
Fenglin Wu3840f8e2018-04-27 13:48:43 +08002077};
2078module_platform_driver(qti_haptics_driver);
2079
2080MODULE_DESCRIPTION("QTI haptics driver");
2081MODULE_LICENSE("GPL v2");