Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) |
| 7 | * |
| 8 | * SMP support for BMIPS |
| 9 | */ |
| 10 | |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 11 | #include <linux/init.h> |
| 12 | #include <linux/sched.h> |
| 13 | #include <linux/mm.h> |
| 14 | #include <linux/delay.h> |
| 15 | #include <linux/smp.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/spinlock.h> |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 18 | #include <linux/cpu.h> |
| 19 | #include <linux/cpumask.h> |
| 20 | #include <linux/reboot.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/compiler.h> |
| 23 | #include <linux/linkage.h> |
| 24 | #include <linux/bug.h> |
| 25 | #include <linux/kernel.h> |
| 26 | |
| 27 | #include <asm/time.h> |
| 28 | #include <asm/pgtable.h> |
| 29 | #include <asm/processor.h> |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 30 | #include <asm/bootinfo.h> |
| 31 | #include <asm/pmon.h> |
| 32 | #include <asm/cacheflush.h> |
| 33 | #include <asm/tlbflush.h> |
| 34 | #include <asm/mipsregs.h> |
| 35 | #include <asm/bmips.h> |
| 36 | #include <asm/traps.h> |
| 37 | #include <asm/barrier.h> |
Kevin Cernekee | fc45578 | 2014-10-20 21:27:53 -0700 | [diff] [blame] | 38 | #include <asm/cpu-features.h> |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 39 | |
| 40 | static int __maybe_unused max_cpus = 1; |
| 41 | |
| 42 | /* these may be configured by the platform code */ |
| 43 | int bmips_smp_enabled = 1; |
| 44 | int bmips_cpu_offset; |
| 45 | cpumask_t bmips_booted_mask; |
| 46 | |
Kevin Cernekee | fc45578 | 2014-10-20 21:27:53 -0700 | [diff] [blame] | 47 | #define RESET_FROM_KSEG0 0x80080800 |
| 48 | #define RESET_FROM_KSEG1 0xa0080800 |
| 49 | |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 50 | #ifdef CONFIG_SMP |
| 51 | |
| 52 | /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */ |
| 53 | unsigned long bmips_smp_boot_sp; |
| 54 | unsigned long bmips_smp_boot_gp; |
| 55 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 56 | static void bmips43xx_send_ipi_single(int cpu, unsigned int action); |
| 57 | static void bmips5000_send_ipi_single(int cpu, unsigned int action); |
| 58 | static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id); |
| 59 | static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 60 | |
| 61 | /* SW interrupts 0,1 are used for interprocessor signaling */ |
| 62 | #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) |
| 63 | #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1) |
| 64 | |
| 65 | #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) |
| 66 | #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) |
| 67 | #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) |
| 68 | #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) |
| 69 | |
| 70 | static void __init bmips_smp_setup(void) |
| 71 | { |
Florian Fainelli | 4df715a | 2013-06-26 18:11:56 +0000 | [diff] [blame] | 72 | int i, cpu = 1, boot_cpu = 0; |
Florian Fainelli | fcfa66d | 2013-08-05 11:50:25 +0100 | [diff] [blame] | 73 | int cpu_hw_intr; |
| 74 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 75 | switch (current_cpu_type()) { |
| 76 | case CPU_BMIPS4350: |
| 77 | case CPU_BMIPS4380: |
| 78 | /* arbitration priority */ |
| 79 | clear_c0_brcm_cmt_ctrl(0x30); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 80 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 81 | /* NBK and weak order flags */ |
| 82 | set_c0_brcm_config_0(0x30000); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 83 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 84 | /* Find out if we are running on TP0 or TP1 */ |
| 85 | boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); |
Florian Fainelli | 4df715a | 2013-06-26 18:11:56 +0000 | [diff] [blame] | 86 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 87 | /* |
| 88 | * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other |
| 89 | * thread |
| 90 | * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output |
| 91 | * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output |
| 92 | */ |
| 93 | if (boot_cpu == 0) |
| 94 | cpu_hw_intr = 0x02; |
| 95 | else |
| 96 | cpu_hw_intr = 0x1d; |
Florian Fainelli | fcfa66d | 2013-08-05 11:50:25 +0100 | [diff] [blame] | 97 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 98 | change_c0_brcm_cmt_intr(0xf8018000, |
| 99 | (cpu_hw_intr << 27) | (0x03 << 15)); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 100 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 101 | /* single core, 2 threads (2 pipelines) */ |
| 102 | max_cpus = 2; |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 103 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 104 | break; |
| 105 | case CPU_BMIPS5000: |
| 106 | /* enable raceless SW interrupts */ |
| 107 | set_c0_brcm_config(0x03 << 22); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 108 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 109 | /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ |
| 110 | change_c0_brcm_mode(0x1f << 27, 0x02 << 27); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 111 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 112 | /* N cores, 2 threads per core */ |
| 113 | max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; |
| 114 | |
| 115 | /* clear any pending SW interrupts */ |
| 116 | for (i = 0; i < max_cpus; i++) { |
| 117 | write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); |
| 118 | write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); |
| 119 | } |
| 120 | |
| 121 | break; |
| 122 | default: |
| 123 | max_cpus = 1; |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 124 | } |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 125 | |
| 126 | if (!bmips_smp_enabled) |
| 127 | max_cpus = 1; |
| 128 | |
| 129 | /* this can be overridden by the BSP */ |
| 130 | if (!board_ebase_setup) |
| 131 | board_ebase_setup = &bmips_ebase_setup; |
| 132 | |
Florian Fainelli | 4df715a | 2013-06-26 18:11:56 +0000 | [diff] [blame] | 133 | __cpu_number_map[boot_cpu] = 0; |
| 134 | __cpu_logical_map[0] = boot_cpu; |
| 135 | |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 136 | for (i = 0; i < max_cpus; i++) { |
Florian Fainelli | 4df715a | 2013-06-26 18:11:56 +0000 | [diff] [blame] | 137 | if (i != boot_cpu) { |
| 138 | __cpu_number_map[i] = cpu; |
| 139 | __cpu_logical_map[cpu] = i; |
| 140 | cpu++; |
| 141 | } |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 142 | set_cpu_possible(i, 1); |
| 143 | set_cpu_present(i, 1); |
| 144 | } |
| 145 | } |
| 146 | |
| 147 | /* |
| 148 | * IPI IRQ setup - runs on CPU0 |
| 149 | */ |
| 150 | static void bmips_prepare_cpus(unsigned int max_cpus) |
| 151 | { |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 152 | irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id); |
| 153 | |
| 154 | switch (current_cpu_type()) { |
| 155 | case CPU_BMIPS4350: |
| 156 | case CPU_BMIPS4380: |
| 157 | bmips_ipi_interrupt = bmips43xx_ipi_interrupt; |
| 158 | break; |
| 159 | case CPU_BMIPS5000: |
| 160 | bmips_ipi_interrupt = bmips5000_ipi_interrupt; |
| 161 | break; |
| 162 | default: |
| 163 | return; |
| 164 | } |
| 165 | |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 166 | if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, |
| 167 | "smp_ipi0", NULL)) |
Ralf Baechle | f7777dc | 2013-09-18 16:05:26 +0200 | [diff] [blame] | 168 | panic("Can't request IPI0 interrupt"); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 169 | if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, |
| 170 | "smp_ipi1", NULL)) |
Ralf Baechle | f7777dc | 2013-09-18 16:05:26 +0200 | [diff] [blame] | 171 | panic("Can't request IPI1 interrupt"); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | /* |
| 175 | * Tell the hardware to boot CPUx - runs on CPU0 |
| 176 | */ |
| 177 | static void bmips_boot_secondary(int cpu, struct task_struct *idle) |
| 178 | { |
| 179 | bmips_smp_boot_sp = __KSTK_TOS(idle); |
| 180 | bmips_smp_boot_gp = (unsigned long)task_thread_info(idle); |
| 181 | mb(); |
| 182 | |
| 183 | /* |
| 184 | * Initial boot sequence for secondary CPU: |
| 185 | * bmips_reset_nmi_vec @ a000_0000 -> |
| 186 | * bmips_smp_entry -> |
| 187 | * plat_wired_tlb_setup (cached function call; optional) -> |
| 188 | * start_secondary (cached jump) |
| 189 | * |
| 190 | * Warm restart sequence: |
| 191 | * play_dead WAIT loop -> |
| 192 | * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC -> |
| 193 | * eret to play_dead -> |
| 194 | * bmips_secondary_reentry -> |
| 195 | * start_secondary |
| 196 | */ |
| 197 | |
| 198 | pr_info("SMP: Booting CPU%d...\n", cpu); |
| 199 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 200 | if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { |
| 201 | switch (current_cpu_type()) { |
| 202 | case CPU_BMIPS4350: |
| 203 | case CPU_BMIPS4380: |
| 204 | bmips43xx_send_ipi_single(cpu, 0); |
| 205 | break; |
| 206 | case CPU_BMIPS5000: |
| 207 | bmips5000_send_ipi_single(cpu, 0); |
| 208 | break; |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 209 | } |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 210 | } |
| 211 | else { |
| 212 | switch (current_cpu_type()) { |
| 213 | case CPU_BMIPS4350: |
| 214 | case CPU_BMIPS4380: |
| 215 | /* Reset slave TP1 if booting from TP0 */ |
| 216 | if (cpu_logical_map(cpu) == 1) |
| 217 | set_c0_brcm_cmt_ctrl(0x01); |
| 218 | break; |
| 219 | case CPU_BMIPS5000: |
Kevin Cernekee | bdb2e05 | 2014-10-20 21:27:52 -0700 | [diff] [blame] | 220 | write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 221 | break; |
| 222 | } |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 223 | cpumask_set_cpu(cpu, &bmips_booted_mask); |
| 224 | } |
| 225 | } |
| 226 | |
| 227 | /* |
| 228 | * Early setup - runs on secondary CPU after cache probe |
| 229 | */ |
| 230 | static void bmips_init_secondary(void) |
| 231 | { |
| 232 | /* move NMI vector to kseg0, in case XKS01 is enabled */ |
| 233 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 234 | void __iomem *cbr; |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 235 | unsigned long old_vec; |
Florian Fainelli | ff5fada | 2013-07-24 17:12:11 +0100 | [diff] [blame] | 236 | unsigned long relo_vector; |
| 237 | int boot_cpu; |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 238 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 239 | switch (current_cpu_type()) { |
| 240 | case CPU_BMIPS4350: |
| 241 | case CPU_BMIPS4380: |
| 242 | cbr = BMIPS_GET_CBR(); |
Florian Fainelli | ff5fada | 2013-07-24 17:12:11 +0100 | [diff] [blame] | 243 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 244 | boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); |
| 245 | relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 : |
| 246 | BMIPS_RELO_VECTOR_CONTROL_1; |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 247 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 248 | old_vec = __raw_readl(cbr + relo_vector); |
| 249 | __raw_writel(old_vec & ~0x20000000, cbr + relo_vector); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 250 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 251 | clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); |
| 252 | break; |
| 253 | case CPU_BMIPS5000: |
| 254 | write_c0_brcm_bootvec(read_c0_brcm_bootvec() & |
| 255 | (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000)); |
| 256 | |
| 257 | write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); |
| 258 | break; |
| 259 | } |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 260 | } |
| 261 | |
| 262 | /* |
| 263 | * Late setup - runs on secondary CPU before entering the idle loop |
| 264 | */ |
| 265 | static void bmips_smp_finish(void) |
| 266 | { |
| 267 | pr_info("SMP: CPU%d is running\n", smp_processor_id()); |
Yong Zhang | 856ac3c | 2012-07-19 09:13:53 +0200 | [diff] [blame] | 268 | |
| 269 | /* make sure there won't be a timer interrupt for a little while */ |
| 270 | write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); |
| 271 | |
| 272 | irq_enable_hazard(); |
| 273 | set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE); |
| 274 | irq_enable_hazard(); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 275 | } |
| 276 | |
| 277 | /* |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 278 | * BMIPS5000 raceless IPIs |
| 279 | * |
| 280 | * Each CPU has two inbound SW IRQs which are independent of all other CPUs. |
| 281 | * IPI0 is used for SMP_RESCHEDULE_YOURSELF |
| 282 | * IPI1 is used for SMP_CALL_FUNCTION |
| 283 | */ |
| 284 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 285 | static void bmips5000_send_ipi_single(int cpu, unsigned int action) |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 286 | { |
| 287 | write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); |
| 288 | } |
| 289 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 290 | static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 291 | { |
| 292 | int action = irq - IPI0_IRQ; |
| 293 | |
| 294 | write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action)); |
| 295 | |
| 296 | if (action == 0) |
| 297 | scheduler_ipi(); |
| 298 | else |
| 299 | smp_call_function_interrupt(); |
| 300 | |
| 301 | return IRQ_HANDLED; |
| 302 | } |
| 303 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 304 | static void bmips5000_send_ipi_mask(const struct cpumask *mask, |
| 305 | unsigned int action) |
| 306 | { |
| 307 | unsigned int i; |
| 308 | |
| 309 | for_each_cpu(i, mask) |
| 310 | bmips5000_send_ipi_single(i, action); |
| 311 | } |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 312 | |
| 313 | /* |
| 314 | * BMIPS43xx racey IPIs |
| 315 | * |
| 316 | * We use one inbound SW IRQ for each CPU. |
| 317 | * |
| 318 | * A spinlock must be held in order to keep CPUx from accidentally clearing |
| 319 | * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The |
| 320 | * same spinlock is used to protect the action masks. |
| 321 | */ |
| 322 | |
| 323 | static DEFINE_SPINLOCK(ipi_lock); |
| 324 | static DEFINE_PER_CPU(int, ipi_action_mask); |
| 325 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 326 | static void bmips43xx_send_ipi_single(int cpu, unsigned int action) |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 327 | { |
| 328 | unsigned long flags; |
| 329 | |
| 330 | spin_lock_irqsave(&ipi_lock, flags); |
| 331 | set_c0_cause(cpu ? C_SW1 : C_SW0); |
| 332 | per_cpu(ipi_action_mask, cpu) |= action; |
| 333 | irq_enable_hazard(); |
| 334 | spin_unlock_irqrestore(&ipi_lock, flags); |
| 335 | } |
| 336 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 337 | static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 338 | { |
| 339 | unsigned long flags; |
| 340 | int action, cpu = irq - IPI0_IRQ; |
| 341 | |
| 342 | spin_lock_irqsave(&ipi_lock, flags); |
Christoph Lameter | 3589871 | 2014-08-17 12:30:44 -0500 | [diff] [blame] | 343 | action = __this_cpu_read(ipi_action_mask); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 344 | per_cpu(ipi_action_mask, cpu) = 0; |
| 345 | clear_c0_cause(cpu ? C_SW1 : C_SW0); |
| 346 | spin_unlock_irqrestore(&ipi_lock, flags); |
| 347 | |
| 348 | if (action & SMP_RESCHEDULE_YOURSELF) |
| 349 | scheduler_ipi(); |
| 350 | if (action & SMP_CALL_FUNCTION) |
| 351 | smp_call_function_interrupt(); |
| 352 | |
| 353 | return IRQ_HANDLED; |
| 354 | } |
| 355 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 356 | static void bmips43xx_send_ipi_mask(const struct cpumask *mask, |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 357 | unsigned int action) |
| 358 | { |
| 359 | unsigned int i; |
| 360 | |
| 361 | for_each_cpu(i, mask) |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 362 | bmips43xx_send_ipi_single(i, action); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 363 | } |
| 364 | |
| 365 | #ifdef CONFIG_HOTPLUG_CPU |
| 366 | |
| 367 | static int bmips_cpu_disable(void) |
| 368 | { |
| 369 | unsigned int cpu = smp_processor_id(); |
| 370 | |
| 371 | if (cpu == 0) |
| 372 | return -EBUSY; |
| 373 | |
| 374 | pr_info("SMP: CPU%d is offline\n", cpu); |
| 375 | |
Rusty Russell | 0b5f9c0 | 2012-03-29 15:38:30 +1030 | [diff] [blame] | 376 | set_cpu_online(cpu, false); |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 377 | cpu_clear(cpu, cpu_callin_map); |
| 378 | |
| 379 | local_flush_tlb_all(); |
| 380 | local_flush_icache_range(0, ~0); |
| 381 | |
| 382 | return 0; |
| 383 | } |
| 384 | |
| 385 | static void bmips_cpu_die(unsigned int cpu) |
| 386 | { |
| 387 | } |
| 388 | |
| 389 | void __ref play_dead(void) |
| 390 | { |
| 391 | idle_task_exit(); |
| 392 | |
| 393 | /* flush data cache */ |
| 394 | _dma_cache_wback_inv(0, ~0); |
| 395 | |
| 396 | /* |
| 397 | * Wakeup is on SW0 or SW1; disable everything else |
| 398 | * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux |
| 399 | * IRQ handlers; this clears ST0_IE and returns immediately. |
| 400 | */ |
| 401 | clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1); |
| 402 | change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV, |
| 403 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV); |
| 404 | irq_disable_hazard(); |
| 405 | |
| 406 | /* |
| 407 | * wait for SW interrupt from bmips_boot_secondary(), then jump |
| 408 | * back to start_secondary() |
| 409 | */ |
| 410 | __asm__ __volatile__( |
| 411 | " wait\n" |
| 412 | " j bmips_secondary_reentry\n" |
| 413 | : : : "memory"); |
| 414 | } |
| 415 | |
| 416 | #endif /* CONFIG_HOTPLUG_CPU */ |
| 417 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 418 | struct plat_smp_ops bmips43xx_smp_ops = { |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 419 | .smp_setup = bmips_smp_setup, |
| 420 | .prepare_cpus = bmips_prepare_cpus, |
| 421 | .boot_secondary = bmips_boot_secondary, |
| 422 | .smp_finish = bmips_smp_finish, |
| 423 | .init_secondary = bmips_init_secondary, |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 424 | .send_ipi_single = bmips43xx_send_ipi_single, |
| 425 | .send_ipi_mask = bmips43xx_send_ipi_mask, |
| 426 | #ifdef CONFIG_HOTPLUG_CPU |
| 427 | .cpu_disable = bmips_cpu_disable, |
| 428 | .cpu_die = bmips_cpu_die, |
| 429 | #endif |
| 430 | }; |
| 431 | |
| 432 | struct plat_smp_ops bmips5000_smp_ops = { |
| 433 | .smp_setup = bmips_smp_setup, |
| 434 | .prepare_cpus = bmips_prepare_cpus, |
| 435 | .boot_secondary = bmips_boot_secondary, |
| 436 | .smp_finish = bmips_smp_finish, |
| 437 | .init_secondary = bmips_init_secondary, |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 438 | .send_ipi_single = bmips5000_send_ipi_single, |
| 439 | .send_ipi_mask = bmips5000_send_ipi_mask, |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 440 | #ifdef CONFIG_HOTPLUG_CPU |
| 441 | .cpu_disable = bmips_cpu_disable, |
| 442 | .cpu_die = bmips_cpu_die, |
| 443 | #endif |
| 444 | }; |
| 445 | |
| 446 | #endif /* CONFIG_SMP */ |
| 447 | |
| 448 | /*********************************************************************** |
| 449 | * BMIPS vector relocation |
| 450 | * This is primarily used for SMP boot, but it is applicable to some |
| 451 | * UP BMIPS systems as well. |
| 452 | ***********************************************************************/ |
| 453 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 454 | static void bmips_wr_vec(unsigned long dst, char *start, char *end) |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 455 | { |
| 456 | memcpy((void *)dst, start, end - start); |
| 457 | dma_cache_wback((unsigned long)start, end - start); |
| 458 | local_flush_icache_range(dst, dst + (end - start)); |
| 459 | instruction_hazard(); |
| 460 | } |
| 461 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 462 | static inline void bmips_nmi_handler_setup(void) |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 463 | { |
| 464 | bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec, |
| 465 | &bmips_reset_nmi_vec_end); |
| 466 | bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec, |
| 467 | &bmips_smp_int_vec_end); |
| 468 | } |
| 469 | |
Kevin Cernekee | fc45578 | 2014-10-20 21:27:53 -0700 | [diff] [blame] | 470 | struct reset_vec_info { |
| 471 | int cpu; |
| 472 | u32 val; |
| 473 | }; |
| 474 | |
| 475 | static void bmips_set_reset_vec_remote(void *vinfo) |
| 476 | { |
| 477 | struct reset_vec_info *info = vinfo; |
| 478 | int shift = info->cpu & 0x01 ? 16 : 0; |
| 479 | u32 mask = ~(0xffff << shift), val = info->val >> 16; |
| 480 | |
| 481 | preempt_disable(); |
| 482 | if (smp_processor_id() > 0) { |
| 483 | smp_call_function_single(0, &bmips_set_reset_vec_remote, |
| 484 | info, 1); |
| 485 | } else { |
| 486 | if (info->cpu & 0x02) { |
| 487 | /* BMIPS5200 "should" use mask/shift, but it's buggy */ |
| 488 | bmips_write_zscm_reg(0xa0, (val << 16) | val); |
| 489 | bmips_read_zscm_reg(0xa0); |
| 490 | } else { |
| 491 | write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) | |
| 492 | (val << shift)); |
| 493 | } |
| 494 | } |
| 495 | preempt_enable(); |
| 496 | } |
| 497 | |
| 498 | static void bmips_set_reset_vec(int cpu, u32 val) |
| 499 | { |
| 500 | struct reset_vec_info info; |
| 501 | |
| 502 | if (current_cpu_type() == CPU_BMIPS5000) { |
| 503 | /* this needs to run from CPU0 (which is always online) */ |
| 504 | info.cpu = cpu; |
| 505 | info.val = val; |
| 506 | bmips_set_reset_vec_remote(&info); |
| 507 | } else { |
| 508 | void __iomem *cbr = BMIPS_GET_CBR(); |
| 509 | |
| 510 | if (cpu == 0) |
| 511 | __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); |
| 512 | else { |
| 513 | if (current_cpu_type() != CPU_BMIPS4380) |
| 514 | return; |
| 515 | __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); |
| 516 | } |
| 517 | } |
| 518 | __sync(); |
| 519 | back_to_back_c0_hazard(); |
| 520 | } |
| 521 | |
Paul Gortmaker | 078a55f | 2013-06-18 13:38:59 +0000 | [diff] [blame] | 522 | void bmips_ebase_setup(void) |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 523 | { |
| 524 | unsigned long new_ebase = ebase; |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 525 | |
| 526 | BUG_ON(ebase != CKSEG0); |
| 527 | |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 528 | switch (current_cpu_type()) { |
| 529 | case CPU_BMIPS4350: |
| 530 | /* |
| 531 | * BMIPS4350 cannot relocate the normal vectors, but it |
| 532 | * can relocate the BEV=1 vectors. So CPU1 starts up at |
| 533 | * the relocated BEV=1, IV=0 general exception vector @ |
| 534 | * 0xa000_0380. |
| 535 | * |
| 536 | * set_uncached_handler() is used here because: |
| 537 | * - CPU1 will run this from uncached space |
| 538 | * - None of the cacheflush functions are set up yet |
| 539 | */ |
| 540 | set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, |
| 541 | &bmips_smp_int_vec, 0x80); |
| 542 | __sync(); |
| 543 | return; |
Jon Fraser | fa01067 | 2014-10-20 21:27:54 -0700 | [diff] [blame^] | 544 | case CPU_BMIPS3300: |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 545 | case CPU_BMIPS4380: |
| 546 | /* |
| 547 | * 0x8000_0000: reset/NMI (initially in kseg1) |
| 548 | * 0x8000_0400: normal vectors |
| 549 | */ |
| 550 | new_ebase = 0x80000400; |
Kevin Cernekee | fc45578 | 2014-10-20 21:27:53 -0700 | [diff] [blame] | 551 | bmips_set_reset_vec(0, RESET_FROM_KSEG0); |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 552 | break; |
| 553 | case CPU_BMIPS5000: |
| 554 | /* |
| 555 | * 0x8000_0000: reset/NMI (initially in kseg1) |
| 556 | * 0x8000_1000: normal vectors |
| 557 | */ |
| 558 | new_ebase = 0x80001000; |
Kevin Cernekee | fc45578 | 2014-10-20 21:27:53 -0700 | [diff] [blame] | 559 | bmips_set_reset_vec(0, RESET_FROM_KSEG0); |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 560 | write_c0_ebase(new_ebase); |
Jonas Gorski | 6465460 | 2013-12-18 14:12:01 +0100 | [diff] [blame] | 561 | break; |
| 562 | default: |
| 563 | return; |
| 564 | } |
| 565 | |
Kevin Cernekee | df0ac8a | 2011-11-16 01:25:45 +0000 | [diff] [blame] | 566 | board_nmi_handler_setup = &bmips_nmi_handler_setup; |
| 567 | ebase = new_ebase; |
| 568 | } |
| 569 | |
| 570 | asmlinkage void __weak plat_wired_tlb_setup(void) |
| 571 | { |
| 572 | /* |
| 573 | * Called when starting/restarting a secondary CPU. |
| 574 | * Kernel stacks and other important data might only be accessible |
| 575 | * once the wired entries are present. |
| 576 | */ |
| 577 | } |