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gerrit-public.fairphone.software / kernel / msm-4.9 / fa665ccf01440644a3956ed039e51e1088cd0f15 / . / arch / blackfin / mach-bf561 / Kconfig
blob: 638ec38ca47066ccc8fcfc15a294a00598934c2e [file] [log] [blame]
Mike Frysinger4f25eb82007-11-15 20:49:44 +0800[diff] [blame]1if (BF561)
2
3source "arch/blackfin/mach-bf561/boards/Kconfig"
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]4
5menu "BF561 Specific Configuration"
6
Graf Yangc51b4482009-01-07 23:14:39 +0800[diff] [blame]7if (!SMP)
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]8
Graf Yangc51b4482009-01-07 23:14:39 +0800[diff] [blame]9comment "Core B Support"
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]10
11config BF561_COREB
12 bool "Enable Core B support"
13 default y
14
15config BF561_COREB_RESET
16 bool "Enable Core B reset support"
17 default n
18 help
19 This requires code in the application that is loaded
20 into Core B. In order to reset, the application needs
21 to install an interrupt handler for Supplemental
22 Interrupt 0, that sets RETI to 0xff600000 and writes
23 bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0.
24 This causes Core B to stall when Supplemental Interrupt
25 0 is set, and will reset PC to 0xff600000 when
26 COREB_SRAM_INIT is cleared.
27
Graf Yangc51b4482009-01-07 23:14:39 +0800[diff] [blame]28endif
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]29
30comment "Interrupt Priority Assignment"
31
32menu "Priority"
33
34config IRQ_PLL_WAKEUP
35 int "PLL Wakeup Interrupt"
36 default 7
37config IRQ_DMA1_ERROR
38 int "DMA1 Error (generic)"
39 default 7
40config IRQ_DMA2_ERROR
41 int "DMA2 Error (generic)"
42 default 7
43config IRQ_IMDMA_ERROR
44 int "IMDMA Error (generic)"
45 default 7
46config IRQ_PPI0_ERROR
47 int "PPI0 Error Interrupt"
48 default 7
49config IRQ_PPI1_ERROR
50 int "PPI1 Error Interrupt"
51 default 7
52config IRQ_SPORT0_ERROR
53 int "SPORT0 Error Interrupt"
54 default 7
55config IRQ_SPORT1_ERROR
56 int "SPORT1 Error Interrupt"
57 default 7
58config IRQ_SPI_ERROR
59 int "SPI Error Interrupt"
60 default 7
61config IRQ_UART_ERROR
62 int "UART Error Interrupt"
63 default 7
64config IRQ_RESERVED_ERROR
65 int "Reserved Interrupt"
66 default 7
67config IRQ_DMA1_0
68 int "DMA1 0 Interrupt(PPI1)"
69 default 8
70config IRQ_DMA1_1
71 int "DMA1 1 Interrupt(PPI2)"
72 default 8
73config IRQ_DMA1_2
74 int "DMA1 2 Interrupt"
75 default 8
76config IRQ_DMA1_3
77 int "DMA1 3 Interrupt"
78 default 8
79config IRQ_DMA1_4
80 int "DMA1 4 Interrupt"
81 default 8
82config IRQ_DMA1_5
83 int "DMA1 5 Interrupt"
84 default 8
85config IRQ_DMA1_6
86 int "DMA1 6 Interrupt"
87 default 8
88config IRQ_DMA1_7
89 int "DMA1 7 Interrupt"
90 default 8
91config IRQ_DMA1_8
92 int "DMA1 8 Interrupt"
93 default 8
94config IRQ_DMA1_9
95 int "DMA1 9 Interrupt"
96 default 8
97config IRQ_DMA1_10
98 int "DMA1 10 Interrupt"
99 default 8
100config IRQ_DMA1_11
101 int "DMA1 11 Interrupt"
102 default 8
103config IRQ_DMA2_0
104 int "DMA2 0 (SPORT0 RX)"
105 default 9
106config IRQ_DMA2_1
107 int "DMA2 1 (SPORT0 TX)"
108 default 9
109config IRQ_DMA2_2
110 int "DMA2 2 (SPORT1 RX)"
111 default 9
112config IRQ_DMA2_3
113 int "DMA2 3 (SPORT2 TX)"
114 default 9
115config IRQ_DMA2_4
116 int "DMA2 4 (SPI)"
117 default 9
118config IRQ_DMA2_5
119 int "DMA2 5 (UART RX)"
120 default 9
121config IRQ_DMA2_6
122 int "DMA2 6 (UART TX)"
123 default 9
124config IRQ_DMA2_7
125 int "DMA2 7 Interrupt"
126 default 9
127config IRQ_DMA2_8
128 int "DMA2 8 Interrupt"
129 default 9
130config IRQ_DMA2_9
131 int "DMA2 9 Interrupt"
132 default 9
133config IRQ_DMA2_10
134 int "DMA2 10 Interrupt"
135 default 9
136config IRQ_DMA2_11
137 int "DMA2 11 Interrupt"
138 default 9
139config IRQ_TIMER0
140 int "TIMER 0 Interrupt"
Yi Li6a01f232009-01-07 23:14:39 +0800[diff] [blame]141 default 8
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]142config IRQ_TIMER1
143 int "TIMER 1 Interrupt"
144 default 10
145config IRQ_TIMER2
146 int "TIMER 2 Interrupt"
147 default 10
148config IRQ_TIMER3
149 int "TIMER 3 Interrupt"
150 default 10
151config IRQ_TIMER4
152 int "TIMER 4 Interrupt"
153 default 10
154config IRQ_TIMER5
155 int "TIMER 5 Interrupt"
156 default 10
157config IRQ_TIMER6
158 int "TIMER 6 Interrupt"
159 default 10
160config IRQ_TIMER7
161 int "TIMER 7 Interrupt"
162 default 10
163config IRQ_TIMER8
164 int "TIMER 8 Interrupt"
165 default 10
166config IRQ_TIMER9
167 int "TIMER 9 Interrupt"
168 default 10
169config IRQ_TIMER10
170 int "TIMER 10 Interrupt"
171 default 10
172config IRQ_TIMER11
173 int "TIMER 11 Interrupt"
174 default 10
175config IRQ_PROG0_INTA
176 int "Programmable Flags0 A (8)"
177 default 11
178config IRQ_PROG0_INTB
179 int "Programmable Flags0 B (8)"
180 default 11
181config IRQ_PROG1_INTA
182 int "Programmable Flags1 A (8)"
183 default 11
184config IRQ_PROG1_INTB
185 int "Programmable Flags1 B (8)"
186 default 11
187config IRQ_PROG2_INTA
188 int "Programmable Flags2 A (8)"
189 default 11
190config IRQ_PROG2_INTB
191 int "Programmable Flags2 B (8)"
192 default 11
193config IRQ_DMA1_WRRD0
194 int "MDMA1 0 write/read INT"
195 default 8
196config IRQ_DMA1_WRRD1
197 int "MDMA1 1 write/read INT"
198 default 8
199config IRQ_DMA2_WRRD0
200 int "MDMA2 0 write/read INT"
201 default 9
202config IRQ_DMA2_WRRD1
203 int "MDMA2 1 write/read INT"
204 default 9
205config IRQ_IMDMA_WRRD0
206 int "IMDMA 0 write/read INT"
207 default 12
208config IRQ_IMDMA_WRRD1
209 int "IMDMA 1 write/read INT"
210 default 12
211config IRQ_WDTIMER
212 int "Watch Dog Timer"
213 default 13
214
215 help
216 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
217 This applies to all the above. It is not recommended to assign the
218 highest priority number 7 to UART or any other device.
219
220endmenu
221
222endmenu
223
224endif