Haojian Zhuang | fa8962a | 2013-12-11 15:54:51 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Hisilicon Ltd. Hi3620 SoC |
| 3 | * |
| 4 | * Copyright (C) 2012-2013 Hisilicon Ltd. |
| 5 | * Copyright (C) 2012-2013 Linaro Ltd. |
| 6 | * |
| 7 | * Author: Haojian Zhuang <haojian.zhuang@linaro.org> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * publishhed by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | /include/ "skeleton.dtsi" |
| 15 | |
| 16 | / { |
| 17 | aliases { |
| 18 | serial0 = &uart0; |
| 19 | serial1 = &uart1; |
| 20 | serial2 = &uart2; |
| 21 | serial3 = &uart3; |
| 22 | serial4 = &uart4; |
| 23 | }; |
| 24 | |
| 25 | pclk: clk { |
| 26 | compatible = "fixed-clock"; |
| 27 | #clock-cells = <0>; |
| 28 | clock-frequency = <26000000>; |
| 29 | clock-output-names = "apb_pclk"; |
| 30 | }; |
| 31 | |
| 32 | cpus { |
| 33 | #address-cells = <1>; |
| 34 | #size-cells = <0>; |
| 35 | |
| 36 | cpu@0 { |
| 37 | device_type = "cpu"; |
| 38 | compatible = "arm,cortex-a9"; |
| 39 | reg = <0x0>; |
| 40 | next-level-cache = <&L2>; |
| 41 | }; |
| 42 | }; |
| 43 | |
| 44 | amba { |
| 45 | #address-cells = <1>; |
| 46 | #size-cells = <1>; |
| 47 | compatible = "arm,amba-bus"; |
| 48 | interrupt-parent = <&gic>; |
| 49 | ranges = <0 0xfc000000 0x2000000>; |
| 50 | |
| 51 | L2: l2-cache { |
| 52 | compatible = "arm,pl310-cache"; |
| 53 | reg = <0xfc10000 0x100000>; |
| 54 | interrupts = <0 15 4>; |
| 55 | cache-unified; |
| 56 | cache-level = <2>; |
| 57 | }; |
| 58 | |
| 59 | gic: interrupt-controller@1000 { |
| 60 | compatible = "arm,cortex-a9-gic"; |
| 61 | #interrupt-cells = <3>; |
| 62 | #address-cells = <0>; |
| 63 | interrupt-controller; |
| 64 | /* gic dist base, gic cpu base */ |
| 65 | reg = <0x1000 0x1000>, <0x100 0x100>; |
| 66 | }; |
| 67 | |
| 68 | dual_timer0: dual_timer@800000 { |
| 69 | compatible = "arm,sp804", "arm,primecell"; |
| 70 | reg = <0x800000 0x1000>; |
| 71 | /* timer00 & timer01 */ |
| 72 | interrupts = <0 0 4>, <0 1 4>; |
| 73 | clocks = <&pclk>; |
| 74 | clock-names = "apb_pclk"; |
| 75 | status = "disabled"; |
| 76 | }; |
| 77 | |
| 78 | dual_timer1: dual_timer@801000 { |
| 79 | compatible = "arm,sp804", "arm,primecell"; |
| 80 | reg = <0x801000 0x1000>; |
| 81 | /* timer10 & timer11 */ |
| 82 | interrupts = <0 2 4>, <0 3 4>; |
| 83 | clocks = <&pclk>; |
| 84 | clock-names = "apb_pclk"; |
| 85 | status = "disabled"; |
| 86 | }; |
| 87 | |
| 88 | dual_timer2: dual_timer@a01000 { |
| 89 | compatible = "arm,sp804", "arm,primecell"; |
| 90 | reg = <0xa01000 0x1000>; |
| 91 | /* timer20 & timer21 */ |
| 92 | interrupts = <0 4 4>, <0 5 4>; |
| 93 | clocks = <&pclk>; |
| 94 | clock-names = "apb_pclk"; |
| 95 | status = "disabled"; |
| 96 | }; |
| 97 | |
| 98 | dual_timer3: dual_timer@a02000 { |
| 99 | compatible = "arm,sp804", "arm,primecell"; |
| 100 | reg = <0xa02000 0x1000>; |
| 101 | /* timer30 & timer31 */ |
| 102 | interrupts = <0 6 4>, <0 7 4>; |
| 103 | clocks = <&pclk>; |
| 104 | clock-names = "apb_pclk"; |
| 105 | status = "disabled"; |
| 106 | }; |
| 107 | |
| 108 | dual_timer4: dual_timer@a03000 { |
| 109 | compatible = "arm,sp804", "arm,primecell"; |
| 110 | reg = <0xa03000 0x1000>; |
| 111 | /* timer40 & timer41 */ |
| 112 | interrupts = <0 96 4>, <0 97 4>; |
| 113 | clocks = <&pclk>; |
| 114 | clock-names = "apb_pclk"; |
| 115 | status = "disabled"; |
| 116 | }; |
| 117 | |
| 118 | uart0: uart@b00000 { |
| 119 | compatible = "arm,pl011", "arm,primecell"; |
| 120 | reg = <0xb00000 0x1000>; |
| 121 | interrupts = <0 20 4>; |
| 122 | clocks = <&pclk>; |
| 123 | clock-names = "apb_pclk"; |
| 124 | status = "disabled"; |
| 125 | }; |
| 126 | |
| 127 | uart1: uart@b01000 { |
| 128 | compatible = "arm,pl011", "arm,primecell"; |
| 129 | reg = <0xb01000 0x1000>; |
| 130 | interrupts = <0 21 4>; |
| 131 | clocks = <&pclk>; |
| 132 | clock-names = "apb_pclk"; |
| 133 | status = "disabled"; |
| 134 | }; |
| 135 | |
| 136 | uart2: uart@b02000 { |
| 137 | compatible = "arm,pl011", "arm,primecell"; |
| 138 | reg = <0xb02000 0x1000>; |
| 139 | interrupts = <0 22 4>; |
| 140 | clocks = <&pclk>; |
| 141 | clock-names = "apb_pclk"; |
| 142 | status = "disabled"; |
| 143 | }; |
| 144 | |
| 145 | uart3: uart@b03000 { |
| 146 | compatible = "arm,pl011", "arm,primecell"; |
| 147 | reg = <0xb03000 0x1000>; |
| 148 | interrupts = <0 23 4>; |
| 149 | clocks = <&pclk>; |
| 150 | clock-names = "apb_pclk"; |
| 151 | status = "disabled"; |
| 152 | }; |
| 153 | |
| 154 | uart4: uart@b04000 { |
| 155 | compatible = "arm,pl011", "arm,primecell"; |
| 156 | reg = <0xb04000 0x1000>; |
| 157 | interrupts = <0 24 4>; |
| 158 | clocks = <&pclk>; |
| 159 | clock-names = "apb_pclk"; |
| 160 | status = "disabled"; |
| 161 | }; |
| 162 | |
| 163 | gpio0: gpio@806000 { |
| 164 | compatible = "arm,pl061", "arm,primecell"; |
| 165 | reg = <0x806000 0x1000>; |
| 166 | interrupts = <0 64 0x4>; |
| 167 | gpio-controller; |
| 168 | #gpio-cells = <2>; |
| 169 | gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1 |
| 170 | &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>; |
| 171 | interrupt-controller; |
| 172 | #interrupt-cells = <2>; |
| 173 | clocks = <&pclk>; |
| 174 | clock-names = "apb_pclk"; |
| 175 | }; |
| 176 | |
| 177 | gpio1: gpio@807000 { |
| 178 | compatible = "arm,pl061", "arm,primecell"; |
| 179 | reg = <0x807000 0x1000>; |
| 180 | interrupts = <0 65 0x4>; |
| 181 | gpio-controller; |
| 182 | #gpio-cells = <2>; |
| 183 | gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 |
| 184 | &pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1 |
| 185 | &pmx0 6 5 1 &pmx0 7 6 1>; |
| 186 | interrupt-controller; |
| 187 | #interrupt-cells = <2>; |
| 188 | clocks = <&pclk>; |
| 189 | clock-names = "apb_pclk"; |
| 190 | }; |
| 191 | |
| 192 | gpio2: gpio@808000 { |
| 193 | compatible = "arm,pl061", "arm,primecell"; |
| 194 | reg = <0x808000 0x1000>; |
| 195 | interrupts = <0 66 0x4>; |
| 196 | gpio-controller; |
| 197 | #gpio-cells = <2>; |
| 198 | gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1 |
| 199 | &pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1 |
| 200 | &pmx0 6 3 1 &pmx0 7 3 1>; |
| 201 | interrupt-controller; |
| 202 | #interrupt-cells = <2>; |
| 203 | clocks = <&pclk>; |
| 204 | clock-names = "apb_pclk"; |
| 205 | }; |
| 206 | |
| 207 | gpio3: gpio@809000 { |
| 208 | compatible = "arm,pl061", "arm,primecell"; |
| 209 | reg = <0x809000 0x1000>; |
| 210 | interrupts = <0 67 0x4>; |
| 211 | gpio-controller; |
| 212 | #gpio-cells = <2>; |
| 213 | gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1 |
| 214 | &pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1 |
| 215 | &pmx0 6 11 1 &pmx0 7 11 1>; |
| 216 | interrupt-controller; |
| 217 | #interrupt-cells = <2>; |
| 218 | clocks = <&pclk>; |
| 219 | clock-names = "apb_pclk"; |
| 220 | }; |
| 221 | |
| 222 | gpio4: gpio@80a000 { |
| 223 | compatible = "arm,pl061", "arm,primecell"; |
| 224 | reg = <0x80a000 0x1000>; |
| 225 | interrupts = <0 68 0x4>; |
| 226 | gpio-controller; |
| 227 | #gpio-cells = <2>; |
| 228 | gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1 |
| 229 | &pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1 |
| 230 | &pmx0 6 13 1 &pmx0 7 13 1>; |
| 231 | interrupt-controller; |
| 232 | #interrupt-cells = <2>; |
| 233 | clocks = <&pclk>; |
| 234 | clock-names = "apb_pclk"; |
| 235 | }; |
| 236 | |
| 237 | gpio5: gpio@80b000 { |
| 238 | compatible = "arm,pl061", "arm,primecell"; |
| 239 | reg = <0x80b000 0x1000>; |
| 240 | interrupts = <0 69 0x4>; |
| 241 | gpio-controller; |
| 242 | #gpio-cells = <2>; |
| 243 | gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1 |
| 244 | &pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1 |
| 245 | &pmx0 6 16 1 &pmx0 7 16 1>; |
| 246 | interrupt-controller; |
| 247 | #interrupt-cells = <2>; |
| 248 | clocks = <&pclk>; |
| 249 | clock-names = "apb_pclk"; |
| 250 | }; |
| 251 | |
| 252 | gpio6: gpio@80c000 { |
| 253 | compatible = "arm,pl061", "arm,primecell"; |
| 254 | reg = <0x80c000 0x1000>; |
| 255 | interrupts = <0 70 0x4>; |
| 256 | gpio-controller; |
| 257 | #gpio-cells = <2>; |
| 258 | gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1 |
| 259 | &pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1 |
| 260 | &pmx0 6 18 1 &pmx0 7 19 1>; |
| 261 | interrupt-controller; |
| 262 | #interrupt-cells = <2>; |
| 263 | clocks = <&pclk>; |
| 264 | clock-names = "apb_pclk"; |
| 265 | }; |
| 266 | |
| 267 | gpio7: gpio@80d000 { |
| 268 | compatible = "arm,pl061", "arm,primecell"; |
| 269 | reg = <0x80d000 0x1000>; |
| 270 | interrupts = <0 71 0x4>; |
| 271 | gpio-controller; |
| 272 | #gpio-cells = <2>; |
| 273 | gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1 |
| 274 | &pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1 |
| 275 | &pmx0 6 25 1 &pmx0 7 26 1>; |
| 276 | interrupt-controller; |
| 277 | #interrupt-cells = <2>; |
| 278 | clocks = <&pclk>; |
| 279 | clock-names = "apb_pclk"; |
| 280 | }; |
| 281 | |
| 282 | gpio8: gpio@80e000 { |
| 283 | compatible = "arm,pl061", "arm,primecell"; |
| 284 | reg = <0x80e000 0x1000>; |
| 285 | interrupts = <0 72 0x4>; |
| 286 | gpio-controller; |
| 287 | #gpio-cells = <2>; |
| 288 | gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1 |
| 289 | &pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1 |
| 290 | &pmx0 6 33 1 &pmx0 7 34 1>; |
| 291 | interrupt-controller; |
| 292 | #interrupt-cells = <2>; |
| 293 | clocks = <&pclk>; |
| 294 | clock-names = "apb_pclk"; |
| 295 | }; |
| 296 | |
| 297 | gpio9: gpio@80f000 { |
| 298 | compatible = "arm,pl061", "arm,primecell"; |
| 299 | reg = <0x80f000 0x1000>; |
| 300 | interrupts = <0 73 0x4>; |
| 301 | gpio-controller; |
| 302 | #gpio-cells = <2>; |
| 303 | gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1 |
| 304 | &pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1 |
| 305 | &pmx0 6 41 1>; |
| 306 | interrupt-controller; |
| 307 | #interrupt-cells = <2>; |
| 308 | clocks = <&pclk>; |
| 309 | clock-names = "apb_pclk"; |
| 310 | }; |
| 311 | |
| 312 | gpio10: gpio@810000 { |
| 313 | compatible = "arm,pl061", "arm,primecell"; |
| 314 | reg = <0x810000 0x1000>; |
| 315 | interrupts = <0 74 0x4>; |
| 316 | gpio-controller; |
| 317 | #gpio-cells = <2>; |
| 318 | gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1 |
| 319 | &pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>; |
| 320 | interrupt-controller; |
| 321 | #interrupt-cells = <2>; |
| 322 | clocks = <&pclk>; |
| 323 | clock-names = "apb_pclk"; |
| 324 | }; |
| 325 | |
| 326 | gpio11: gpio@811000 { |
| 327 | compatible = "arm,pl061", "arm,primecell"; |
| 328 | reg = <0x811000 0x1000>; |
| 329 | interrupts = <0 75 0x4>; |
| 330 | gpio-controller; |
| 331 | #gpio-cells = <2>; |
| 332 | gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1 |
| 333 | &pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1 |
| 334 | &pmx0 6 49 1 &pmx0 7 49 1>; |
| 335 | interrupt-controller; |
| 336 | #interrupt-cells = <2>; |
| 337 | clocks = <&pclk>; |
| 338 | clock-names = "apb_pclk"; |
| 339 | }; |
| 340 | |
| 341 | gpio12: gpio@812000 { |
| 342 | compatible = "arm,pl061", "arm,primecell"; |
| 343 | reg = <0x812000 0x1000>; |
| 344 | interrupts = <0 76 0x4>; |
| 345 | gpio-controller; |
| 346 | #gpio-cells = <2>; |
| 347 | gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1 |
| 348 | &pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1 |
| 349 | &pmx0 6 51 1 &pmx0 7 52 1>; |
| 350 | interrupt-controller; |
| 351 | #interrupt-cells = <2>; |
| 352 | clocks = <&pclk>; |
| 353 | clock-names = "apb_pclk"; |
| 354 | }; |
| 355 | |
| 356 | gpio13: gpio@813000 { |
| 357 | compatible = "arm,pl061", "arm,primecell"; |
| 358 | reg = <0x813000 0x1000>; |
| 359 | interrupts = <0 77 0x4>; |
| 360 | gpio-controller; |
| 361 | #gpio-cells = <2>; |
| 362 | gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1 |
| 363 | &pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1 |
| 364 | &pmx0 6 55 1 &pmx0 7 56 1>; |
| 365 | interrupt-controller; |
| 366 | #interrupt-cells = <2>; |
| 367 | clocks = <&pclk>; |
| 368 | clock-names = "apb_pclk"; |
| 369 | }; |
| 370 | |
| 371 | gpio14: gpio@814000 { |
| 372 | compatible = "arm,pl061", "arm,primecell"; |
| 373 | reg = <0x814000 0x1000>; |
| 374 | interrupts = <0 78 0x4>; |
| 375 | gpio-controller; |
| 376 | #gpio-cells = <2>; |
| 377 | gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1 |
| 378 | &pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1 |
| 379 | &pmx0 6 60 1 &pmx0 7 61 1>; |
| 380 | interrupt-controller; |
| 381 | #interrupt-cells = <2>; |
| 382 | clocks = <&pclk>; |
| 383 | clock-names = "apb_pclk"; |
| 384 | }; |
| 385 | |
| 386 | gpio15: gpio@815000 { |
| 387 | compatible = "arm,pl061", "arm,primecell"; |
| 388 | reg = <0x815000 0x1000>; |
| 389 | interrupts = <0 79 0x4>; |
| 390 | gpio-controller; |
| 391 | #gpio-cells = <2>; |
| 392 | gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1 |
| 393 | &pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1 |
| 394 | &pmx0 6 64 1 &pmx0 7 65 1>; |
| 395 | interrupt-controller; |
| 396 | #interrupt-cells = <2>; |
| 397 | clocks = <&pclk>; |
| 398 | clock-names = "apb_pclk"; |
| 399 | }; |
| 400 | |
| 401 | gpio16: gpio@816000 { |
| 402 | compatible = "arm,pl061", "arm,primecell"; |
| 403 | reg = <0x816000 0x1000>; |
| 404 | interrupts = <0 80 0x4>; |
| 405 | gpio-controller; |
| 406 | #gpio-cells = <2>; |
| 407 | gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1 |
| 408 | &pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1 |
| 409 | &pmx0 6 72 1 &pmx0 7 73 1>; |
| 410 | interrupt-controller; |
| 411 | #interrupt-cells = <2>; |
| 412 | clocks = <&pclk>; |
| 413 | clock-names = "apb_pclk"; |
| 414 | }; |
| 415 | |
| 416 | gpio17: gpio@817000 { |
| 417 | compatible = "arm,pl061", "arm,primecell"; |
| 418 | reg = <0x817000 0x1000>; |
| 419 | interrupts = <0 81 0x4>; |
| 420 | gpio-controller; |
| 421 | #gpio-cells = <2>; |
| 422 | gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1 |
| 423 | &pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1 |
| 424 | &pmx0 6 80 1 &pmx0 7 81 1>; |
| 425 | interrupt-controller; |
| 426 | #interrupt-cells = <2>; |
| 427 | clocks = <&pclk>; |
| 428 | clock-names = "apb_pclk"; |
| 429 | }; |
| 430 | |
| 431 | gpio18: gpio@818000 { |
| 432 | compatible = "arm,pl061", "arm,primecell"; |
| 433 | reg = <0x818000 0x1000>; |
| 434 | interrupts = <0 82 0x4>; |
| 435 | gpio-controller; |
| 436 | #gpio-cells = <2>; |
| 437 | gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1 |
| 438 | &pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1 |
| 439 | &pmx0 6 86 1 &pmx0 7 87 1>; |
| 440 | interrupt-controller; |
| 441 | #interrupt-cells = <2>; |
| 442 | clocks = <&pclk>; |
| 443 | clock-names = "apb_pclk"; |
| 444 | }; |
| 445 | |
| 446 | gpio19: gpio@819000 { |
| 447 | compatible = "arm,pl061", "arm,primecell"; |
| 448 | reg = <0x819000 0x1000>; |
| 449 | interrupts = <0 83 0x4>; |
| 450 | gpio-controller; |
| 451 | #gpio-cells = <2>; |
| 452 | gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1 |
| 453 | &pmx0 3 88 1>; |
| 454 | interrupt-controller; |
| 455 | #interrupt-cells = <2>; |
| 456 | clocks = <&pclk>; |
| 457 | clock-names = "apb_pclk"; |
| 458 | }; |
| 459 | |
| 460 | gpio20: gpio@81a000 { |
| 461 | compatible = "arm,pl061", "arm,primecell"; |
| 462 | reg = <0x81a000 0x1000>; |
| 463 | interrupts = <0 84 0x4>; |
| 464 | gpio-controller; |
| 465 | #gpio-cells = <2>; |
| 466 | gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1 |
| 467 | &pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>; |
| 468 | interrupt-controller; |
| 469 | #interrupt-cells = <2>; |
| 470 | clocks = <&pclk>; |
| 471 | clock-names = "apb_pclk"; |
| 472 | }; |
| 473 | |
| 474 | gpio21: gpio@81b000 { |
| 475 | compatible = "arm,pl061", "arm,primecell"; |
| 476 | reg = <0x81b000 0x1000>; |
| 477 | interrupts = <0 85 0x4>; |
| 478 | gpio-controller; |
| 479 | #gpio-cells = <2>; |
| 480 | gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>; |
| 481 | interrupt-controller; |
| 482 | #interrupt-cells = <2>; |
| 483 | clocks = <&pclk>; |
| 484 | clock-names = "apb_pclk"; |
| 485 | }; |
| 486 | |
| 487 | pmx0: pinmux@803000 { |
| 488 | compatible = "pinctrl-single"; |
| 489 | reg = <0x803000 0x188>; |
| 490 | #address-cells = <1>; |
| 491 | #size-cells = <1>; |
| 492 | #gpio-range-cells = <3>; |
| 493 | ranges; |
| 494 | |
| 495 | pinctrl-single,register-width = <32>; |
| 496 | pinctrl-single,function-mask = <7>; |
| 497 | /* pin base, nr pins & gpio function */ |
| 498 | pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1 |
| 499 | &range 12 1 0 &range 13 29 1 |
| 500 | &range 43 1 0 &range 44 49 1 |
| 501 | &range 94 1 1 &range 96 2 1>; |
| 502 | |
| 503 | range: gpio-range { |
| 504 | #pinctrl-single,gpio-range-cells = <3>; |
| 505 | }; |
| 506 | }; |
| 507 | |
| 508 | pmx1: pinmux@803800 { |
| 509 | compatible = "pinconf-single"; |
| 510 | reg = <0x803800 0x2dc>; |
| 511 | #address-cells = <1>; |
| 512 | #size-cells = <1>; |
| 513 | ranges; |
| 514 | |
| 515 | pinctrl-single,register-width = <32>; |
| 516 | }; |
| 517 | }; |
| 518 | }; |