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Tony Lindgren046d6b22005-11-10 14:26:52 +00001/*
Paul Walmsley8c810e72011-02-25 13:56:40 -07002 * OMAP2420 clock data
Tony Lindgren046d6b22005-11-10 14:26:52 +00003 *
Paul Walmsley8c810e72011-02-25 13:56:40 -07004 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
Tony Lindgrena16e9702008-03-18 11:56:39 +02006 *
Paul Walmsley8c810e72011-02-25 13:56:40 -07007 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
Tony Lindgren046d6b22005-11-10 14:26:52 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
Paul Walmsleyd8a94452009-12-08 16:21:29 -070016#include <linux/kernel.h>
17#include <linux/clk.h>
Paul Walmsley93340a22010-02-22 22:09:12 -070018#include <linux/list.h>
Paul Walmsleyd8a94452009-12-08 16:21:29 -070019
20#include <plat/clkdev_omap.h>
Tony Lindgren046d6b22005-11-10 14:26:52 +000021
Paul Walmsley6b8858a2008-03-18 10:35:15 +020022#include "clock.h"
Paul Walmsleyd8a94452009-12-08 16:21:29 -070023#include "clock2xxx.h"
24#include "opp2xxx.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -070025#include "cm2xxx_3xxx.h"
26#include "prm2xxx_3xxx.h"
Paul Walmsley6b8858a2008-03-18 10:35:15 +020027#include "prm-regbits-24xx.h"
28#include "cm-regbits-24xx.h"
29#include "sdrc.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060030#include "control.h"
Paul Walmsley6b8858a2008-03-18 10:35:15 +020031
Paul Walmsley81b34fb2010-02-22 22:09:22 -070032#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
33
34/*
35 * 2420 clock tree.
Tony Lindgren046d6b22005-11-10 14:26:52 +000036 *
Paul Walmsley8c810e72011-02-25 13:56:40 -070037 * NOTE:In many cases here we are assigning a 'default' parent. In
38 * many cases the parent is selectable. The set parent calls will
39 * also switch sources.
Tony Lindgren046d6b22005-11-10 14:26:52 +000040 *
41 * Several sources are given initial rates which may be wrong, this will
42 * be fixed up in the init func.
43 *
44 * Things are broadly separated below by clock domains. It is
Paul Walmsley8c810e72011-02-25 13:56:40 -070045 * noteworthy that most peripherals have dependencies on multiple clock
Tony Lindgren046d6b22005-11-10 14:26:52 +000046 * domains. Many get their interface clocks from the L4 domain, but get
47 * functional clocks from fixed sources or other core domain derived
48 * clocks.
Paul Walmsley81b34fb2010-02-22 22:09:22 -070049 */
Tony Lindgren046d6b22005-11-10 14:26:52 +000050
51/* Base external input clocks */
52static struct clk func_32k_ck = {
53 .name = "func_32k_ck",
Russell King897dcde2008-11-04 16:35:03 +000054 .ops = &clkops_null,
Paul Walmsley3f9cfd32011-02-16 15:38:38 -070055 .rate = 32768,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +030056 .clkdm_name = "wkup_clkdm",
Tony Lindgren046d6b22005-11-10 14:26:52 +000057};
Paul Walmsleye32744b2008-03-18 15:47:55 +020058
Paul Walmsleyf2480762009-04-23 21:11:10 -060059static struct clk secure_32k_ck = {
60 .name = "secure_32k_ck",
61 .ops = &clkops_null,
62 .rate = 32768,
Paul Walmsleyf2480762009-04-23 21:11:10 -060063 .clkdm_name = "wkup_clkdm",
64};
65
Tony Lindgren046d6b22005-11-10 14:26:52 +000066/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
67static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
68 .name = "osc_ck",
Russell King548d8492008-11-04 14:02:46 +000069 .ops = &clkops_oscck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +030070 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +020071 .recalc = &omap2_osc_clk_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +000072};
73
Paul Walmsleyd1b03f62008-08-19 11:08:44 +030074/* Without modem likely 12MHz, with modem likely 13MHz */
Tony Lindgren046d6b22005-11-10 14:26:52 +000075static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
76 .name = "sys_ck", /* ~ ref_clk also */
Russell King897dcde2008-11-04 16:35:03 +000077 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +000078 .parent = &osc_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +030079 .clkdm_name = "wkup_clkdm",
Paul Walmsley44da0a52010-01-26 20:13:08 -070080 .recalc = &omap2xxx_sys_clk_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +000081};
Paul Walmsleye32744b2008-03-18 15:47:55 +020082
Tony Lindgren046d6b22005-11-10 14:26:52 +000083static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
84 .name = "alt_ck",
Russell King897dcde2008-11-04 16:35:03 +000085 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +000086 .rate = 54000000,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +030087 .clkdm_name = "wkup_clkdm",
Tony Lindgren046d6b22005-11-10 14:26:52 +000088};
Paul Walmsleye32744b2008-03-18 15:47:55 +020089
Paul Walmsley1bccb342010-10-08 11:40:17 -060090/* Optional external clock input for McBSP CLKS */
91static struct clk mcbsp_clks = {
92 .name = "mcbsp_clks",
93 .ops = &clkops_null,
94};
95
Tony Lindgren046d6b22005-11-10 14:26:52 +000096/*
97 * Analog domain root source clocks
98 */
99
100/* dpll_ck, is broken out in to special cases through clksel */
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200101/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
102 * deal with this
103 */
104
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300105static struct dpll_data dpll_dd = {
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200106 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
107 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
108 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
Russell Kingc0bf3132009-02-19 13:29:22 +0000109 .clk_bypass = &sys_ck,
110 .clk_ref = &sys_ck,
111 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
112 .enable_mask = OMAP24XX_EN_DPLL_MASK,
Paul Walmsley93340a22010-02-22 22:09:12 -0700113 .max_multiplier = 1023,
Paul Walmsley95f538a2009-01-28 12:08:44 -0700114 .min_divider = 1,
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300115 .max_divider = 16,
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200116};
117
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300118/*
119 * XXX Cannot add round_rate here yet, as this is still a composite clock,
120 * not just a DPLL
121 */
Tony Lindgren046d6b22005-11-10 14:26:52 +0000122static struct clk dpll_ck = {
123 .name = "dpll_ck",
Paul Walmsley0fd0c212011-02-25 15:49:53 -0700124 .ops = &clkops_omap2xxx_dpll_ops,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000125 .parent = &sys_ck, /* Can be func_32k also */
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200126 .dpll_data = &dpll_dd,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300127 .clkdm_name = "wkup_clkdm",
Paul Walmsley88b8ba92008-07-03 12:24:46 +0300128 .recalc = &omap2_dpllcore_recalc,
129 .set_rate = &omap2_reprogram_dpllcore,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000130};
131
132static struct clk apll96_ck = {
133 .name = "apll96_ck",
Paul Walmsley06b16932009-12-08 16:18:46 -0700134 .ops = &clkops_apll96,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000135 .parent = &sys_ck,
136 .rate = 96000000,
Paul Walmsley51c19542010-02-22 22:09:26 -0700137 .flags = ENABLE_ON_INIT,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300138 .clkdm_name = "wkup_clkdm",
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200139 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
140 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000141};
142
143static struct clk apll54_ck = {
144 .name = "apll54_ck",
Paul Walmsley06b16932009-12-08 16:18:46 -0700145 .ops = &clkops_apll54,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000146 .parent = &sys_ck,
147 .rate = 54000000,
Paul Walmsley51c19542010-02-22 22:09:26 -0700148 .flags = ENABLE_ON_INIT,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300149 .clkdm_name = "wkup_clkdm",
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200150 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
151 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000152};
153
154/*
155 * PRCM digital base sources
156 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200157
158/* func_54m_ck */
159
160static const struct clksel_rate func_54m_apll54_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600161 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200162 { .div = 0 },
163};
164
165static const struct clksel_rate func_54m_alt_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600166 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200167 { .div = 0 },
168};
169
170static const struct clksel func_54m_clksel[] = {
171 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
172 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
173 { .parent = NULL },
174};
175
Tony Lindgren046d6b22005-11-10 14:26:52 +0000176static struct clk func_54m_ck = {
177 .name = "func_54m_ck",
Russell King57137182008-11-04 16:48:35 +0000178 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000179 .parent = &apll54_ck, /* can also be alt_clk */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300180 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200181 .init = &omap2_init_clksel_parent,
182 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
Paul Walmsleyf38ca102010-05-20 12:31:04 -0600183 .clksel_mask = OMAP24XX_54M_SOURCE_MASK,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200184 .clksel = func_54m_clksel,
185 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000186};
Paul Walmsleye32744b2008-03-18 15:47:55 +0200187
Tony Lindgren046d6b22005-11-10 14:26:52 +0000188static struct clk core_ck = {
189 .name = "core_ck",
Russell King897dcde2008-11-04 16:35:03 +0000190 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000191 .parent = &dpll_ck, /* can also be 32k */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300192 .clkdm_name = "wkup_clkdm",
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200193 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000194};
Paul Walmsleye32744b2008-03-18 15:47:55 +0200195
Tony Lindgren046d6b22005-11-10 14:26:52 +0000196static struct clk func_96m_ck = {
197 .name = "func_96m_ck",
Russell King57137182008-11-04 16:48:35 +0000198 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000199 .parent = &apll96_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300200 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700201 .recalc = &followparent_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200202};
203
204/* func_48m_ck */
205
206static const struct clksel_rate func_48m_apll96_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600207 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200208 { .div = 0 },
209};
210
211static const struct clksel_rate func_48m_alt_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600212 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200213 { .div = 0 },
214};
215
216static const struct clksel func_48m_clksel[] = {
217 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
218 { .parent = &alt_ck, .rates = func_48m_alt_rates },
219 { .parent = NULL }
Tony Lindgren046d6b22005-11-10 14:26:52 +0000220};
221
222static struct clk func_48m_ck = {
223 .name = "func_48m_ck",
Russell King57137182008-11-04 16:48:35 +0000224 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000225 .parent = &apll96_ck, /* 96M or Alt */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300226 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200227 .init = &omap2_init_clksel_parent,
228 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
Paul Walmsleyf38ca102010-05-20 12:31:04 -0600229 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200230 .clksel = func_48m_clksel,
231 .recalc = &omap2_clksel_recalc,
232 .round_rate = &omap2_clksel_round_rate,
233 .set_rate = &omap2_clksel_set_rate
Tony Lindgren046d6b22005-11-10 14:26:52 +0000234};
235
236static struct clk func_12m_ck = {
237 .name = "func_12m_ck",
Russell King57137182008-11-04 16:48:35 +0000238 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000239 .parent = &func_48m_ck,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200240 .fixed_div = 4,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300241 .clkdm_name = "wkup_clkdm",
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700242 .recalc = &omap_fixed_divisor_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000243};
244
245/* Secure timer, only available in secure mode */
246static struct clk wdt1_osc_ck = {
247 .name = "ck_wdt1_osc",
Russell King897dcde2008-11-04 16:35:03 +0000248 .ops = &clkops_null, /* RMK: missing? */
Tony Lindgren046d6b22005-11-10 14:26:52 +0000249 .parent = &osc_ck,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200250 .recalc = &followparent_recalc,
251};
252
253/*
254 * The common_clkout* clksel_rate structs are common to
255 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
256 * sys_clkout2_* are 2420-only, so the
257 * clksel_rate flags fields are inaccurate for those clocks. This is
258 * harmless since access to those clocks are gated by the struct clk
259 * flags fields, which mark them as 2420-only.
260 */
261static const struct clksel_rate common_clkout_src_core_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600262 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200263 { .div = 0 }
264};
265
266static const struct clksel_rate common_clkout_src_sys_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600267 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200268 { .div = 0 }
269};
270
271static const struct clksel_rate common_clkout_src_96m_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600272 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200273 { .div = 0 }
274};
275
276static const struct clksel_rate common_clkout_src_54m_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600277 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200278 { .div = 0 }
279};
280
281static const struct clksel common_clkout_src_clksel[] = {
282 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
283 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
284 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
285 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
286 { .parent = NULL }
287};
288
289static struct clk sys_clkout_src = {
290 .name = "sys_clkout_src",
Russell Kingc1168dc2008-11-04 21:24:00 +0000291 .ops = &clkops_omap2_dflt,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200292 .parent = &func_54m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300293 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700294 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200295 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
296 .init = &omap2_init_clksel_parent,
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700297 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200298 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
299 .clksel = common_clkout_src_clksel,
300 .recalc = &omap2_clksel_recalc,
301 .round_rate = &omap2_clksel_round_rate,
302 .set_rate = &omap2_clksel_set_rate
303};
304
305static const struct clksel_rate common_clkout_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600306 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200307 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
308 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
309 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
310 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
311 { .div = 0 },
312};
313
314static const struct clksel sys_clkout_clksel[] = {
315 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
316 { .parent = NULL }
Tony Lindgren046d6b22005-11-10 14:26:52 +0000317};
318
319static struct clk sys_clkout = {
320 .name = "sys_clkout",
Russell King57137182008-11-04 16:48:35 +0000321 .ops = &clkops_null,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200322 .parent = &sys_clkout_src,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300323 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700324 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200325 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
326 .clksel = sys_clkout_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000327 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200328 .round_rate = &omap2_clksel_round_rate,
329 .set_rate = &omap2_clksel_set_rate
330};
331
332/* In 2430, new in 2420 ES2 */
333static struct clk sys_clkout2_src = {
334 .name = "sys_clkout2_src",
Russell Kingc1168dc2008-11-04 21:24:00 +0000335 .ops = &clkops_omap2_dflt,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200336 .parent = &func_54m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300337 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700338 .enable_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200339 .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
340 .init = &omap2_init_clksel_parent,
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700341 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200342 .clksel_mask = OMAP2420_CLKOUT2_SOURCE_MASK,
343 .clksel = common_clkout_src_clksel,
344 .recalc = &omap2_clksel_recalc,
345 .round_rate = &omap2_clksel_round_rate,
346 .set_rate = &omap2_clksel_set_rate
347};
348
349static const struct clksel sys_clkout2_clksel[] = {
350 { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
351 { .parent = NULL }
Tony Lindgren046d6b22005-11-10 14:26:52 +0000352};
353
354/* In 2430, new in 2420 ES2 */
355static struct clk sys_clkout2 = {
356 .name = "sys_clkout2",
Russell King57137182008-11-04 16:48:35 +0000357 .ops = &clkops_null,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200358 .parent = &sys_clkout2_src,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300359 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700360 .clksel_reg = OMAP2420_PRCM_CLKOUT_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200361 .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
362 .clksel = sys_clkout2_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000363 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200364 .round_rate = &omap2_clksel_round_rate,
365 .set_rate = &omap2_clksel_set_rate
Tony Lindgren046d6b22005-11-10 14:26:52 +0000366};
367
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100368static struct clk emul_ck = {
369 .name = "emul_ck",
Russell Kingc1168dc2008-11-04 21:24:00 +0000370 .ops = &clkops_omap2_dflt,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100371 .parent = &func_54m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300372 .clkdm_name = "wkup_clkdm",
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700373 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200374 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
375 .recalc = &followparent_recalc,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100376
377};
Paul Walmsleye32744b2008-03-18 15:47:55 +0200378
Tony Lindgren046d6b22005-11-10 14:26:52 +0000379/*
380 * MPU clock domain
381 * Clocks:
382 * MPU_FCLK, MPU_ICLK
383 * INT_M_FCLK, INT_M_I_CLK
384 *
385 * - Individual clocks are hardware managed.
386 * - Base divider comes from: CM_CLKSEL_MPU
387 *
388 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200389static const struct clksel_rate mpu_core_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600390 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200391 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
392 { .div = 4, .val = 4, .flags = RATE_IN_242X },
393 { .div = 6, .val = 6, .flags = RATE_IN_242X },
394 { .div = 8, .val = 8, .flags = RATE_IN_242X },
395 { .div = 0 },
396};
397
398static const struct clksel mpu_clksel[] = {
399 { .parent = &core_ck, .rates = mpu_core_rates },
400 { .parent = NULL }
401};
402
Tony Lindgren046d6b22005-11-10 14:26:52 +0000403static struct clk mpu_ck = { /* Control cpu */
404 .name = "mpu_ck",
Russell King897dcde2008-11-04 16:35:03 +0000405 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000406 .parent = &core_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300407 .clkdm_name = "mpu_clkdm",
Paul Walmsley6b8858a2008-03-18 10:35:15 +0200408 .init = &omap2_init_clksel_parent,
409 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
410 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200411 .clksel = mpu_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000412 .recalc = &omap2_clksel_recalc,
413};
Paul Walmsleye32744b2008-03-18 15:47:55 +0200414
Tony Lindgren046d6b22005-11-10 14:26:52 +0000415/*
Paul Walmsley81b34fb2010-02-22 22:09:22 -0700416 * DSP (2420-UMA+IVA1) clock domain
Tony Lindgren046d6b22005-11-10 14:26:52 +0000417 * Clocks:
Tony Lindgren046d6b22005-11-10 14:26:52 +0000418 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
Paul Walmsleye32744b2008-03-18 15:47:55 +0200419 *
Tony Lindgren046d6b22005-11-10 14:26:52 +0000420 * Won't be too specific here. The core clock comes into this block
421 * it is divided then tee'ed. One branch goes directly to xyz enable
422 * controls. The other branch gets further divided by 2 then possibly
423 * routed into a synchronizer and out of clocks abc.
424 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200425static const struct clksel_rate dsp_fck_core_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600426 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200427 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
428 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
429 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
430 { .div = 6, .val = 6, .flags = RATE_IN_242X },
431 { .div = 8, .val = 8, .flags = RATE_IN_242X },
432 { .div = 12, .val = 12, .flags = RATE_IN_242X },
433 { .div = 0 },
434};
435
436static const struct clksel dsp_fck_clksel[] = {
437 { .parent = &core_ck, .rates = dsp_fck_core_rates },
438 { .parent = NULL }
439};
440
Tony Lindgren046d6b22005-11-10 14:26:52 +0000441static struct clk dsp_fck = {
442 .name = "dsp_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000443 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000444 .parent = &core_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300445 .clkdm_name = "dsp_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200446 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
447 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
448 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
449 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
450 .clksel = dsp_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000451 .recalc = &omap2_clksel_recalc,
452};
453
Paul Walmsley22411392011-02-25 15:52:04 -0700454static const struct clksel dsp_ick_clksel[] = {
455 { .parent = &dsp_fck, .rates = dsp_ick_rates },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200456 { .parent = NULL }
457};
458
Tony Lindgren046d6b22005-11-10 14:26:52 +0000459static struct clk dsp_ick = {
460 .name = "dsp_ick", /* apparently ipi and isp */
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700461 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley22411392011-02-25 15:52:04 -0700462 .parent = &dsp_fck,
463 .clkdm_name = "dsp_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200464 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
465 .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */
Paul Walmsley22411392011-02-25 15:52:04 -0700466 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
467 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
468 .clksel = dsp_ick_clksel,
469 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200470};
471
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300472/*
473 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
474 * the C54x, but which is contained in the DSP powerdomain. Does not
475 * exist on later OMAPs.
476 */
Tony Lindgren046d6b22005-11-10 14:26:52 +0000477static struct clk iva1_ifck = {
478 .name = "iva1_ifck",
Russell Kingb36ee722008-11-04 17:59:52 +0000479 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000480 .parent = &core_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300481 .clkdm_name = "iva1_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200482 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
483 .enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
484 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
485 .clksel_mask = OMAP2420_CLKSEL_IVA_MASK,
486 .clksel = dsp_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000487 .recalc = &omap2_clksel_recalc,
488};
489
490/* IVA1 mpu/int/i/f clocks are /2 of parent */
491static struct clk iva1_mpu_int_ifck = {
492 .name = "iva1_mpu_int_ifck",
Russell Kingb36ee722008-11-04 17:59:52 +0000493 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000494 .parent = &iva1_ifck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300495 .clkdm_name = "iva1_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200496 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
497 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
498 .fixed_div = 2,
Paul Walmsleye9b98f62010-01-26 20:12:57 -0700499 .recalc = &omap_fixed_divisor_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000500};
501
502/*
503 * L3 clock domain
504 * L3 clocks are used for both interface and functional clocks to
505 * multiple entities. Some of these clocks are completely managed
506 * by hardware, and some others allow software control. Hardware
507 * managed ones general are based on directly CLK_REQ signals and
508 * various auto idle settings. The functional spec sets many of these
509 * as 'tie-high' for their enables.
510 *
511 * I-CLOCKS:
512 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
513 * CAM, HS-USB.
514 * F-CLOCK
515 * SSI.
516 *
517 * GPMC memories and SDRC have timing and clock sensitive registers which
518 * may very well need notification when the clock changes. Currently for low
519 * operating points, these are taken care of in sleep.S.
520 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200521static const struct clksel_rate core_l3_core_rates[] = {
522 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
523 { .div = 2, .val = 2, .flags = RATE_IN_242X },
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600524 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200525 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
526 { .div = 8, .val = 8, .flags = RATE_IN_242X },
527 { .div = 12, .val = 12, .flags = RATE_IN_242X },
528 { .div = 16, .val = 16, .flags = RATE_IN_242X },
529 { .div = 0 }
530};
531
532static const struct clksel core_l3_clksel[] = {
533 { .parent = &core_ck, .rates = core_l3_core_rates },
534 { .parent = NULL }
535};
536
Tony Lindgren046d6b22005-11-10 14:26:52 +0000537static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
538 .name = "core_l3_ck",
Russell King897dcde2008-11-04 16:35:03 +0000539 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000540 .parent = &core_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300541 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200542 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
543 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
544 .clksel = core_l3_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000545 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200546};
547
548/* usb_l4_ick */
549static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
550 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600551 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200552 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
553 { .div = 0 }
554};
555
556static const struct clksel usb_l4_ick_clksel[] = {
557 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
558 { .parent = NULL },
Tony Lindgren046d6b22005-11-10 14:26:52 +0000559};
560
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300561/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
Tony Lindgren046d6b22005-11-10 14:26:52 +0000562static struct clk usb_l4_ick = { /* FS-USB interface clock */
563 .name = "usb_l4_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700564 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgrenfde0fd42006-01-17 15:31:18 -0800565 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300566 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200567 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
568 .enable_bit = OMAP24XX_EN_USB_SHIFT,
569 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
570 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
571 .clksel = usb_l4_ick_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000572 .recalc = &omap2_clksel_recalc,
573};
574
575/*
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300576 * L4 clock management domain
577 *
578 * This domain contains lots of interface clocks from the L4 interface, some
579 * functional clocks. Fixed APLL functional source clocks are managed in
580 * this domain.
581 */
582static const struct clksel_rate l4_core_l3_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600583 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300584 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
585 { .div = 0 }
586};
587
588static const struct clksel l4_clksel[] = {
589 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
590 { .parent = NULL }
591};
592
593static struct clk l4_ck = { /* used both as an ick and fck */
594 .name = "l4_ck",
Russell King897dcde2008-11-04 16:35:03 +0000595 .ops = &clkops_null,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300596 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300597 .clkdm_name = "core_l4_clkdm",
598 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
599 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
600 .clksel = l4_clksel,
601 .recalc = &omap2_clksel_recalc,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300602};
603
604/*
Tony Lindgren046d6b22005-11-10 14:26:52 +0000605 * SSI is in L3 management domain, its direct parent is core not l3,
606 * many core power domain entities are grouped into the L3 clock
607 * domain.
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300608 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
Tony Lindgren046d6b22005-11-10 14:26:52 +0000609 *
610 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
611 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200612static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
613 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600614 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200615 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
616 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200617 { .div = 6, .val = 6, .flags = RATE_IN_242X },
618 { .div = 8, .val = 8, .flags = RATE_IN_242X },
619 { .div = 0 }
620};
621
622static const struct clksel ssi_ssr_sst_fck_clksel[] = {
623 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
624 { .parent = NULL }
625};
626
Tony Lindgren046d6b22005-11-10 14:26:52 +0000627static struct clk ssi_ssr_sst_fck = {
628 .name = "ssi_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000629 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000630 .parent = &core_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300631 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
633 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
634 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
635 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
636 .clksel = ssi_ssr_sst_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000637 .recalc = &omap2_clksel_recalc,
638};
639
Paul Walmsley9299fd82009-01-27 19:12:54 -0700640/*
641 * Presumably this is the same as SSI_ICLK.
642 * TRM contradicts itself on what clockdomain SSI_ICLK is in
643 */
644static struct clk ssi_l4_ick = {
645 .name = "ssi_l4_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700646 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley9299fd82009-01-27 19:12:54 -0700647 .parent = &l4_ck,
648 .clkdm_name = "core_l4_clkdm",
649 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
650 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
651 .recalc = &followparent_recalc,
652};
653
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300654
Tony Lindgren046d6b22005-11-10 14:26:52 +0000655/*
656 * GFX clock domain
657 * Clocks:
658 * GFX_FCLK, GFX_ICLK
659 * GFX_CG1(2d), GFX_CG2(3d)
660 *
661 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
662 * The 2d and 3d clocks run at a hardware determined
663 * divided value of fclk.
664 *
665 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200666
667/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
668static const struct clksel gfx_fck_clksel[] = {
669 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
670 { .parent = NULL },
671};
672
Tony Lindgren046d6b22005-11-10 14:26:52 +0000673static struct clk gfx_3d_fck = {
674 .name = "gfx_3d_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000675 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000676 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300677 .clkdm_name = "gfx_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200678 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
679 .enable_bit = OMAP24XX_EN_3D_SHIFT,
680 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
681 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
682 .clksel = gfx_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000683 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200684 .round_rate = &omap2_clksel_round_rate,
685 .set_rate = &omap2_clksel_set_rate
Tony Lindgren046d6b22005-11-10 14:26:52 +0000686};
687
688static struct clk gfx_2d_fck = {
689 .name = "gfx_2d_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000690 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000691 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300692 .clkdm_name = "gfx_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200693 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
694 .enable_bit = OMAP24XX_EN_2D_SHIFT,
695 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
696 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
697 .clksel = gfx_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000698 .recalc = &omap2_clksel_recalc,
699};
700
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700701/* This interface clock does not have a CM_AUTOIDLE bit */
Tony Lindgren046d6b22005-11-10 14:26:52 +0000702static struct clk gfx_ick = {
703 .name = "gfx_ick", /* From l3 */
Russell Kingb36ee722008-11-04 17:59:52 +0000704 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000705 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300706 .clkdm_name = "gfx_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200707 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
708 .enable_bit = OMAP_EN_GFX_SHIFT,
709 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000710};
711
712/*
Tony Lindgren046d6b22005-11-10 14:26:52 +0000713 * DSS clock domain
714 * CLOCKs:
715 * DSS_L4_ICLK, DSS_L3_ICLK,
716 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
717 *
718 * DSS is both initiator and target.
719 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200720/* XXX Add RATE_NOT_VALIDATED */
721
722static const struct clksel_rate dss1_fck_sys_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600723 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200724 { .div = 0 }
725};
726
727static const struct clksel_rate dss1_fck_core_rates[] = {
728 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
729 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
730 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
731 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
732 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
733 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
734 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
735 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
736 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600737 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200738 { .div = 0 }
739};
740
741static const struct clksel dss1_fck_clksel[] = {
742 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
743 { .parent = &core_ck, .rates = dss1_fck_core_rates },
744 { .parent = NULL },
745};
746
Tony Lindgren046d6b22005-11-10 14:26:52 +0000747static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
748 .name = "dss_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700749 .ops = &clkops_omap2_iclk_dflt,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000750 .parent = &l4_ck, /* really both l3 and l4 */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300751 .clkdm_name = "dss_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200752 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
753 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
754 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000755};
756
757static struct clk dss1_fck = {
758 .name = "dss1_fck",
Russell Kingbc51da42008-11-04 18:59:32 +0000759 .ops = &clkops_omap2_dflt,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000760 .parent = &core_ck, /* Core or sys */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300761 .clkdm_name = "dss_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200762 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
763 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
764 .init = &omap2_init_clksel_parent,
765 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
766 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
767 .clksel = dss1_fck_clksel,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000768 .recalc = &omap2_clksel_recalc,
Paul Walmsleye32744b2008-03-18 15:47:55 +0200769};
770
771static const struct clksel_rate dss2_fck_sys_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600772 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200773 { .div = 0 }
774};
775
776static const struct clksel_rate dss2_fck_48m_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600777 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200778 { .div = 0 }
779};
780
781static const struct clksel dss2_fck_clksel[] = {
782 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
783 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
784 { .parent = NULL }
Tony Lindgren046d6b22005-11-10 14:26:52 +0000785};
786
787static struct clk dss2_fck = { /* Alt clk used in power management */
788 .name = "dss2_fck",
Russell Kingbc51da42008-11-04 18:59:32 +0000789 .ops = &clkops_omap2_dflt,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000790 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300791 .clkdm_name = "dss_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200792 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
793 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
794 .init = &omap2_init_clksel_parent,
795 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
796 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
797 .clksel = dss2_fck_clksel,
Paul Walmsleyd4521f62010-12-21 21:08:14 -0700798 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000799};
800
801static struct clk dss_54m_fck = { /* Alt clk used in power management */
802 .name = "dss_54m_fck", /* 54m tv clk */
Russell Kingb36ee722008-11-04 17:59:52 +0000803 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000804 .parent = &func_54m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300805 .clkdm_name = "dss_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200806 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
807 .enable_bit = OMAP24XX_EN_TV_SHIFT,
808 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000809};
810
Paul Walmsley19c1c0c2011-02-16 15:38:38 -0700811static struct clk wu_l4_ick = {
812 .name = "wu_l4_ick",
813 .ops = &clkops_null,
814 .parent = &sys_ck,
815 .clkdm_name = "wkup_clkdm",
816 .recalc = &followparent_recalc,
817};
818
Tony Lindgren046d6b22005-11-10 14:26:52 +0000819/*
820 * CORE power domain ICLK & FCLK defines.
821 * Many of the these can have more than one possible parent. Entries
822 * here will likely have an L4 interface parent, and may have multiple
823 * functional clock parents.
824 */
Paul Walmsleye32744b2008-03-18 15:47:55 +0200825static const struct clksel_rate gpt_alt_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -0600826 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
Paul Walmsleye32744b2008-03-18 15:47:55 +0200827 { .div = 0 }
828};
829
830static const struct clksel omap24xx_gpt_clksel[] = {
831 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
832 { .parent = &sys_ck, .rates = gpt_sys_rates },
833 { .parent = &alt_ck, .rates = gpt_alt_rates },
834 { .parent = NULL },
835};
836
Tony Lindgren046d6b22005-11-10 14:26:52 +0000837static struct clk gpt1_ick = {
838 .name = "gpt1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700839 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -0700840 .parent = &wu_l4_ick,
841 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200842 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
843 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
844 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000845};
846
847static struct clk gpt1_fck = {
848 .name = "gpt1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000849 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000850 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300851 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200852 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
853 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
854 .init = &omap2_init_clksel_parent,
855 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
856 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
857 .clksel = omap24xx_gpt_clksel,
858 .recalc = &omap2_clksel_recalc,
859 .round_rate = &omap2_clksel_round_rate,
860 .set_rate = &omap2_clksel_set_rate
Tony Lindgren046d6b22005-11-10 14:26:52 +0000861};
862
863static struct clk gpt2_ick = {
864 .name = "gpt2_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700865 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000866 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300867 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200868 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
869 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
870 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000871};
872
873static struct clk gpt2_fck = {
874 .name = "gpt2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000875 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000876 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300877 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200878 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
879 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
880 .init = &omap2_init_clksel_parent,
881 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
882 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
883 .clksel = omap24xx_gpt_clksel,
884 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000885};
886
887static struct clk gpt3_ick = {
888 .name = "gpt3_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700889 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000890 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300891 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200892 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
893 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
894 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000895};
896
897static struct clk gpt3_fck = {
898 .name = "gpt3_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000899 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000900 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300901 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200902 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
903 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
904 .init = &omap2_init_clksel_parent,
905 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
906 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
907 .clksel = omap24xx_gpt_clksel,
908 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000909};
910
911static struct clk gpt4_ick = {
912 .name = "gpt4_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700913 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000914 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300915 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200916 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
917 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
918 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000919};
920
921static struct clk gpt4_fck = {
922 .name = "gpt4_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000923 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000924 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300925 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200926 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
927 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
928 .init = &omap2_init_clksel_parent,
929 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
930 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
931 .clksel = omap24xx_gpt_clksel,
932 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000933};
934
935static struct clk gpt5_ick = {
936 .name = "gpt5_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700937 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000938 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300939 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
941 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
942 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000943};
944
945static struct clk gpt5_fck = {
946 .name = "gpt5_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000947 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000948 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300949 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200950 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
951 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
952 .init = &omap2_init_clksel_parent,
953 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
954 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
955 .clksel = omap24xx_gpt_clksel,
956 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000957};
958
959static struct clk gpt6_ick = {
960 .name = "gpt6_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700961 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000962 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300963 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200964 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
965 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
966 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000967};
968
969static struct clk gpt6_fck = {
970 .name = "gpt6_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000971 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000972 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300973 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200974 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
975 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
976 .init = &omap2_init_clksel_parent,
977 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
978 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
979 .clksel = omap24xx_gpt_clksel,
980 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000981};
982
983static struct clk gpt7_ick = {
984 .name = "gpt7_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -0700985 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000986 .parent = &l4_ck,
Paul Walmsleya4fc9272011-02-25 14:53:40 -0700987 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200988 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
989 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
990 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000991};
992
993static struct clk gpt7_fck = {
994 .name = "gpt7_fck",
Russell Kingb36ee722008-11-04 17:59:52 +0000995 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +0000996 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +0300997 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +0200998 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
999 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1000 .init = &omap2_init_clksel_parent,
1001 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1002 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1003 .clksel = omap24xx_gpt_clksel,
1004 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001005};
1006
1007static struct clk gpt8_ick = {
1008 .name = "gpt8_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001009 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001010 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001011 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001012 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1013 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1014 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001015};
1016
1017static struct clk gpt8_fck = {
1018 .name = "gpt8_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001019 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001020 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001021 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001022 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1023 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1024 .init = &omap2_init_clksel_parent,
1025 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1026 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1027 .clksel = omap24xx_gpt_clksel,
1028 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001029};
1030
1031static struct clk gpt9_ick = {
1032 .name = "gpt9_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001033 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001034 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001035 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001036 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1037 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1038 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001039};
1040
1041static struct clk gpt9_fck = {
1042 .name = "gpt9_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001043 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001044 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001045 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001046 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1047 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1048 .init = &omap2_init_clksel_parent,
1049 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1050 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1051 .clksel = omap24xx_gpt_clksel,
1052 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001053};
1054
1055static struct clk gpt10_ick = {
1056 .name = "gpt10_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001057 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001058 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001059 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001060 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1061 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1062 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001063};
1064
1065static struct clk gpt10_fck = {
1066 .name = "gpt10_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001067 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001068 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001069 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001070 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1071 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1072 .init = &omap2_init_clksel_parent,
1073 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1074 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1075 .clksel = omap24xx_gpt_clksel,
1076 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001077};
1078
1079static struct clk gpt11_ick = {
1080 .name = "gpt11_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001081 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001082 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001083 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001084 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1085 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1086 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001087};
1088
1089static struct clk gpt11_fck = {
1090 .name = "gpt11_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001091 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001092 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001093 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001094 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1095 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1096 .init = &omap2_init_clksel_parent,
1097 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1098 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1099 .clksel = omap24xx_gpt_clksel,
1100 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001101};
1102
1103static struct clk gpt12_ick = {
1104 .name = "gpt12_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001105 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001106 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001107 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001108 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1109 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1110 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001111};
1112
1113static struct clk gpt12_fck = {
1114 .name = "gpt12_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001115 .ops = &clkops_omap2_dflt_wait,
Paul Walmsleyf2480762009-04-23 21:11:10 -06001116 .parent = &secure_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001117 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001118 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1119 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1120 .init = &omap2_init_clksel_parent,
1121 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1122 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1123 .clksel = omap24xx_gpt_clksel,
1124 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001125};
1126
1127static struct clk mcbsp1_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001128 .name = "mcbsp1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001129 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001130 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001131 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001132 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1133 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1134 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001135};
1136
Paul Walmsley1bccb342010-10-08 11:40:17 -06001137static const struct clksel_rate common_mcbsp_96m_rates[] = {
1138 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1139 { .div = 0 }
1140};
1141
1142static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1143 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1144 { .div = 0 }
1145};
1146
1147static const struct clksel mcbsp_fck_clksel[] = {
1148 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1149 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1150 { .parent = NULL }
1151};
1152
Tony Lindgren046d6b22005-11-10 14:26:52 +00001153static struct clk mcbsp1_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001154 .name = "mcbsp1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001155 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001156 .parent = &func_96m_ck,
Paul Walmsley1bccb342010-10-08 11:40:17 -06001157 .init = &omap2_init_clksel_parent,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001158 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001159 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1160 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
Paul Walmsley1bccb342010-10-08 11:40:17 -06001161 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1162 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1163 .clksel = mcbsp_fck_clksel,
1164 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001165};
1166
1167static struct clk mcbsp2_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001168 .name = "mcbsp2_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001169 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001170 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001171 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001172 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1173 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1174 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001175};
1176
1177static struct clk mcbsp2_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001178 .name = "mcbsp2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001179 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001180 .parent = &func_96m_ck,
Paul Walmsley1bccb342010-10-08 11:40:17 -06001181 .init = &omap2_init_clksel_parent,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001182 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001183 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1184 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
Paul Walmsley1bccb342010-10-08 11:40:17 -06001185 .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1186 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
1187 .clksel = mcbsp_fck_clksel,
1188 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001189};
1190
Tony Lindgren046d6b22005-11-10 14:26:52 +00001191static struct clk mcspi1_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001192 .name = "mcspi1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001193 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001194 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001195 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1197 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1198 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001199};
1200
1201static struct clk mcspi1_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001202 .name = "mcspi1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001203 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001204 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001205 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001206 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1207 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1208 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001209};
1210
1211static struct clk mcspi2_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001212 .name = "mcspi2_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001213 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001214 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001215 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1217 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1218 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001219};
1220
1221static struct clk mcspi2_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001222 .name = "mcspi2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001223 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001224 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001225 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001226 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1227 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1228 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001229};
1230
Tony Lindgren046d6b22005-11-10 14:26:52 +00001231static struct clk uart1_ick = {
1232 .name = "uart1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001233 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001234 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001235 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001236 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1237 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1238 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001239};
1240
1241static struct clk uart1_fck = {
1242 .name = "uart1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001243 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001244 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001245 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001246 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1247 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1248 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001249};
1250
1251static struct clk uart2_ick = {
1252 .name = "uart2_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001253 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001254 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001255 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1257 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1258 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001259};
1260
1261static struct clk uart2_fck = {
1262 .name = "uart2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001263 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001264 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001265 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1267 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1268 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001269};
1270
1271static struct clk uart3_ick = {
1272 .name = "uart3_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001273 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001274 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001275 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001276 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1277 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1278 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001279};
1280
1281static struct clk uart3_fck = {
1282 .name = "uart3_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001283 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001284 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001285 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001286 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1287 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1288 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001289};
1290
1291static struct clk gpios_ick = {
1292 .name = "gpios_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001293 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001294 .parent = &wu_l4_ick,
1295 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001296 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1297 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1298 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001299};
1300
1301static struct clk gpios_fck = {
1302 .name = "gpios_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001303 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001304 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001305 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001306 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1307 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1308 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001309};
1310
1311static struct clk mpu_wdt_ick = {
1312 .name = "mpu_wdt_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001313 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001314 .parent = &wu_l4_ick,
1315 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001316 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1317 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1318 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001319};
1320
1321static struct clk mpu_wdt_fck = {
1322 .name = "mpu_wdt_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001323 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001324 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001325 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001326 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1327 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1328 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001329};
1330
1331static struct clk sync_32k_ick = {
1332 .name = "sync_32k_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001333 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001334 .parent = &wu_l4_ick,
1335 .clkdm_name = "wkup_clkdm",
Russell King8ad8ff62009-01-19 15:27:29 +00001336 .flags = ENABLE_ON_INIT,
Paul Walmsleye32744b2008-03-18 15:47:55 +02001337 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1338 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1339 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001340};
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001341
Tony Lindgren046d6b22005-11-10 14:26:52 +00001342static struct clk wdt1_ick = {
1343 .name = "wdt1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001344 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001345 .parent = &wu_l4_ick,
1346 .clkdm_name = "wkup_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001347 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1348 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1349 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001350};
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001351
Tony Lindgren046d6b22005-11-10 14:26:52 +00001352static struct clk omapctrl_ick = {
1353 .name = "omapctrl_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001354 .ops = &clkops_omap2_iclk_dflt_wait,
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001355 .parent = &wu_l4_ick,
1356 .clkdm_name = "wkup_clkdm",
Russell King8ad8ff62009-01-19 15:27:29 +00001357 .flags = ENABLE_ON_INIT,
Paul Walmsleye32744b2008-03-18 15:47:55 +02001358 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1359 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1360 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001361};
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001362
Tony Lindgren046d6b22005-11-10 14:26:52 +00001363static struct clk cam_ick = {
1364 .name = "cam_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001365 .ops = &clkops_omap2_iclk_dflt,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001366 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001367 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1369 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1370 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001371};
1372
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001373/*
1374 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1375 * split into two separate clocks, since the parent clocks are different
1376 * and the clockdomains are also different.
1377 */
Tony Lindgren046d6b22005-11-10 14:26:52 +00001378static struct clk cam_fck = {
1379 .name = "cam_fck",
Russell Kingbc51da42008-11-04 18:59:32 +00001380 .ops = &clkops_omap2_dflt,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001381 .parent = &func_96m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001382 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001383 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1384 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1385 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001386};
1387
1388static struct clk mailboxes_ick = {
1389 .name = "mailboxes_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001390 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001391 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001392 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001393 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1394 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1395 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001396};
1397
1398static struct clk wdt4_ick = {
1399 .name = "wdt4_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001400 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001401 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001402 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001403 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1404 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1405 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001406};
1407
1408static struct clk wdt4_fck = {
1409 .name = "wdt4_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001410 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001411 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001412 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001413 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1414 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1415 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001416};
1417
1418static struct clk wdt3_ick = {
1419 .name = "wdt3_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001420 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001421 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001422 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001423 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1424 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1425 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001426};
1427
1428static struct clk wdt3_fck = {
1429 .name = "wdt3_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001430 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001431 .parent = &func_32k_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001432 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001433 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1434 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1435 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001436};
1437
1438static struct clk mspro_ick = {
1439 .name = "mspro_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001440 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001441 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001442 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001443 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1444 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1445 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001446};
1447
1448static struct clk mspro_fck = {
1449 .name = "mspro_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001450 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001451 .parent = &func_96m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001452 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001453 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1455 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001456};
1457
1458static struct clk mmc_ick = {
1459 .name = "mmc_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001460 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001461 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001462 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001463 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1464 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1465 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001466};
1467
1468static struct clk mmc_fck = {
1469 .name = "mmc_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001470 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001471 .parent = &func_96m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001472 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001473 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1475 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001476};
1477
1478static struct clk fac_ick = {
1479 .name = "fac_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001480 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001481 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001482 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001483 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1484 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1485 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001486};
1487
1488static struct clk fac_fck = {
1489 .name = "fac_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001490 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001491 .parent = &func_12m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001492 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001493 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1494 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1495 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001496};
1497
1498static struct clk eac_ick = {
1499 .name = "eac_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001500 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001501 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001502 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001503 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1504 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1505 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001506};
1507
1508static struct clk eac_fck = {
1509 .name = "eac_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001510 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001511 .parent = &func_96m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001512 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1514 .enable_bit = OMAP2420_EN_EAC_SHIFT,
1515 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001516};
1517
1518static struct clk hdq_ick = {
1519 .name = "hdq_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001520 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001521 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001522 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001523 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1524 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1525 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001526};
1527
1528static struct clk hdq_fck = {
1529 .name = "hdq_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001530 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001531 .parent = &func_12m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001532 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001533 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1534 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1535 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001536};
1537
1538static struct clk i2c2_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001539 .name = "i2c2_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001540 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001541 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001542 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1544 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1545 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001546};
1547
1548static struct clk i2c2_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001549 .name = "i2c2_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001550 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001551 .parent = &func_12m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001552 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001553 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1554 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1555 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001556};
1557
Tony Lindgren046d6b22005-11-10 14:26:52 +00001558static struct clk i2c1_ick = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001559 .name = "i2c1_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001560 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001561 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001562 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001563 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1564 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1565 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001566};
1567
1568static struct clk i2c1_fck = {
Paul Walmsleyb92c1702010-02-22 22:09:19 -07001569 .name = "i2c1_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001570 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001571 .parent = &func_12m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001572 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001573 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1574 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1575 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001576};
1577
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001578/*
1579 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1580 * accesses derived from this data.
1581 */
Paul Walmsleye32744b2008-03-18 15:47:55 +02001582static struct clk gpmc_fck = {
1583 .name = "gpmc_fck",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001584 .ops = &clkops_omap2_iclk_idle_only,
Paul Walmsleye32744b2008-03-18 15:47:55 +02001585 .parent = &core_l3_ck,
Russell King8ad8ff62009-01-19 15:27:29 +00001586 .flags = ENABLE_ON_INIT,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001587 .clkdm_name = "core_l3_clkdm",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1589 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
Paul Walmsleye32744b2008-03-18 15:47:55 +02001590 .recalc = &followparent_recalc,
1591};
1592
1593static struct clk sdma_fck = {
1594 .name = "sdma_fck",
Russell King897dcde2008-11-04 16:35:03 +00001595 .ops = &clkops_null, /* RMK: missing? */
Paul Walmsleye32744b2008-03-18 15:47:55 +02001596 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001597 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001598 .recalc = &followparent_recalc,
1599};
1600
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001601/*
1602 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1603 * accesses derived from this data.
1604 */
Paul Walmsleye32744b2008-03-18 15:47:55 +02001605static struct clk sdma_ick = {
1606 .name = "sdma_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001607 .ops = &clkops_omap2_iclk_idle_only,
Paul Walmsleya1fed572011-02-25 15:51:02 -07001608 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001609 .clkdm_name = "core_l3_clkdm",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001610 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1611 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
Paul Walmsleye32744b2008-03-18 15:47:55 +02001612 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001613};
1614
Paul Walmsleya56d9ea2011-02-25 15:39:29 -07001615/*
1616 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
1617 * accesses derived from this data.
1618 */
1619static struct clk sdrc_ick = {
1620 .name = "sdrc_ick",
1621 .ops = &clkops_omap2_iclk_idle_only,
1622 .parent = &core_l3_ck,
1623 .flags = ENABLE_ON_INIT,
1624 .clkdm_name = "core_l3_clkdm",
1625 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1626 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1627 .recalc = &followparent_recalc,
1628};
1629
Tony Lindgren046d6b22005-11-10 14:26:52 +00001630static struct clk vlynq_ick = {
1631 .name = "vlynq_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001632 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001633 .parent = &core_l3_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001634 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001635 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1636 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1637 .recalc = &followparent_recalc,
1638};
1639
1640static const struct clksel_rate vlynq_fck_96m_rates[] = {
Paul Walmsleyd74b4942010-05-18 18:40:24 -06001641 { .div = 1, .val = 0, .flags = RATE_IN_242X },
Paul Walmsleye32744b2008-03-18 15:47:55 +02001642 { .div = 0 }
1643};
1644
1645static const struct clksel_rate vlynq_fck_core_rates[] = {
1646 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1647 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1648 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1649 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1650 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1651 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1652 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1653 { .div = 12, .val = 12, .flags = RATE_IN_242X },
Paul Walmsleyd74b4942010-05-18 18:40:24 -06001654 { .div = 16, .val = 16, .flags = RATE_IN_242X },
Paul Walmsleye32744b2008-03-18 15:47:55 +02001655 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1656 { .div = 0 }
1657};
1658
1659static const struct clksel vlynq_fck_clksel[] = {
1660 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1661 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1662 { .parent = NULL }
Tony Lindgren046d6b22005-11-10 14:26:52 +00001663};
1664
1665static struct clk vlynq_fck = {
1666 .name = "vlynq_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001667 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001668 .parent = &func_96m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001669 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001670 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1671 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1672 .init = &omap2_init_clksel_parent,
1673 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1674 .clksel_mask = OMAP2420_CLKSEL_VLYNQ_MASK,
1675 .clksel = vlynq_fck_clksel,
1676 .recalc = &omap2_clksel_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001677};
1678
Tony Lindgren046d6b22005-11-10 14:26:52 +00001679static struct clk des_ick = {
1680 .name = "des_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001681 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001682 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001683 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001684 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1685 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1686 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001687};
1688
1689static struct clk sha_ick = {
1690 .name = "sha_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001691 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001692 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001693 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1695 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1696 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001697};
1698
1699static struct clk rng_ick = {
1700 .name = "rng_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001701 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001702 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001703 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001704 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1705 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1706 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001707};
1708
1709static struct clk aes_ick = {
1710 .name = "aes_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001711 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001712 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001713 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001714 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1715 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1716 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001717};
1718
1719static struct clk pka_ick = {
1720 .name = "pka_ick",
Paul Walmsley6ae690d2011-02-25 15:39:29 -07001721 .ops = &clkops_omap2_iclk_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001722 .parent = &l4_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001723 .clkdm_name = "core_l4_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001724 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1725 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1726 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001727};
1728
1729static struct clk usb_fck = {
1730 .name = "usb_fck",
Russell Kingb36ee722008-11-04 17:59:52 +00001731 .ops = &clkops_omap2_dflt_wait,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001732 .parent = &func_48m_ck,
Paul Walmsleyd1b03f62008-08-19 11:08:44 +03001733 .clkdm_name = "core_l3_clkdm",
Paul Walmsleye32744b2008-03-18 15:47:55 +02001734 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1735 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1736 .recalc = &followparent_recalc,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001737};
1738
Tony Lindgren046d6b22005-11-10 14:26:52 +00001739/*
1740 * This clock is a composite clock which does entire set changes then
1741 * forces a rebalance. It keys on the MPU speed, but it really could
1742 * be any key speed part of a set in the rate table.
1743 *
1744 * to really change a set, you need memory table sets which get changed
1745 * in sram, pre-notifiers & post notifiers, changing the top set, without
1746 * having low level display recalc's won't work... this is why dpm notifiers
1747 * work, isr's off, walk a list of clocks already _off_ and not messing with
1748 * the bus.
1749 *
1750 * This clock should have no parent. It embodies the entire upper level
1751 * active set. A parent will mess up some of the init also.
1752 */
1753static struct clk virt_prcm_set = {
1754 .name = "virt_prcm_set",
Russell King897dcde2008-11-04 16:35:03 +00001755 .ops = &clkops_null,
Tony Lindgren046d6b22005-11-10 14:26:52 +00001756 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
Paul Walmsleye32744b2008-03-18 15:47:55 +02001757 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
Tony Lindgren046d6b22005-11-10 14:26:52 +00001758 .set_rate = &omap2_select_table_rate,
1759 .round_rate = &omap2_round_to_table_rate,
1760};
Paul Walmsleye32744b2008-03-18 15:47:55 +02001761
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001762
1763/*
1764 * clkdev integration
1765 */
1766
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001767static struct omap_clk omap2420_clks[] = {
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001768 /* external root sources */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001769 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
1770 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
1771 CLK(NULL, "osc_ck", &osc_ck, CK_242X),
1772 CLK(NULL, "sys_ck", &sys_ck, CK_242X),
1773 CLK(NULL, "alt_ck", &alt_ck, CK_242X),
Paul Walmsley1bccb342010-10-08 11:40:17 -06001774 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_242X),
1775 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_242X),
1776 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001777 /* internal analog sources */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001778 CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
1779 CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
1780 CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001781 /* internal prcm root sources */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001782 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
1783 CLK(NULL, "core_ck", &core_ck, CK_242X),
Paul Walmsley1bccb342010-10-08 11:40:17 -06001784 CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_242X),
1785 CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001786 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1787 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1788 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
1789 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
1790 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
1791 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001792 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1793 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
1794 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
1795 /* mpu domain clocks */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001796 CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001797 /* dsp domain clocks */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001798 CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001799 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001800 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
1801 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1802 /* GFX domain clocks */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001803 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
1804 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
1805 CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001806 /* DSS domain clocks */
Senthilvadivu Guruswamy8b9cb3a2011-01-24 06:21:58 +00001807 CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001808 CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
1809 CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
1810 CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001811 /* L3 domain clocks */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001812 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
1813 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
1814 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001815 /* L4 domain clocks */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001816 CLK(NULL, "l4_ck", &l4_ck, CK_242X),
1817 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
Paul Walmsley19c1c0c2011-02-16 15:38:38 -07001818 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001819 /* virtual meta-group clock */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001820 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001821 /* general l4 interface ck, multi-parent functional clk */
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001822 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
1823 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
1824 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
1825 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
1826 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
1827 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
1828 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
1829 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
1830 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
1831 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
1832 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
1833 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
1834 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
1835 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
1836 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
1837 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
1838 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
1839 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
1840 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
1841 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
1842 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
1843 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
1844 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
1845 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
1846 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001847 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001848 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001849 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001850 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001851 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001852 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001853 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001854 CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
1855 CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
1856 CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
1857 CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
1858 CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
1859 CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
1860 CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
1861 CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
1862 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001863 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001864 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
1865 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
1866 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
1867 CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
1868 CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
1869 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
1870 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
1871 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001872 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
1873 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001874 CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
1875 CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001876 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
1877 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001878 CLK(NULL, "fac_ick", &fac_ick, CK_242X),
1879 CLK(NULL, "fac_fck", &fac_fck, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001880 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
1881 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001882 CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001883 CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
Benoit Coussonf7bb0d92010-12-09 14:24:16 +00001884 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001885 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
Benoit Coussonf7bb0d92010-12-09 14:24:16 +00001886 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
Benoit Coussonbf1e0772011-07-10 05:54:12 -06001887 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001888 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
1889 CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
1890 CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
Paul Walmsleya56d9ea2011-02-25 15:39:29 -07001891 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001892 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
1893 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001894 CLK(NULL, "des_ick", &des_ick, CK_242X),
Dmitry Kasatkinee5500c2010-05-03 11:10:03 +08001895 CLK("omap-sham", "ick", &sha_ick, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001896 CLK("omap_rng", "ick", &rng_ick, CK_242X),
Dmitry Kasatkin82a0c142010-08-20 13:44:46 +00001897 CLK("omap-aes", "ick", &aes_ick, CK_242X),
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001898 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1899 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
Felipe Balbi05ac10d2010-12-02 08:49:26 +02001900 CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
Tarun Kanti DebBarma318c3e12011-09-20 17:00:16 +05301901 CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
1902 CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
1903 CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),
1904 CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X),
1905 CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X),
1906 CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X),
1907 CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X),
1908 CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X),
1909 CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X),
1910 CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X),
1911 CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X),
1912 CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X),
1913 CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X),
1914 CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X),
1915 CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X),
1916 CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X),
1917 CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X),
1918 CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X),
1919 CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X),
1920 CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X),
1921 CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X),
1922 CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X),
1923 CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X),
1924 CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X),
1925 CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X),
1926 CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X),
1927 CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X),
1928 CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X),
1929 CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X),
1930 CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X),
1931 CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X),
1932 CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X),
1933 CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X),
1934 CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X),
1935 CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X),
1936 CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X),
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001937};
1938
1939/*
1940 * init code
1941 */
1942
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001943int __init omap2420_clk_init(void)
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001944{
1945 const struct prcm_config *prcm;
1946 struct omap_clk *c;
1947 u32 clkrate;
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001948
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001949 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1950 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
1951 cpu_mask = RATE_IN_242X;
1952 rate_table = omap2420_rate_table;
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001953
1954 clk_init(&omap2_clk_functions);
1955
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001956 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1957 c++)
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001958 clk_preinit(c->lk.clk);
1959
1960 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
1961 propagate_rate(&osc_ck);
Paul Walmsley44da0a52010-01-26 20:13:08 -07001962 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001963 propagate_rate(&sys_ck);
1964
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001965 for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1966 c++) {
1967 clkdev_add(&c->lk);
1968 clk_register(c->lk.clk);
1969 omap2_init_clk_clkdm(c->lk.clk);
1970 }
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001971
Paul Walmsleyc6461f52011-02-25 15:49:53 -07001972 /* Disable autoidle on all clocks; let the PM code enable it later */
1973 omap_clk_disable_autoidle_all();
1974
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001975 /* Check the MPU rate set by bootloader */
1976 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
1977 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1978 if (!(prcm->flags & cpu_mask))
1979 continue;
1980 if (prcm->xtal_speed != sys_ck.rate)
1981 continue;
1982 if (prcm->dpll_speed <= clkrate)
1983 break;
1984 }
1985 curr_prcm_set = prcm;
1986
1987 recalculate_root_clocks();
1988
Paul Walmsley81b34fb2010-02-22 22:09:22 -07001989 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1990 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1991 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
Paul Walmsleyd8a94452009-12-08 16:21:29 -07001992
1993 /*
1994 * Only enable those clocks we will need, let the drivers
1995 * enable other clocks as necessary
1996 */
1997 clk_enable_init_clocks();
1998
1999 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
2000 vclk = clk_get(NULL, "virt_prcm_set");
2001 sclk = clk_get(NULL, "sys_ck");
2002 dclk = clk_get(NULL, "dpll_ck");
2003
2004 return 0;
2005}
Paul Walmsley6b8858a2008-03-18 10:35:15 +02002006