Gabor Juhos | f8365ec | 2012-03-14 10:36:10 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Atheros AR71xx PCI host controller driver |
| 3 | * |
| 4 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> |
| 5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
| 6 | * |
| 7 | * Parts of this file are based on Atheros' 2.6.15 BSP |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License version 2 as published |
| 11 | * by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/resource.h> |
| 15 | #include <linux/types.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/pci.h> |
| 19 | #include <linux/pci_regs.h> |
| 20 | #include <linux/interrupt.h> |
Gabor Juhos | fb167e8 | 2013-02-02 11:40:43 +0000 | [diff] [blame^] | 21 | #include <linux/module.h> |
| 22 | #include <linux/platform_device.h> |
Gabor Juhos | f8365ec | 2012-03-14 10:36:10 +0100 | [diff] [blame] | 23 | |
| 24 | #include <asm/mach-ath79/ar71xx_regs.h> |
| 25 | #include <asm/mach-ath79/ath79.h> |
| 26 | #include <asm/mach-ath79/pci.h> |
| 27 | |
| 28 | #define AR71XX_PCI_MEM_BASE 0x10000000 |
Gabor Juhos | fe950df | 2013-01-29 08:27:04 +0000 | [diff] [blame] | 29 | #define AR71XX_PCI_MEM_SIZE 0x07000000 |
Gabor Juhos | f8365ec | 2012-03-14 10:36:10 +0100 | [diff] [blame] | 30 | |
| 31 | #define AR71XX_PCI_WIN0_OFFS 0x10000000 |
| 32 | #define AR71XX_PCI_WIN1_OFFS 0x11000000 |
| 33 | #define AR71XX_PCI_WIN2_OFFS 0x12000000 |
| 34 | #define AR71XX_PCI_WIN3_OFFS 0x13000000 |
| 35 | #define AR71XX_PCI_WIN4_OFFS 0x14000000 |
| 36 | #define AR71XX_PCI_WIN5_OFFS 0x15000000 |
| 37 | #define AR71XX_PCI_WIN6_OFFS 0x16000000 |
| 38 | #define AR71XX_PCI_WIN7_OFFS 0x07000000 |
| 39 | |
| 40 | #define AR71XX_PCI_CFG_BASE \ |
| 41 | (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) |
| 42 | #define AR71XX_PCI_CFG_SIZE 0x100 |
| 43 | |
| 44 | #define AR71XX_PCI_REG_CRP_AD_CBE 0x00 |
| 45 | #define AR71XX_PCI_REG_CRP_WRDATA 0x04 |
| 46 | #define AR71XX_PCI_REG_CRP_RDDATA 0x08 |
| 47 | #define AR71XX_PCI_REG_CFG_AD 0x0c |
| 48 | #define AR71XX_PCI_REG_CFG_CBE 0x10 |
| 49 | #define AR71XX_PCI_REG_CFG_WRDATA 0x14 |
| 50 | #define AR71XX_PCI_REG_CFG_RDDATA 0x18 |
| 51 | #define AR71XX_PCI_REG_PCI_ERR 0x1c |
| 52 | #define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20 |
| 53 | #define AR71XX_PCI_REG_AHB_ERR 0x24 |
| 54 | #define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28 |
| 55 | |
| 56 | #define AR71XX_PCI_CRP_CMD_WRITE 0x00010000 |
| 57 | #define AR71XX_PCI_CRP_CMD_READ 0x00000000 |
| 58 | #define AR71XX_PCI_CFG_CMD_READ 0x0000000a |
| 59 | #define AR71XX_PCI_CFG_CMD_WRITE 0x0000000b |
| 60 | |
| 61 | #define AR71XX_PCI_INT_CORE BIT(4) |
| 62 | #define AR71XX_PCI_INT_DEV2 BIT(2) |
| 63 | #define AR71XX_PCI_INT_DEV1 BIT(1) |
| 64 | #define AR71XX_PCI_INT_DEV0 BIT(0) |
| 65 | |
| 66 | #define AR71XX_PCI_IRQ_COUNT 5 |
| 67 | |
| 68 | static DEFINE_SPINLOCK(ar71xx_pci_lock); |
| 69 | static void __iomem *ar71xx_pcicfg_base; |
| 70 | |
| 71 | /* Byte lane enable bits */ |
| 72 | static const u8 ar71xx_pci_ble_table[4][4] = { |
| 73 | {0x0, 0xf, 0xf, 0xf}, |
| 74 | {0xe, 0xd, 0xb, 0x7}, |
| 75 | {0xc, 0xf, 0x3, 0xf}, |
| 76 | {0xf, 0xf, 0xf, 0xf}, |
| 77 | }; |
| 78 | |
| 79 | static const u32 ar71xx_pci_read_mask[8] = { |
| 80 | 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 |
| 81 | }; |
| 82 | |
| 83 | static inline u32 ar71xx_pci_get_ble(int where, int size, int local) |
| 84 | { |
| 85 | u32 t; |
| 86 | |
| 87 | t = ar71xx_pci_ble_table[size & 3][where & 3]; |
| 88 | BUG_ON(t == 0xf); |
| 89 | t <<= (local) ? 20 : 4; |
| 90 | |
| 91 | return t; |
| 92 | } |
| 93 | |
| 94 | static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, |
| 95 | int where) |
| 96 | { |
| 97 | u32 ret; |
| 98 | |
| 99 | if (!bus->number) { |
| 100 | /* type 0 */ |
| 101 | ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) | |
| 102 | (where & ~3); |
| 103 | } else { |
| 104 | /* type 1 */ |
| 105 | ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) | |
| 106 | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1; |
| 107 | } |
| 108 | |
| 109 | return ret; |
| 110 | } |
| 111 | |
| 112 | static int ar71xx_pci_check_error(int quiet) |
| 113 | { |
| 114 | void __iomem *base = ar71xx_pcicfg_base; |
| 115 | u32 pci_err; |
| 116 | u32 ahb_err; |
| 117 | |
| 118 | pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; |
| 119 | if (pci_err) { |
| 120 | if (!quiet) { |
| 121 | u32 addr; |
| 122 | |
| 123 | addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); |
| 124 | pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", |
| 125 | "PCI", pci_err, addr); |
| 126 | } |
| 127 | |
| 128 | /* clear PCI error status */ |
| 129 | __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR); |
| 130 | } |
| 131 | |
| 132 | ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; |
| 133 | if (ahb_err) { |
| 134 | if (!quiet) { |
| 135 | u32 addr; |
| 136 | |
| 137 | addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); |
| 138 | pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", |
| 139 | "AHB", ahb_err, addr); |
| 140 | } |
| 141 | |
| 142 | /* clear AHB error status */ |
| 143 | __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR); |
| 144 | } |
| 145 | |
| 146 | return !!(ahb_err | pci_err); |
| 147 | } |
| 148 | |
| 149 | static inline void ar71xx_pci_local_write(int where, int size, u32 value) |
| 150 | { |
| 151 | void __iomem *base = ar71xx_pcicfg_base; |
| 152 | u32 ad_cbe; |
| 153 | |
| 154 | value = value << (8 * (where & 3)); |
| 155 | |
| 156 | ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3); |
| 157 | ad_cbe |= ar71xx_pci_get_ble(where, size, 1); |
| 158 | |
| 159 | __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE); |
| 160 | __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA); |
| 161 | } |
| 162 | |
| 163 | static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, |
| 164 | unsigned int devfn, |
| 165 | int where, int size, u32 cmd) |
| 166 | { |
| 167 | void __iomem *base = ar71xx_pcicfg_base; |
| 168 | u32 addr; |
| 169 | |
| 170 | addr = ar71xx_pci_bus_addr(bus, devfn, where); |
| 171 | |
| 172 | __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD); |
| 173 | __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), |
| 174 | base + AR71XX_PCI_REG_CFG_CBE); |
| 175 | |
| 176 | return ar71xx_pci_check_error(1); |
| 177 | } |
| 178 | |
| 179 | static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, |
| 180 | int where, int size, u32 *value) |
| 181 | { |
| 182 | void __iomem *base = ar71xx_pcicfg_base; |
| 183 | unsigned long flags; |
| 184 | u32 data; |
| 185 | int err; |
| 186 | int ret; |
| 187 | |
| 188 | ret = PCIBIOS_SUCCESSFUL; |
| 189 | data = ~0; |
| 190 | |
| 191 | spin_lock_irqsave(&ar71xx_pci_lock, flags); |
| 192 | |
| 193 | err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, |
| 194 | AR71XX_PCI_CFG_CMD_READ); |
| 195 | if (err) |
| 196 | ret = PCIBIOS_DEVICE_NOT_FOUND; |
| 197 | else |
| 198 | data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); |
| 199 | |
| 200 | spin_unlock_irqrestore(&ar71xx_pci_lock, flags); |
| 201 | |
| 202 | *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7]; |
| 203 | |
| 204 | return ret; |
| 205 | } |
| 206 | |
| 207 | static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, |
| 208 | int where, int size, u32 value) |
| 209 | { |
| 210 | void __iomem *base = ar71xx_pcicfg_base; |
| 211 | unsigned long flags; |
| 212 | int err; |
| 213 | int ret; |
| 214 | |
| 215 | value = value << (8 * (where & 3)); |
| 216 | ret = PCIBIOS_SUCCESSFUL; |
| 217 | |
| 218 | spin_lock_irqsave(&ar71xx_pci_lock, flags); |
| 219 | |
| 220 | err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, |
| 221 | AR71XX_PCI_CFG_CMD_WRITE); |
| 222 | if (err) |
| 223 | ret = PCIBIOS_DEVICE_NOT_FOUND; |
| 224 | else |
| 225 | __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); |
| 226 | |
| 227 | spin_unlock_irqrestore(&ar71xx_pci_lock, flags); |
| 228 | |
| 229 | return ret; |
| 230 | } |
| 231 | |
| 232 | static struct pci_ops ar71xx_pci_ops = { |
| 233 | .read = ar71xx_pci_read_config, |
| 234 | .write = ar71xx_pci_write_config, |
| 235 | }; |
| 236 | |
| 237 | static struct resource ar71xx_pci_io_resource = { |
| 238 | .name = "PCI IO space", |
| 239 | .start = 0, |
| 240 | .end = 0, |
| 241 | .flags = IORESOURCE_IO, |
| 242 | }; |
| 243 | |
| 244 | static struct resource ar71xx_pci_mem_resource = { |
| 245 | .name = "PCI memory space", |
| 246 | .start = AR71XX_PCI_MEM_BASE, |
| 247 | .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, |
| 248 | .flags = IORESOURCE_MEM |
| 249 | }; |
| 250 | |
| 251 | static struct pci_controller ar71xx_pci_controller = { |
| 252 | .pci_ops = &ar71xx_pci_ops, |
| 253 | .mem_resource = &ar71xx_pci_mem_resource, |
| 254 | .io_resource = &ar71xx_pci_io_resource, |
| 255 | }; |
| 256 | |
| 257 | static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) |
| 258 | { |
| 259 | void __iomem *base = ath79_reset_base; |
| 260 | u32 pending; |
| 261 | |
| 262 | pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & |
| 263 | __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
| 264 | |
| 265 | if (pending & AR71XX_PCI_INT_DEV0) |
| 266 | generic_handle_irq(ATH79_PCI_IRQ(0)); |
| 267 | |
| 268 | else if (pending & AR71XX_PCI_INT_DEV1) |
| 269 | generic_handle_irq(ATH79_PCI_IRQ(1)); |
| 270 | |
| 271 | else if (pending & AR71XX_PCI_INT_DEV2) |
| 272 | generic_handle_irq(ATH79_PCI_IRQ(2)); |
| 273 | |
| 274 | else if (pending & AR71XX_PCI_INT_CORE) |
| 275 | generic_handle_irq(ATH79_PCI_IRQ(4)); |
| 276 | |
| 277 | else |
| 278 | spurious_interrupt(); |
| 279 | } |
| 280 | |
| 281 | static void ar71xx_pci_irq_unmask(struct irq_data *d) |
| 282 | { |
| 283 | unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; |
| 284 | void __iomem *base = ath79_reset_base; |
| 285 | u32 t; |
| 286 | |
| 287 | t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
| 288 | __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
| 289 | |
| 290 | /* flush write */ |
| 291 | __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
| 292 | } |
| 293 | |
| 294 | static void ar71xx_pci_irq_mask(struct irq_data *d) |
| 295 | { |
| 296 | unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; |
| 297 | void __iomem *base = ath79_reset_base; |
| 298 | u32 t; |
| 299 | |
| 300 | t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
| 301 | __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
| 302 | |
| 303 | /* flush write */ |
| 304 | __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
| 305 | } |
| 306 | |
| 307 | static struct irq_chip ar71xx_pci_irq_chip = { |
| 308 | .name = "AR71XX PCI", |
| 309 | .irq_mask = ar71xx_pci_irq_mask, |
| 310 | .irq_unmask = ar71xx_pci_irq_unmask, |
| 311 | .irq_mask_ack = ar71xx_pci_irq_mask, |
| 312 | }; |
| 313 | |
Gabor Juhos | fb167e8 | 2013-02-02 11:40:43 +0000 | [diff] [blame^] | 314 | static void ar71xx_pci_irq_init(int irq) |
Gabor Juhos | f8365ec | 2012-03-14 10:36:10 +0100 | [diff] [blame] | 315 | { |
| 316 | void __iomem *base = ath79_reset_base; |
| 317 | int i; |
| 318 | |
| 319 | __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
| 320 | __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); |
| 321 | |
| 322 | BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT); |
| 323 | |
| 324 | for (i = ATH79_PCI_IRQ_BASE; |
| 325 | i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) |
| 326 | irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, |
| 327 | handle_level_irq); |
| 328 | |
Gabor Juhos | fb167e8 | 2013-02-02 11:40:43 +0000 | [diff] [blame^] | 329 | irq_set_chained_handler(irq, ar71xx_pci_irq_handler); |
Gabor Juhos | f8365ec | 2012-03-14 10:36:10 +0100 | [diff] [blame] | 330 | } |
| 331 | |
Gabor Juhos | fb167e8 | 2013-02-02 11:40:43 +0000 | [diff] [blame^] | 332 | static void ar71xx_pci_reset(void) |
Gabor Juhos | f8365ec | 2012-03-14 10:36:10 +0100 | [diff] [blame] | 333 | { |
| 334 | void __iomem *ddr_base = ath79_ddr_base; |
| 335 | |
| 336 | ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); |
| 337 | mdelay(100); |
| 338 | |
| 339 | ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); |
| 340 | mdelay(100); |
| 341 | |
| 342 | __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); |
| 343 | __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); |
| 344 | __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); |
| 345 | __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); |
| 346 | __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); |
| 347 | __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); |
| 348 | __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); |
| 349 | __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); |
| 350 | |
| 351 | mdelay(100); |
| 352 | } |
| 353 | |
| 354 | __init int ar71xx_pcibios_init(void) |
| 355 | { |
| 356 | u32 t; |
| 357 | |
| 358 | ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE); |
| 359 | if (ar71xx_pcicfg_base == NULL) |
| 360 | return -ENOMEM; |
| 361 | |
| 362 | ar71xx_pci_reset(); |
| 363 | |
| 364 | /* setup COMMAND register */ |
| 365 | t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
| 366 | | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; |
| 367 | ar71xx_pci_local_write(PCI_COMMAND, 4, t); |
| 368 | |
| 369 | /* clear bus errors */ |
| 370 | ar71xx_pci_check_error(1); |
| 371 | |
Gabor Juhos | fb167e8 | 2013-02-02 11:40:43 +0000 | [diff] [blame^] | 372 | ar71xx_pci_irq_init(ATH79_CPU_IRQ_IP2); |
Gabor Juhos | f8365ec | 2012-03-14 10:36:10 +0100 | [diff] [blame] | 373 | |
| 374 | register_pci_controller(&ar71xx_pci_controller); |
| 375 | |
| 376 | return 0; |
| 377 | } |
Gabor Juhos | fb167e8 | 2013-02-02 11:40:43 +0000 | [diff] [blame^] | 378 | |
| 379 | static int ar71xx_pci_probe(struct platform_device *pdev) |
| 380 | { |
| 381 | struct resource *res; |
| 382 | int irq; |
| 383 | u32 t; |
| 384 | |
| 385 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base"); |
| 386 | if (!res) |
| 387 | return -EINVAL; |
| 388 | |
| 389 | ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res); |
| 390 | if (!ar71xx_pcicfg_base) |
| 391 | return -ENOMEM; |
| 392 | |
| 393 | irq = platform_get_irq(pdev, 0); |
| 394 | if (irq < 0) |
| 395 | return -EINVAL; |
| 396 | |
| 397 | ar71xx_pci_reset(); |
| 398 | |
| 399 | /* setup COMMAND register */ |
| 400 | t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
| 401 | | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; |
| 402 | ar71xx_pci_local_write(PCI_COMMAND, 4, t); |
| 403 | |
| 404 | /* clear bus errors */ |
| 405 | ar71xx_pci_check_error(1); |
| 406 | |
| 407 | ar71xx_pci_irq_init(irq); |
| 408 | |
| 409 | register_pci_controller(&ar71xx_pci_controller); |
| 410 | |
| 411 | return 0; |
| 412 | } |
| 413 | |
| 414 | static struct platform_driver ar71xx_pci_driver = { |
| 415 | .probe = ar71xx_pci_probe, |
| 416 | .driver = { |
| 417 | .name = "ar71xx-pci", |
| 418 | .owner = THIS_MODULE, |
| 419 | }, |
| 420 | }; |
| 421 | |
| 422 | static int __init ar71xx_pci_init(void) |
| 423 | { |
| 424 | return platform_driver_register(&ar71xx_pci_driver); |
| 425 | } |
| 426 | |
| 427 | postcore_initcall(ar71xx_pci_init); |