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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-pxa/irq.c
3 *
eric miaoe3630db2008-03-04 11:42:26 +08004 * Generic PXA IRQ handling
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
eric miaoc01655042008-01-28 23:00:02 +000018#include <linux/sysdev.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019
Russell Kinga09e64f2008-08-05 16:14:15 +010020#include <mach/hardware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <asm/irq.h>
22#include <asm/mach/irq.h>
Eric Miaoa58fbcd2009-01-06 17:37:37 +080023#include <mach/gpio.h>
Eric Miao5bf3df32009-01-20 11:04:16 +080024#include <mach/regs-intc.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025
26#include "generic.h"
27
Haojian Zhuangc482ae42009-11-02 14:02:21 -050028#define MAX_INTERNAL_IRQS 128
29
eric miaof6fb7af2008-03-04 13:53:05 +080030#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
31#define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
32#define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
34/*
35 * This is for peripheral IRQs internal to the PXA chip.
36 */
37
eric miaof6fb7af2008-03-04 13:53:05 +080038static int pxa_internal_irq_nr;
39
40static void pxa_mask_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -070041{
eric miaof6fb7af2008-03-04 13:53:05 +080042 _ICMR(irq) &= ~(1 << IRQ_BIT(irq));
Linus Torvalds1da177e2005-04-16 15:20:36 -070043}
44
eric miaof6fb7af2008-03-04 13:53:05 +080045static void pxa_unmask_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -070046{
eric miaof6fb7af2008-03-04 13:53:05 +080047 _ICMR(irq) |= 1 << IRQ_BIT(irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -070048}
49
eric miaof6fb7af2008-03-04 13:53:05 +080050static struct irq_chip pxa_internal_irq_chip = {
David Brownell38c677c2006-08-01 22:26:25 +010051 .name = "SC",
eric miaof6fb7af2008-03-04 13:53:05 +080052 .ack = pxa_mask_irq,
53 .mask = pxa_mask_irq,
54 .unmask = pxa_unmask_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -070055};
56
Eric Miaoa58fbcd2009-01-06 17:37:37 +080057/*
58 * GPIO IRQs for GPIO 0 and 1
59 */
60static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type)
61{
62 int gpio = irq - IRQ_GPIO0;
63
64 if (__gpio_is_occupied(gpio)) {
65 pr_err("%s failed: GPIO is configured\n", __func__);
66 return -EINVAL;
67 }
68
69 if (type & IRQ_TYPE_EDGE_RISING)
70 GRER0 |= GPIO_bit(gpio);
71 else
72 GRER0 &= ~GPIO_bit(gpio);
73
74 if (type & IRQ_TYPE_EDGE_FALLING)
75 GFER0 |= GPIO_bit(gpio);
76 else
77 GFER0 &= ~GPIO_bit(gpio);
78
79 return 0;
80}
81
82static void pxa_ack_low_gpio(unsigned int irq)
83{
84 GEDR0 = (1 << (irq - IRQ_GPIO0));
85}
86
87static void pxa_mask_low_gpio(unsigned int irq)
88{
89 ICMR &= ~(1 << (irq - PXA_IRQ(0)));
90}
91
92static void pxa_unmask_low_gpio(unsigned int irq)
93{
94 ICMR |= 1 << (irq - PXA_IRQ(0));
95}
96
97static struct irq_chip pxa_low_gpio_chip = {
98 .name = "GPIO-l",
99 .ack = pxa_ack_low_gpio,
100 .mask = pxa_mask_low_gpio,
101 .unmask = pxa_unmask_low_gpio,
102 .set_type = pxa_set_low_gpio_type,
103};
104
105static void __init pxa_init_low_gpio_irq(set_wake_t fn)
106{
107 int irq;
108
109 /* clear edge detection on GPIO 0 and 1 */
110 GFER0 &= ~0x3;
111 GRER0 &= ~0x3;
112 GEDR0 = 0x3;
113
114 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
115 set_irq_chip(irq, &pxa_low_gpio_chip);
116 set_irq_handler(irq, handle_edge_irq);
117 set_irq_flags(irq, IRQF_VALID);
118 }
119
120 pxa_low_gpio_chip.set_wake = fn;
121}
122
eric miaob9e25ac2008-03-04 14:19:58 +0800123void __init pxa_init_irq(int irq_nr, set_wake_t fn)
Eric Miao53665a52007-06-06 06:36:04 +0100124{
Haojian Zhuangd2c37062009-08-19 19:49:31 +0800125 int irq, i;
Eric Miao53665a52007-06-06 06:36:04 +0100126
Haojian Zhuangc482ae42009-11-02 14:02:21 -0500127 BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
128
eric miaof6fb7af2008-03-04 13:53:05 +0800129 pxa_internal_irq_nr = irq_nr;
Eric Miao53665a52007-06-06 06:36:04 +0100130
Marc Zyngier57a7a622008-09-01 13:03:32 +0100131 for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
eric miaof6fb7af2008-03-04 13:53:05 +0800132 _ICMR(irq) = 0; /* disable all IRQs */
133 _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
134 }
Eric Miao53665a52007-06-06 06:36:04 +0100135
Haojian Zhuangd2c37062009-08-19 19:49:31 +0800136 /* initialize interrupt priority */
137 if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
138 for (i = 0; i < irq_nr; i++)
139 IPR(i) = i | (1 << 31);
140 }
141
Eric Miao53665a52007-06-06 06:36:04 +0100142 /* only unmasked interrupts kick us out of idle */
143 ICCR = 1;
144
eric miaof6fb7af2008-03-04 13:53:05 +0800145 for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
146 set_irq_chip(irq, &pxa_internal_irq_chip);
Eric Miao53665a52007-06-06 06:36:04 +0100147 set_irq_handler(irq, handle_level_irq);
148 set_irq_flags(irq, IRQF_VALID);
149 }
Eric Miao53665a52007-06-06 06:36:04 +0100150
eric miaob9e25ac2008-03-04 14:19:58 +0800151 pxa_internal_irq_chip.set_wake = fn;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800152 pxa_init_low_gpio_irq(fn);
eric miaoc95530c2007-08-29 10:22:17 +0100153}
eric miaoc01655042008-01-28 23:00:02 +0000154
155#ifdef CONFIG_PM
Haojian Zhuangc482ae42009-11-02 14:02:21 -0500156static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
157static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
eric miaoc01655042008-01-28 23:00:02 +0000158
159static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
160{
eric miaof6fb7af2008-03-04 13:53:05 +0800161 int i, irq = PXA_IRQ(0);
162
163 for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
164 saved_icmr[i] = _ICMR(irq);
165 _ICMR(irq) = 0;
eric miaoc01655042008-01-28 23:00:02 +0000166 }
Eric Miaoc70f5a62010-01-11 20:39:37 +0800167
168 if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
169 for (i = 0; i < pxa_internal_irq_nr; i++)
170 saved_ipr[i] = IPR(i);
171 }
eric miaoc01655042008-01-28 23:00:02 +0000172
173 return 0;
174}
175
176static int pxa_irq_resume(struct sys_device *dev)
177{
eric miaof6fb7af2008-03-04 13:53:05 +0800178 int i, irq = PXA_IRQ(0);
179
Eric Miaoc70f5a62010-01-11 20:39:37 +0800180 if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
181 for (i = 0; i < pxa_internal_irq_nr; i++)
182 IPR(i) = saved_ipr[i];
183 }
184
eric miaof6fb7af2008-03-04 13:53:05 +0800185 for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
186 _ICMR(irq) = saved_icmr[i];
187 _ICLR(irq) = 0;
eric miaoc01655042008-01-28 23:00:02 +0000188 }
189
eric miaof6fb7af2008-03-04 13:53:05 +0800190 ICCR = 1;
eric miaoc01655042008-01-28 23:00:02 +0000191 return 0;
192}
193#else
194#define pxa_irq_suspend NULL
195#define pxa_irq_resume NULL
196#endif
197
198struct sysdev_class pxa_irq_sysclass = {
199 .name = "irq",
200 .suspend = pxa_irq_suspend,
201 .resume = pxa_irq_resume,
202};
203
204static int __init pxa_irq_init(void)
205{
206 return sysdev_class_register(&pxa_irq_sysclass);
207}
208
209core_initcall(pxa_irq_init);