Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-v850/rte_cb.h -- Midas labs RTE-CB series of evaluation boards |
| 3 | * |
| 4 | * Copyright (C) 2001,02,03 NEC Electronics Corporation |
| 5 | * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org> |
| 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General |
| 8 | * Public License. See the file COPYING in the main directory of this |
| 9 | * archive for more details. |
| 10 | * |
| 11 | * Written by Miles Bader <miles@gnu.org> |
| 12 | */ |
| 13 | |
| 14 | #ifndef __V850_RTE_CB_H__ |
| 15 | #define __V850_RTE_CB_H__ |
| 16 | |
| 17 | |
| 18 | /* The SRAM on the Mother-A motherboard. */ |
| 19 | #define MB_A_SRAM_ADDR GCS0_ADDR |
| 20 | #define MB_A_SRAM_SIZE 0x00200000 /* 2MB */ |
| 21 | |
| 22 | |
| 23 | #ifdef CONFIG_RTE_GBUS_INT |
| 24 | /* GBUS interrupt support. */ |
| 25 | |
| 26 | # include <asm/gbus_int.h> |
| 27 | |
| 28 | # define GBUS_INT_BASE_IRQ NUM_RTE_CB_IRQS |
| 29 | # define GBUS_INT_BASE_ADDR (GCS2_ADDR + 0x00006000) |
| 30 | |
| 31 | /* Some specific interrupts. */ |
| 32 | # define IRQ_MB_A_LAN IRQ_GBUS_INT(10) |
| 33 | # define IRQ_MB_A_PCI1(n) (IRQ_GBUS_INT(16) + (n)) |
| 34 | # define IRQ_MB_A_PCI1_NUM 4 |
| 35 | # define IRQ_MB_A_PCI2(n) (IRQ_GBUS_INT(20) + (n)) |
| 36 | # define IRQ_MB_A_PCI2_NUM 4 |
| 37 | # define IRQ_MB_A_EXT(n) (IRQ_GBUS_INT(24) + (n)) |
| 38 | # define IRQ_MB_A_EXT_NUM 4 |
| 39 | # define IRQ_MB_A_USB_OC(n) (IRQ_GBUS_INT(28) + (n)) |
| 40 | # define IRQ_MB_A_USB_OC_NUM 2 |
| 41 | # define IRQ_MB_A_PCMCIA_OC IRQ_GBUS_INT(30) |
| 42 | |
| 43 | /* We define NUM_MACH_IRQS to include extra interrupts from the GBUS. */ |
| 44 | # define NUM_MACH_IRQS (NUM_RTE_CB_IRQS + IRQ_GBUS_INT_NUM) |
| 45 | |
| 46 | #else /* !CONFIG_RTE_GBUS_INT */ |
| 47 | |
| 48 | # define NUM_MACH_IRQS NUM_RTE_CB_IRQS |
| 49 | |
| 50 | #endif /* CONFIG_RTE_GBUS_INT */ |
| 51 | |
| 52 | |
| 53 | #ifdef CONFIG_RTE_MB_A_PCI |
| 54 | /* Mother-A PCI bus support. */ |
| 55 | |
| 56 | # include <asm/rte_mb_a_pci.h> |
| 57 | |
| 58 | /* These are the base addresses used for allocating device address |
| 59 | space. 512K of the motherboard SRAM is in the same space, so we have |
| 60 | to be careful not to let it be allocated. */ |
| 61 | # define PCIBIOS_MIN_MEM (MB_A_PCI_MEM_ADDR + 0x80000) |
| 62 | # define PCIBIOS_MIN_IO MB_A_PCI_IO_ADDR |
| 63 | |
| 64 | /* As we don't really support PCI DMA to cpu memory, and use bounce-buffers |
| 65 | instead, perversely enough, this becomes always true! */ |
| 66 | # define pci_dma_supported(dev, mask) 1 |
| 67 | # define pci_dac_dma_supported(dev, mask) 0 |
| 68 | # define pcibios_assign_all_busses() 1 |
| 69 | |
| 70 | #endif /* CONFIG_RTE_MB_A_PCI */ |
| 71 | |
| 72 | |
| 73 | /* For <asm/param.h> */ |
| 74 | #ifndef HZ |
| 75 | #define HZ 100 |
| 76 | #endif |
| 77 | |
| 78 | |
| 79 | #ifndef __ASSEMBLY__ |
| 80 | extern void rte_cb_early_init (void); |
| 81 | extern void rte_cb_init_irqs (void); |
| 82 | #endif /* !__ASSEMBLY__ */ |
| 83 | |
| 84 | |
| 85 | #endif /* __V850_RTE_CB_H__ */ |