Padmavathi Venna | 1241ef9 | 2013-06-18 00:02:17 +0900 | [diff] [blame] | 1 | * Samsung Audio Subsystem Clock Controller |
| 2 | |
| 3 | The Samsung Audio Subsystem clock controller generates and supplies clocks |
| 4 | to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock |
Sachin Kamat | 30abda1 | 2013-07-12 08:53:43 +0530 | [diff] [blame] | 5 | binding described here is applicable to all SoCs in Exynos family. |
Padmavathi Venna | 1241ef9 | 2013-06-18 00:02:17 +0900 | [diff] [blame] | 6 | |
| 7 | Required Properties: |
| 8 | |
| 9 | - compatible: should be one of the following: |
| 10 | - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. |
Andrew Bresticker | 3538a2c | 2013-09-25 14:12:51 -0700 | [diff] [blame] | 11 | - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250 |
| 12 | SoCs. |
| 13 | - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420 |
| 14 | SoCs. |
Padmavathi Venna | 1241ef9 | 2013-06-18 00:02:17 +0900 | [diff] [blame] | 15 | - reg: physical base address and length of the controller's register set. |
| 16 | |
| 17 | - #clock-cells: should be 1. |
| 18 | |
Andrew Bresticker | 547f335 | 2013-09-25 14:12:48 -0700 | [diff] [blame] | 19 | - clocks: |
| 20 | - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" |
| 21 | is used if not specified. |
| 22 | - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" |
| 23 | is used if not specified. |
| 24 | - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not |
| 25 | specified. |
| 26 | - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if |
| 27 | not specified. |
| 28 | - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not |
| 29 | specified. |
| 30 | |
| 31 | - clock-names: Aliases for the above clocks. They should be "pll_ref", |
| 32 | "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively. |
| 33 | |
Padmavathi Venna | 1241ef9 | 2013-06-18 00:02:17 +0900 | [diff] [blame] | 34 | The following is the list of clocks generated by the controller. Each clock is |
| 35 | assigned an identifier and client nodes use this identifier to specify the |
| 36 | clock which they consume. Some of the clocks are available only on a particular |
| 37 | Exynos4 SoC and this is specified where applicable. |
| 38 | |
| 39 | Provided clocks: |
| 40 | |
| 41 | Clock ID SoC (if specific) |
| 42 | ----------------------------------------------- |
| 43 | |
| 44 | mout_audss 0 |
| 45 | mout_i2s 1 |
| 46 | dout_srp 2 |
| 47 | dout_aud_bus 3 |
| 48 | dout_i2s 4 |
| 49 | srp_clk 5 |
| 50 | i2s_bus 6 |
| 51 | sclk_i2s 7 |
| 52 | pcm_bus 8 |
| 53 | sclk_pcm 9 |
Andrew Bresticker | 3538a2c | 2013-09-25 14:12:51 -0700 | [diff] [blame] | 54 | adma 10 Exynos5420 |
Padmavathi Venna | 1241ef9 | 2013-06-18 00:02:17 +0900 | [diff] [blame] | 55 | |
Andrew Bresticker | 547f335 | 2013-09-25 14:12:48 -0700 | [diff] [blame] | 56 | Example 1: An example of a clock controller node using the default input |
| 57 | clock names is listed below. |
Padmavathi Venna | 1241ef9 | 2013-06-18 00:02:17 +0900 | [diff] [blame] | 58 | |
| 59 | clock_audss: audss-clock-controller@3810000 { |
| 60 | compatible = "samsung,exynos5250-audss-clock"; |
| 61 | reg = <0x03810000 0x0C>; |
| 62 | #clock-cells = <1>; |
| 63 | }; |
| 64 | |
Andrew Bresticker | 547f335 | 2013-09-25 14:12:48 -0700 | [diff] [blame] | 65 | Example 2: An example of a clock controller node with the input clocks |
| 66 | specified. |
| 67 | |
| 68 | clock_audss: audss-clock-controller@3810000 { |
| 69 | compatible = "samsung,exynos5250-audss-clock"; |
| 70 | reg = <0x03810000 0x0C>; |
| 71 | #clock-cells = <1>; |
| 72 | clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, |
| 73 | <&ext_i2s_clk>; |
| 74 | clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk"; |
| 75 | }; |
| 76 | |
| 77 | Example 3: I2S controller node that consumes the clock generated by the clock |
Padmavathi Venna | 1241ef9 | 2013-06-18 00:02:17 +0900 | [diff] [blame] | 78 | controller. Refer to the standard clock bindings for information |
| 79 | about 'clocks' and 'clock-names' property. |
| 80 | |
| 81 | i2s0: i2s@03830000 { |
| 82 | compatible = "samsung,i2s-v5"; |
| 83 | reg = <0x03830000 0x100>; |
| 84 | dmas = <&pdma0 10 |
| 85 | &pdma0 9 |
| 86 | &pdma0 8>; |
| 87 | dma-names = "tx", "rx", "tx-sec"; |
| 88 | clocks = <&clock_audss EXYNOS_I2S_BUS>, |
| 89 | <&clock_audss EXYNOS_I2S_BUS>, |
| 90 | <&clock_audss EXYNOS_SCLK_I2S>, |
| 91 | <&clock_audss EXYNOS_MOUT_AUDSS>, |
| 92 | <&clock_audss EXYNOS_MOUT_I2S>; |
| 93 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1", |
| 94 | "mout_audss", "mout_i2s"; |
| 95 | }; |