Vineet Gupta | a12ebe1 | 2015-03-09 14:30:19 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
Vineet Gupta | 2e8cd93 | 2016-01-19 16:00:42 +0530 | [diff] [blame] | 10 | /include/ "skeleton_hs_idu.dtsi" |
Vineet Gupta | a12ebe1 | 2015-03-09 14:30:19 +0530 | [diff] [blame] | 11 | |
| 12 | / { |
| 13 | compatible = "snps,nsim_hs"; |
| 14 | interrupt-parent = <&core_intc>; |
| 15 | |
| 16 | chosen { |
| 17 | bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8"; |
| 18 | }; |
| 19 | |
| 20 | aliases { |
| 21 | serial0 = &arcuart0; |
| 22 | }; |
| 23 | |
| 24 | fpga { |
| 25 | compatible = "simple-bus"; |
| 26 | #address-cells = <1>; |
| 27 | #size-cells = <1>; |
| 28 | |
| 29 | /* child and parent address space 1:1 mapped */ |
| 30 | ranges; |
| 31 | |
Vineet Gupta | b3d6aba | 2016-01-01 18:48:40 +0530 | [diff] [blame] | 32 | core_clk: core_clk { |
| 33 | #clock-cells = <0>; |
| 34 | compatible = "fixed-clock"; |
| 35 | clock-frequency = <80000000>; |
| 36 | }; |
| 37 | |
Vineet Gupta | a12ebe1 | 2015-03-09 14:30:19 +0530 | [diff] [blame] | 38 | core_intc: core-interrupt-controller { |
| 39 | compatible = "snps,archs-intc"; |
| 40 | interrupt-controller; |
| 41 | #interrupt-cells = <1>; |
| 42 | }; |
| 43 | |
| 44 | idu_intc: idu-interrupt-controller { |
| 45 | compatible = "snps,archs-idu-intc"; |
| 46 | interrupt-controller; |
| 47 | interrupt-parent = <&core_intc>; |
| 48 | |
| 49 | /* |
| 50 | * <hwirq distribution> |
| 51 | * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 |
| 52 | */ |
| 53 | #interrupt-cells = <2>; |
| 54 | |
| 55 | /* |
| 56 | * upstream irqs to core intc - downstream these are |
| 57 | * "COMMON" irq 0,1.. |
| 58 | */ |
| 59 | interrupts = <24 25 26 27 28 29 30 31>; |
| 60 | }; |
| 61 | |
| 62 | arcuart0: serial@c0fc1000 { |
| 63 | compatible = "snps,arc-uart"; |
| 64 | reg = <0xc0fc1000 0x100>; |
| 65 | interrupt-parent = <&idu_intc>; |
| 66 | interrupts = <0 0>; |
| 67 | clock-frequency = <80000000>; |
| 68 | current-speed = <115200>; |
| 69 | status = "okay"; |
| 70 | }; |
| 71 | |
| 72 | arcpct0: pct { |
| 73 | compatible = "snps,archs-pct"; |
| 74 | #interrupt-cells = <1>; |
| 75 | interrupts = <20>; |
| 76 | }; |
| 77 | }; |
| 78 | }; |