Andre Przywara | e116a37 | 2014-11-14 15:54:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Contains CPU specific errata definitions |
| 3 | * |
| 4 | * Copyright (C) 2014 ARM Ltd. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
Andre Przywara | e116a37 | 2014-11-14 15:54:09 +0000 | [diff] [blame] | 19 | #include <linux/types.h> |
| 20 | #include <asm/cpu.h> |
| 21 | #include <asm/cputype.h> |
| 22 | #include <asm/cpufeature.h> |
| 23 | |
Andre Przywara | 301bcfa | 2014-11-14 15:54:10 +0000 | [diff] [blame] | 24 | static bool __maybe_unused |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 25 | is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) |
Andre Przywara | 301bcfa | 2014-11-14 15:54:10 +0000 | [diff] [blame] | 26 | { |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 27 | WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); |
Will Deacon | d5370f7 | 2016-02-02 12:46:24 +0000 | [diff] [blame] | 28 | return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model, |
| 29 | entry->midr_range_min, |
| 30 | entry->midr_range_max); |
Andre Przywara | 301bcfa | 2014-11-14 15:54:10 +0000 | [diff] [blame] | 31 | } |
| 32 | |
| 33 | #define MIDR_RANGE(model, min, max) \ |
Suzuki K Poulose | 92406f0 | 2016-04-22 12:25:31 +0100 | [diff] [blame] | 34 | .def_scope = SCOPE_LOCAL_CPU, \ |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 35 | .matches = is_affected_midr_range, \ |
Andre Przywara | 301bcfa | 2014-11-14 15:54:10 +0000 | [diff] [blame] | 36 | .midr_model = model, \ |
| 37 | .midr_range_min = min, \ |
| 38 | .midr_range_max = max |
| 39 | |
Marc Zyngier | 359b706 | 2015-03-27 13:09:23 +0000 | [diff] [blame] | 40 | const struct arm64_cpu_capabilities arm64_errata[] = { |
Andre Przywara | c0a01b8 | 2014-11-14 15:54:12 +0000 | [diff] [blame] | 41 | #if defined(CONFIG_ARM64_ERRATUM_826319) || \ |
| 42 | defined(CONFIG_ARM64_ERRATUM_827319) || \ |
| 43 | defined(CONFIG_ARM64_ERRATUM_824069) |
Andre Przywara | 301bcfa | 2014-11-14 15:54:10 +0000 | [diff] [blame] | 44 | { |
| 45 | /* Cortex-A53 r0p[012] */ |
| 46 | .desc = "ARM errata 826319, 827319, 824069", |
| 47 | .capability = ARM64_WORKAROUND_CLEAN_CACHE, |
| 48 | MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02), |
Andre Przywara | 7dd01ae | 2016-06-28 18:07:32 +0100 | [diff] [blame] | 49 | .enable = cpu_enable_cache_maint_trap, |
Andre Przywara | 301bcfa | 2014-11-14 15:54:10 +0000 | [diff] [blame] | 50 | }, |
Andre Przywara | c0a01b8 | 2014-11-14 15:54:12 +0000 | [diff] [blame] | 51 | #endif |
| 52 | #ifdef CONFIG_ARM64_ERRATUM_819472 |
| 53 | { |
| 54 | /* Cortex-A53 r0p[01] */ |
| 55 | .desc = "ARM errata 819472", |
| 56 | .capability = ARM64_WORKAROUND_CLEAN_CACHE, |
| 57 | MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01), |
Andre Przywara | 7dd01ae | 2016-06-28 18:07:32 +0100 | [diff] [blame] | 58 | .enable = cpu_enable_cache_maint_trap, |
Andre Przywara | c0a01b8 | 2014-11-14 15:54:12 +0000 | [diff] [blame] | 59 | }, |
| 60 | #endif |
| 61 | #ifdef CONFIG_ARM64_ERRATUM_832075 |
Andre Przywara | 301bcfa | 2014-11-14 15:54:10 +0000 | [diff] [blame] | 62 | { |
Andre Przywara | 5afaa1f | 2014-11-14 15:54:11 +0000 | [diff] [blame] | 63 | /* Cortex-A57 r0p0 - r1p2 */ |
| 64 | .desc = "ARM erratum 832075", |
| 65 | .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, |
Bo Yan | 6d1966d | 2015-03-31 21:30:48 +0100 | [diff] [blame] | 66 | MIDR_RANGE(MIDR_CORTEX_A57, 0x00, |
| 67 | (1 << MIDR_VARIANT_SHIFT) | 2), |
Andre Przywara | 5afaa1f | 2014-11-14 15:54:11 +0000 | [diff] [blame] | 68 | }, |
Andre Przywara | c0a01b8 | 2014-11-14 15:54:12 +0000 | [diff] [blame] | 69 | #endif |
Marc Zyngier | 498cd5c | 2015-11-16 10:28:18 +0000 | [diff] [blame] | 70 | #ifdef CONFIG_ARM64_ERRATUM_834220 |
| 71 | { |
| 72 | /* Cortex-A57 r0p0 - r1p2 */ |
| 73 | .desc = "ARM erratum 834220", |
| 74 | .capability = ARM64_WORKAROUND_834220, |
| 75 | MIDR_RANGE(MIDR_CORTEX_A57, 0x00, |
| 76 | (1 << MIDR_VARIANT_SHIFT) | 2), |
| 77 | }, |
| 78 | #endif |
Will Deacon | 905e8c5 | 2015-03-23 19:07:02 +0000 | [diff] [blame] | 79 | #ifdef CONFIG_ARM64_ERRATUM_845719 |
| 80 | { |
| 81 | /* Cortex-A53 r0p[01234] */ |
| 82 | .desc = "ARM erratum 845719", |
| 83 | .capability = ARM64_WORKAROUND_845719, |
| 84 | MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), |
| 85 | }, |
| 86 | #endif |
Robert Richter | 6d4e11c | 2015-09-21 22:58:35 +0200 | [diff] [blame] | 87 | #ifdef CONFIG_CAVIUM_ERRATUM_23154 |
| 88 | { |
| 89 | /* Cavium ThunderX, pass 1.x */ |
| 90 | .desc = "Cavium erratum 23154", |
| 91 | .capability = ARM64_WORKAROUND_CAVIUM_23154, |
| 92 | MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), |
| 93 | }, |
| 94 | #endif |
Andrew Pinski | 104a0c0 | 2016-02-24 17:44:57 -0800 | [diff] [blame] | 95 | #ifdef CONFIG_CAVIUM_ERRATUM_27456 |
| 96 | { |
| 97 | /* Cavium ThunderX, T88 pass 1.x - 2.1 */ |
| 98 | .desc = "Cavium erratum 27456", |
| 99 | .capability = ARM64_WORKAROUND_CAVIUM_27456, |
| 100 | MIDR_RANGE(MIDR_THUNDERX, 0x00, |
| 101 | (1 << MIDR_VARIANT_SHIFT) | 1), |
| 102 | }, |
Ganapatrao Kulkarni | 47c459b | 2016-07-07 10:18:17 +0530 | [diff] [blame] | 103 | { |
| 104 | /* Cavium ThunderX, T81 pass 1.0 */ |
| 105 | .desc = "Cavium erratum 27456", |
| 106 | .capability = ARM64_WORKAROUND_CAVIUM_27456, |
| 107 | MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00), |
| 108 | }, |
Andrew Pinski | 104a0c0 | 2016-02-24 17:44:57 -0800 | [diff] [blame] | 109 | #endif |
Andre Przywara | 5afaa1f | 2014-11-14 15:54:11 +0000 | [diff] [blame] | 110 | { |
Andre Przywara | 301bcfa | 2014-11-14 15:54:10 +0000 | [diff] [blame] | 111 | } |
Andre Przywara | e116a37 | 2014-11-14 15:54:09 +0000 | [diff] [blame] | 112 | }; |
| 113 | |
Suzuki K Poulose | 6a6efbb | 2016-04-22 12:25:34 +0100 | [diff] [blame] | 114 | /* |
| 115 | * The CPU Errata work arounds are detected and applied at boot time |
| 116 | * and the related information is freed soon after. If the new CPU requires |
| 117 | * an errata not detected at boot, fail this CPU. |
| 118 | */ |
| 119 | void verify_local_cpu_errata(void) |
| 120 | { |
| 121 | const struct arm64_cpu_capabilities *caps = arm64_errata; |
| 122 | |
| 123 | for (; caps->matches; caps++) |
| 124 | if (!cpus_have_cap(caps->capability) && |
| 125 | caps->matches(caps, SCOPE_LOCAL_CPU)) { |
| 126 | pr_crit("CPU%d: Requires work around for %s, not detected" |
| 127 | " at boot time\n", |
| 128 | smp_processor_id(), |
| 129 | caps->desc ? : "an erratum"); |
| 130 | cpu_die_early(); |
| 131 | } |
| 132 | } |
| 133 | |
Andre Przywara | e116a37 | 2014-11-14 15:54:09 +0000 | [diff] [blame] | 134 | void check_local_cpu_errata(void) |
| 135 | { |
Suzuki K. Poulose | ce8b602 | 2015-10-19 14:24:49 +0100 | [diff] [blame] | 136 | update_cpu_capabilities(arm64_errata, "enabling workaround for"); |
Andre Przywara | e116a37 | 2014-11-14 15:54:09 +0000 | [diff] [blame] | 137 | } |
Andre Przywara | 8e23185 | 2016-06-28 18:07:30 +0100 | [diff] [blame] | 138 | |
| 139 | void __init enable_errata_workarounds(void) |
| 140 | { |
| 141 | enable_cpu_capabilities(arm64_errata); |
| 142 | } |