Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * PMU support |
| 3 | * |
| 4 | * Copyright (C) 2012 ARM Limited |
| 5 | * Author: Will Deacon <will.deacon@arm.com> |
| 6 | * |
| 7 | * This code is based heavily on the ARMv7 perf event code. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 20 | */ |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 21 | |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 22 | #include <asm/irq_regs.h> |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 23 | #include <asm/perf_event.h> |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 24 | #include <asm/sysreg.h> |
Marc Zyngier | d98ecda | 2016-01-25 17:31:13 +0000 | [diff] [blame] | 25 | #include <asm/virt.h> |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 26 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 27 | #include <linux/of.h> |
| 28 | #include <linux/perf/arm_pmu.h> |
| 29 | #include <linux/platform_device.h> |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 30 | |
| 31 | /* |
| 32 | * ARMv8 PMUv3 Performance Events handling code. |
| 33 | * Common event types. |
| 34 | */ |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 35 | |
Drew Richardson | 90381cb | 2015-10-22 07:07:01 -0700 | [diff] [blame] | 36 | /* Required events. */ |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 37 | #define ARMV8_PMUV3_PERFCTR_SW_INCR 0x00 |
| 38 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x03 |
| 39 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x04 |
| 40 | #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x10 |
| 41 | #define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x11 |
| 42 | #define ARMV8_PMUV3_PERFCTR_BR_PRED 0x12 |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 43 | |
Drew Richardson | 90381cb | 2015-10-22 07:07:01 -0700 | [diff] [blame] | 44 | /* At least one of the following is required. */ |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 45 | #define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x08 |
| 46 | #define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x1B |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 47 | |
Drew Richardson | 90381cb | 2015-10-22 07:07:01 -0700 | [diff] [blame] | 48 | /* Common architectural events. */ |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 49 | #define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x06 |
| 50 | #define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x07 |
Drew Richardson | 90381cb | 2015-10-22 07:07:01 -0700 | [diff] [blame] | 51 | #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x09 |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 52 | #define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x0A |
| 53 | #define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x0B |
| 54 | #define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x0C |
| 55 | #define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x0D |
| 56 | #define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x0E |
| 57 | #define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x0F |
| 58 | #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x1C |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 59 | #define ARMV8_PMUV3_PERFCTR_CHAIN 0x1E |
| 60 | #define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x21 |
Drew Richardson | 90381cb | 2015-10-22 07:07:01 -0700 | [diff] [blame] | 61 | |
| 62 | /* Common microarchitectural events. */ |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 63 | #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x01 |
| 64 | #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x02 |
| 65 | #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x05 |
Drew Richardson | 90381cb | 2015-10-22 07:07:01 -0700 | [diff] [blame] | 66 | #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x13 |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 67 | #define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x14 |
| 68 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x15 |
| 69 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x16 |
| 70 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x17 |
| 71 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x18 |
Drew Richardson | 90381cb | 2015-10-22 07:07:01 -0700 | [diff] [blame] | 72 | #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x19 |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 73 | #define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x1A |
Drew Richardson | 90381cb | 2015-10-22 07:07:01 -0700 | [diff] [blame] | 74 | #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x1D |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 75 | #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x1F |
| 76 | #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x20 |
| 77 | #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x22 |
| 78 | #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x23 |
| 79 | #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x24 |
| 80 | #define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x25 |
| 81 | #define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x26 |
| 82 | #define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x27 |
| 83 | #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x28 |
| 84 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x29 |
| 85 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x2A |
| 86 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x2B |
| 87 | #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x2C |
| 88 | #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x2D |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 89 | #define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x2E |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 90 | #define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x2F |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 91 | #define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x30 |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 92 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 93 | /* ARMv8 recommended implementation defined event types */ |
| 94 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40 |
| 95 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41 |
| 96 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x42 |
| 97 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x43 |
Ashok Kumar | 0893f74 | 2016-04-21 05:58:42 -0700 | [diff] [blame] | 98 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x44 |
| 99 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x45 |
| 100 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x46 |
| 101 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x47 |
| 102 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x48 |
| 103 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 104 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x4C |
| 105 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x4D |
| 106 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x4E |
| 107 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x4F |
Ashok Kumar | 0893f74 | 2016-04-21 05:58:42 -0700 | [diff] [blame] | 108 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x50 |
| 109 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x51 |
| 110 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x52 |
| 111 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x53 |
| 112 | |
| 113 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x56 |
| 114 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x57 |
| 115 | #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x58 |
| 116 | |
| 117 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x5C |
| 118 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x5D |
| 119 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x5E |
| 120 | #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x5F |
| 121 | |
| 122 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x60 |
| 123 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x61 |
| 124 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x62 |
| 125 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x63 |
| 126 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x64 |
| 127 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x65 |
| 128 | |
| 129 | #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x66 |
| 130 | #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x67 |
| 131 | #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x68 |
| 132 | #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x69 |
| 133 | #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x6A |
| 134 | |
| 135 | #define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x6C |
| 136 | #define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x6D |
| 137 | #define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x6E |
| 138 | #define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x6F |
| 139 | #define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x70 |
| 140 | #define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x71 |
| 141 | #define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x72 |
| 142 | #define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x73 |
| 143 | #define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x74 |
| 144 | #define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x75 |
| 145 | #define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x76 |
| 146 | #define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x77 |
| 147 | #define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x78 |
| 148 | #define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x79 |
| 149 | #define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x7A |
| 150 | |
| 151 | #define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x7C |
| 152 | #define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x7D |
| 153 | #define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x7E |
| 154 | |
| 155 | #define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x81 |
| 156 | #define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x82 |
| 157 | #define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x83 |
| 158 | #define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x84 |
| 159 | |
| 160 | #define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x86 |
| 161 | #define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x87 |
| 162 | #define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x88 |
| 163 | |
| 164 | #define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x8A |
| 165 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x8B |
| 166 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x8C |
| 167 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x8D |
| 168 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x8E |
| 169 | #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x8F |
| 170 | #define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x90 |
| 171 | #define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x91 |
| 172 | |
| 173 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0xA0 |
| 174 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0xA1 |
| 175 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0xA2 |
| 176 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0xA3 |
| 177 | |
| 178 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0xA6 |
| 179 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0xA7 |
| 180 | #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0xA8 |
Jan Glauber | 5f140cc | 2016-02-18 17:50:10 +0100 | [diff] [blame] | 181 | |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 182 | /* ARMv8 Cortex-A53 specific event types. */ |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 183 | #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2 |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 184 | |
Jan Glauber | d0aa2bf | 2016-02-18 17:50:11 +0100 | [diff] [blame] | 185 | /* ARMv8 Cavium ThunderX specific event types. */ |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 186 | #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9 |
| 187 | #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA |
| 188 | #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB |
| 189 | #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC |
| 190 | #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 191 | |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 192 | /* PMUv3 HW events mapping. */ |
| 193 | static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = { |
Mark Rutland | ae2fb7e | 2015-07-21 11:36:39 +0100 | [diff] [blame] | 194 | PERF_MAP_ALL_UNSUPPORTED, |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 195 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES, |
| 196 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED, |
| 197 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, |
| 198 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, |
| 199 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 200 | }; |
| 201 | |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 202 | /* ARM Cortex-A53 HW events mapping. */ |
| 203 | static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = { |
| 204 | PERF_MAP_ALL_UNSUPPORTED, |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 205 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES, |
| 206 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED, |
| 207 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, |
| 208 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, |
| 209 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED, |
| 210 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 211 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES, |
| 212 | }; |
| 213 | |
Will Deacon | 5d7ee87 | 2015-12-22 14:45:35 +0000 | [diff] [blame] | 214 | /* ARM Cortex-A57 and Cortex-A72 events mapping. */ |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 215 | static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = { |
| 216 | PERF_MAP_ALL_UNSUPPORTED, |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 217 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES, |
| 218 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED, |
| 219 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, |
| 220 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, |
| 221 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 222 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES, |
| 223 | }; |
| 224 | |
Jan Glauber | d0aa2bf | 2016-02-18 17:50:11 +0100 | [diff] [blame] | 225 | static const unsigned armv8_thunder_perf_map[PERF_COUNT_HW_MAX] = { |
| 226 | PERF_MAP_ALL_UNSUPPORTED, |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 227 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES, |
| 228 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED, |
| 229 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, |
| 230 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, |
| 231 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED, |
| 232 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
Jan Glauber | d0aa2bf | 2016-02-18 17:50:11 +0100 | [diff] [blame] | 233 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND, |
| 234 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND, |
| 235 | }; |
| 236 | |
Ashok Kumar | 201a72b | 2016-04-21 05:58:45 -0700 | [diff] [blame] | 237 | /* Broadcom Vulcan events mapping */ |
| 238 | static const unsigned armv8_vulcan_perf_map[PERF_COUNT_HW_MAX] = { |
| 239 | PERF_MAP_ALL_UNSUPPORTED, |
| 240 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES, |
| 241 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED, |
| 242 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, |
| 243 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, |
| 244 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_BR_RETIRED, |
| 245 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
| 246 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES, |
| 247 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND, |
| 248 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND, |
| 249 | }; |
| 250 | |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 251 | static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 252 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 253 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
Mark Rutland | ae2fb7e | 2015-07-21 11:36:39 +0100 | [diff] [blame] | 254 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 255 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 256 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, |
| 257 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, |
| 258 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, |
| 259 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, |
Mark Rutland | ae2fb7e | 2015-07-21 11:36:39 +0100 | [diff] [blame] | 260 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 261 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, |
| 262 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
| 263 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, |
| 264 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 265 | }; |
| 266 | |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 267 | static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 268 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 269 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
| 270 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 271 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 272 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, |
| 273 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, |
| 274 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, |
| 275 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, |
| 276 | [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL, |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 277 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 278 | [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, |
| 279 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 280 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 281 | [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL, |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 282 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 283 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, |
| 284 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
| 285 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, |
| 286 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 287 | }; |
| 288 | |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 289 | static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 290 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 291 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
| 292 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 293 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 294 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, |
| 295 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, |
| 296 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, |
| 297 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 298 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 299 | [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, |
| 300 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 301 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 302 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, |
| 303 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 304 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 305 | [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL, |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 306 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 307 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, |
| 308 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
| 309 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, |
| 310 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 311 | }; |
| 312 | |
Jan Glauber | d0aa2bf | 2016-02-18 17:50:11 +0100 | [diff] [blame] | 313 | static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 314 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 315 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
| 316 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 317 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 318 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, |
| 319 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, |
| 320 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, |
| 321 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST, |
| 322 | [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS, |
| 323 | [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS, |
Jan Glauber | d0aa2bf | 2016-02-18 17:50:11 +0100 | [diff] [blame] | 324 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 325 | [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, |
| 326 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, |
| 327 | [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS, |
| 328 | [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS, |
Jan Glauber | d0aa2bf | 2016-02-18 17:50:11 +0100 | [diff] [blame] | 329 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 330 | [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, |
| 331 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, |
| 332 | [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, |
| 333 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 334 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 335 | [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL, |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 336 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 337 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, |
| 338 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
| 339 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, |
| 340 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 341 | }; |
| 342 | |
Ashok Kumar | 201a72b | 2016-04-21 05:58:45 -0700 | [diff] [blame] | 343 | static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
| 344 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 345 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { |
| 346 | PERF_CACHE_MAP_ALL_UNSUPPORTED, |
| 347 | |
| 348 | [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, |
| 349 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, |
| 350 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, |
| 351 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, |
| 352 | |
| 353 | [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, |
| 354 | [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, |
| 355 | |
| 356 | [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL, |
| 357 | [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB, |
| 358 | |
| 359 | [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, |
| 360 | [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, |
| 361 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, |
| 362 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, |
| 363 | |
| 364 | [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, |
| 365 | [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
| 366 | [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, |
| 367 | [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, |
| 368 | |
| 369 | [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, |
| 370 | [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, |
| 371 | }; |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 372 | |
| 373 | static ssize_t |
| 374 | armv8pmu_events_sysfs_show(struct device *dev, |
| 375 | struct device_attribute *attr, char *page) |
| 376 | { |
| 377 | struct perf_pmu_events_attr *pmu_attr; |
| 378 | |
| 379 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); |
| 380 | |
| 381 | return sprintf(page, "event=0x%03llx\n", pmu_attr->id); |
| 382 | } |
| 383 | |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 384 | #define ARMV8_EVENT_ATTR_RESOLVE(m) #m |
| 385 | #define ARMV8_EVENT_ATTR(name, config) \ |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 386 | PMU_EVENT_ATTR(name, armv8_event_attr_##name, \ |
| 387 | config, armv8pmu_events_sysfs_show) |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 388 | |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 389 | ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR); |
| 390 | ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL); |
| 391 | ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL); |
| 392 | ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL); |
| 393 | ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE); |
| 394 | ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL); |
| 395 | ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED); |
| 396 | ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED); |
| 397 | ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED); |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 398 | ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN); |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 399 | ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN); |
| 400 | ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED); |
| 401 | ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED); |
| 402 | ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED); |
| 403 | ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED); |
| 404 | ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED); |
| 405 | ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED); |
| 406 | ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES); |
| 407 | ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED); |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 408 | ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS); |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 409 | ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE); |
| 410 | ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB); |
| 411 | ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE); |
| 412 | ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL); |
| 413 | ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB); |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 414 | ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS); |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 415 | ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR); |
| 416 | ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC); |
| 417 | ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED); |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 418 | ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES); |
Will Deacon | 4ba2578 | 2016-04-25 15:05:24 +0100 | [diff] [blame] | 419 | /* Don't expose the chain event in /sys, since it's useless in isolation */ |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 420 | ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE); |
| 421 | ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE); |
| 422 | ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED); |
| 423 | ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED); |
| 424 | ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND); |
| 425 | ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND); |
| 426 | ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB); |
| 427 | ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB); |
| 428 | ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE); |
| 429 | ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL); |
| 430 | ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE); |
| 431 | ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL); |
| 432 | ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE); |
| 433 | ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB); |
| 434 | ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL); |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 435 | ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL); |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 436 | ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB); |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 437 | ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB); |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 438 | |
| 439 | static struct attribute *armv8_pmuv3_event_attrs[] = { |
| 440 | &armv8_event_attr_sw_incr.attr.attr, |
| 441 | &armv8_event_attr_l1i_cache_refill.attr.attr, |
| 442 | &armv8_event_attr_l1i_tlb_refill.attr.attr, |
| 443 | &armv8_event_attr_l1d_cache_refill.attr.attr, |
| 444 | &armv8_event_attr_l1d_cache.attr.attr, |
| 445 | &armv8_event_attr_l1d_tlb_refill.attr.attr, |
| 446 | &armv8_event_attr_ld_retired.attr.attr, |
| 447 | &armv8_event_attr_st_retired.attr.attr, |
| 448 | &armv8_event_attr_inst_retired.attr.attr, |
| 449 | &armv8_event_attr_exc_taken.attr.attr, |
| 450 | &armv8_event_attr_exc_return.attr.attr, |
| 451 | &armv8_event_attr_cid_write_retired.attr.attr, |
| 452 | &armv8_event_attr_pc_write_retired.attr.attr, |
| 453 | &armv8_event_attr_br_immed_retired.attr.attr, |
| 454 | &armv8_event_attr_br_return_retired.attr.attr, |
| 455 | &armv8_event_attr_unaligned_ldst_retired.attr.attr, |
| 456 | &armv8_event_attr_br_mis_pred.attr.attr, |
| 457 | &armv8_event_attr_cpu_cycles.attr.attr, |
| 458 | &armv8_event_attr_br_pred.attr.attr, |
| 459 | &armv8_event_attr_mem_access.attr.attr, |
| 460 | &armv8_event_attr_l1i_cache.attr.attr, |
| 461 | &armv8_event_attr_l1d_cache_wb.attr.attr, |
| 462 | &armv8_event_attr_l2d_cache.attr.attr, |
| 463 | &armv8_event_attr_l2d_cache_refill.attr.attr, |
| 464 | &armv8_event_attr_l2d_cache_wb.attr.attr, |
| 465 | &armv8_event_attr_bus_access.attr.attr, |
| 466 | &armv8_event_attr_memory_error.attr.attr, |
| 467 | &armv8_event_attr_inst_spec.attr.attr, |
| 468 | &armv8_event_attr_ttbr_write_retired.attr.attr, |
| 469 | &armv8_event_attr_bus_cycles.attr.attr, |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 470 | &armv8_event_attr_l1d_cache_allocate.attr.attr, |
| 471 | &armv8_event_attr_l2d_cache_allocate.attr.attr, |
| 472 | &armv8_event_attr_br_retired.attr.attr, |
| 473 | &armv8_event_attr_br_mis_pred_retired.attr.attr, |
| 474 | &armv8_event_attr_stall_frontend.attr.attr, |
| 475 | &armv8_event_attr_stall_backend.attr.attr, |
| 476 | &armv8_event_attr_l1d_tlb.attr.attr, |
| 477 | &armv8_event_attr_l1i_tlb.attr.attr, |
| 478 | &armv8_event_attr_l2i_cache.attr.attr, |
| 479 | &armv8_event_attr_l2i_cache_refill.attr.attr, |
| 480 | &armv8_event_attr_l3d_cache_allocate.attr.attr, |
| 481 | &armv8_event_attr_l3d_cache_refill.attr.attr, |
| 482 | &armv8_event_attr_l3d_cache.attr.attr, |
| 483 | &armv8_event_attr_l3d_cache_wb.attr.attr, |
| 484 | &armv8_event_attr_l2d_tlb_refill.attr.attr, |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 485 | &armv8_event_attr_l2i_tlb_refill.attr.attr, |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 486 | &armv8_event_attr_l2d_tlb.attr.attr, |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 487 | &armv8_event_attr_l2i_tlb.attr.attr, |
Will Deacon | 57d7412 | 2015-12-22 14:42:57 +0000 | [diff] [blame] | 488 | NULL, |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 489 | }; |
| 490 | |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 491 | static umode_t |
| 492 | armv8pmu_event_attr_is_visible(struct kobject *kobj, |
| 493 | struct attribute *attr, int unused) |
| 494 | { |
| 495 | struct device *dev = kobj_to_dev(kobj); |
| 496 | struct pmu *pmu = dev_get_drvdata(dev); |
| 497 | struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); |
| 498 | struct perf_pmu_events_attr *pmu_attr; |
| 499 | |
| 500 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr); |
| 501 | |
| 502 | if (test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap)) |
| 503 | return attr->mode; |
| 504 | |
| 505 | return 0; |
| 506 | } |
| 507 | |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 508 | static struct attribute_group armv8_pmuv3_events_attr_group = { |
| 509 | .name = "events", |
| 510 | .attrs = armv8_pmuv3_event_attrs, |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 511 | .is_visible = armv8pmu_event_attr_is_visible, |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 512 | }; |
| 513 | |
Will Deacon | 57d7412 | 2015-12-22 14:42:57 +0000 | [diff] [blame] | 514 | PMU_FORMAT_ATTR(event, "config:0-9"); |
| 515 | |
| 516 | static struct attribute *armv8_pmuv3_format_attrs[] = { |
| 517 | &format_attr_event.attr, |
| 518 | NULL, |
| 519 | }; |
| 520 | |
| 521 | static struct attribute_group armv8_pmuv3_format_attr_group = { |
| 522 | .name = "format", |
| 523 | .attrs = armv8_pmuv3_format_attrs, |
| 524 | }; |
| 525 | |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 526 | static const struct attribute_group *armv8_pmuv3_attr_groups[] = { |
| 527 | &armv8_pmuv3_events_attr_group, |
Will Deacon | 57d7412 | 2015-12-22 14:42:57 +0000 | [diff] [blame] | 528 | &armv8_pmuv3_format_attr_group, |
| 529 | NULL, |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 530 | }; |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 531 | |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 532 | /* |
| 533 | * Perf Events' indices |
| 534 | */ |
| 535 | #define ARMV8_IDX_CYCLE_COUNTER 0 |
| 536 | #define ARMV8_IDX_COUNTER0 1 |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 537 | #define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \ |
| 538 | (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 539 | |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 540 | /* |
| 541 | * ARMv8 low level PMU access |
| 542 | */ |
| 543 | |
| 544 | /* |
| 545 | * Perf Event to low level counters mapping |
| 546 | */ |
| 547 | #define ARMV8_IDX_TO_COUNTER(x) \ |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 548 | (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 549 | |
| 550 | static inline u32 armv8pmu_pmcr_read(void) |
| 551 | { |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 552 | return read_sysreg(pmcr_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 553 | } |
| 554 | |
| 555 | static inline void armv8pmu_pmcr_write(u32 val) |
| 556 | { |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 557 | val &= ARMV8_PMU_PMCR_MASK; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 558 | isb(); |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 559 | write_sysreg(val, pmcr_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | static inline int armv8pmu_has_overflowed(u32 pmovsr) |
| 563 | { |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 564 | return pmovsr & ARMV8_PMU_OVERFLOWED_MASK; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 565 | } |
| 566 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 567 | static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 568 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 569 | return idx >= ARMV8_IDX_CYCLE_COUNTER && |
| 570 | idx <= ARMV8_IDX_COUNTER_LAST(cpu_pmu); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 571 | } |
| 572 | |
| 573 | static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx) |
| 574 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 575 | return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx)); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 576 | } |
| 577 | |
| 578 | static inline int armv8pmu_select_counter(int idx) |
| 579 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 580 | u32 counter = ARMV8_IDX_TO_COUNTER(idx); |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 581 | write_sysreg(counter, pmselr_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 582 | isb(); |
| 583 | |
| 584 | return idx; |
| 585 | } |
| 586 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 587 | static inline u32 armv8pmu_read_counter(struct perf_event *event) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 588 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 589 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
| 590 | struct hw_perf_event *hwc = &event->hw; |
| 591 | int idx = hwc->idx; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 592 | u32 value = 0; |
| 593 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 594 | if (!armv8pmu_counter_valid(cpu_pmu, idx)) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 595 | pr_err("CPU%u reading wrong counter %d\n", |
| 596 | smp_processor_id(), idx); |
| 597 | else if (idx == ARMV8_IDX_CYCLE_COUNTER) |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 598 | value = read_sysreg(pmccntr_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 599 | else if (armv8pmu_select_counter(idx) == idx) |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 600 | value = read_sysreg(pmxevcntr_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 601 | |
| 602 | return value; |
| 603 | } |
| 604 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 605 | static inline void armv8pmu_write_counter(struct perf_event *event, u32 value) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 606 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 607 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
| 608 | struct hw_perf_event *hwc = &event->hw; |
| 609 | int idx = hwc->idx; |
| 610 | |
| 611 | if (!armv8pmu_counter_valid(cpu_pmu, idx)) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 612 | pr_err("CPU%u writing wrong counter %d\n", |
| 613 | smp_processor_id(), idx); |
Jan Glauber | 7175f05 | 2016-02-18 17:50:13 +0100 | [diff] [blame] | 614 | else if (idx == ARMV8_IDX_CYCLE_COUNTER) { |
| 615 | /* |
| 616 | * Set the upper 32bits as this is a 64bit counter but we only |
| 617 | * count using the lower 32bits and we want an interrupt when |
| 618 | * it overflows. |
| 619 | */ |
| 620 | u64 value64 = 0xffffffff00000000ULL | value; |
| 621 | |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 622 | write_sysreg(value64, pmccntr_el0); |
Jan Glauber | 7175f05 | 2016-02-18 17:50:13 +0100 | [diff] [blame] | 623 | } else if (armv8pmu_select_counter(idx) == idx) |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 624 | write_sysreg(value, pmxevcntr_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 625 | } |
| 626 | |
| 627 | static inline void armv8pmu_write_evtype(int idx, u32 val) |
| 628 | { |
| 629 | if (armv8pmu_select_counter(idx) == idx) { |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 630 | val &= ARMV8_PMU_EVTYPE_MASK; |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 631 | write_sysreg(val, pmxevtyper_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 632 | } |
| 633 | } |
| 634 | |
| 635 | static inline int armv8pmu_enable_counter(int idx) |
| 636 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 637 | u32 counter = ARMV8_IDX_TO_COUNTER(idx); |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 638 | write_sysreg(BIT(counter), pmcntenset_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 639 | return idx; |
| 640 | } |
| 641 | |
| 642 | static inline int armv8pmu_disable_counter(int idx) |
| 643 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 644 | u32 counter = ARMV8_IDX_TO_COUNTER(idx); |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 645 | write_sysreg(BIT(counter), pmcntenclr_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 646 | return idx; |
| 647 | } |
| 648 | |
| 649 | static inline int armv8pmu_enable_intens(int idx) |
| 650 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 651 | u32 counter = ARMV8_IDX_TO_COUNTER(idx); |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 652 | write_sysreg(BIT(counter), pmintenset_el1); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 653 | return idx; |
| 654 | } |
| 655 | |
| 656 | static inline int armv8pmu_disable_intens(int idx) |
| 657 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 658 | u32 counter = ARMV8_IDX_TO_COUNTER(idx); |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 659 | write_sysreg(BIT(counter), pmintenclr_el1); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 660 | isb(); |
| 661 | /* Clear the overflow flag in case an interrupt is pending. */ |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 662 | write_sysreg(BIT(counter), pmovsclr_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 663 | isb(); |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 664 | |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 665 | return idx; |
| 666 | } |
| 667 | |
| 668 | static inline u32 armv8pmu_getreset_flags(void) |
| 669 | { |
| 670 | u32 value; |
| 671 | |
| 672 | /* Read */ |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 673 | value = read_sysreg(pmovsclr_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 674 | |
| 675 | /* Write to clear flags */ |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 676 | value &= ARMV8_PMU_OVSR_MASK; |
Ashok Kumar | bf2d478 | 2016-04-21 05:58:43 -0700 | [diff] [blame] | 677 | write_sysreg(value, pmovsclr_el0); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 678 | |
| 679 | return value; |
| 680 | } |
| 681 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 682 | static void armv8pmu_enable_event(struct perf_event *event) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 683 | { |
| 684 | unsigned long flags; |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 685 | struct hw_perf_event *hwc = &event->hw; |
| 686 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
| 687 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
| 688 | int idx = hwc->idx; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 689 | |
| 690 | /* |
| 691 | * Enable counter and interrupt, and set the counter to count |
| 692 | * the event that we're interested in. |
| 693 | */ |
| 694 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
| 695 | |
| 696 | /* |
| 697 | * Disable counter |
| 698 | */ |
| 699 | armv8pmu_disable_counter(idx); |
| 700 | |
| 701 | /* |
| 702 | * Set event (if destined for PMNx counters). |
| 703 | */ |
| 704 | armv8pmu_write_evtype(idx, hwc->config_base); |
| 705 | |
| 706 | /* |
| 707 | * Enable interrupt for this counter |
| 708 | */ |
| 709 | armv8pmu_enable_intens(idx); |
| 710 | |
| 711 | /* |
| 712 | * Enable counter |
| 713 | */ |
| 714 | armv8pmu_enable_counter(idx); |
| 715 | |
| 716 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
| 717 | } |
| 718 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 719 | static void armv8pmu_disable_event(struct perf_event *event) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 720 | { |
| 721 | unsigned long flags; |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 722 | struct hw_perf_event *hwc = &event->hw; |
| 723 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
| 724 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
| 725 | int idx = hwc->idx; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 726 | |
| 727 | /* |
| 728 | * Disable counter and interrupt |
| 729 | */ |
| 730 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
| 731 | |
| 732 | /* |
| 733 | * Disable counter |
| 734 | */ |
| 735 | armv8pmu_disable_counter(idx); |
| 736 | |
| 737 | /* |
| 738 | * Disable interrupt for this counter |
| 739 | */ |
| 740 | armv8pmu_disable_intens(idx); |
| 741 | |
| 742 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
| 743 | } |
| 744 | |
| 745 | static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev) |
| 746 | { |
| 747 | u32 pmovsr; |
| 748 | struct perf_sample_data data; |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 749 | struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev; |
| 750 | struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 751 | struct pt_regs *regs; |
| 752 | int idx; |
| 753 | |
| 754 | /* |
| 755 | * Get and reset the IRQ flags |
| 756 | */ |
| 757 | pmovsr = armv8pmu_getreset_flags(); |
| 758 | |
| 759 | /* |
| 760 | * Did an overflow occur? |
| 761 | */ |
| 762 | if (!armv8pmu_has_overflowed(pmovsr)) |
| 763 | return IRQ_NONE; |
| 764 | |
| 765 | /* |
| 766 | * Handle the counter(s) overflow(s) |
| 767 | */ |
| 768 | regs = get_irq_regs(); |
| 769 | |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 770 | for (idx = 0; idx < cpu_pmu->num_events; ++idx) { |
| 771 | struct perf_event *event = cpuc->events[idx]; |
| 772 | struct hw_perf_event *hwc; |
| 773 | |
| 774 | /* Ignore if we don't have an event. */ |
| 775 | if (!event) |
| 776 | continue; |
| 777 | |
| 778 | /* |
| 779 | * We have a single interrupt for all counters. Check that |
| 780 | * each counter has overflowed before we process it. |
| 781 | */ |
| 782 | if (!armv8pmu_counter_has_overflowed(pmovsr, idx)) |
| 783 | continue; |
| 784 | |
| 785 | hwc = &event->hw; |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 786 | armpmu_event_update(event); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 787 | perf_sample_data_init(&data, 0, hwc->last_period); |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 788 | if (!armpmu_event_set_period(event)) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 789 | continue; |
| 790 | |
| 791 | if (perf_event_overflow(event, &data, regs)) |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 792 | cpu_pmu->disable(event); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 793 | } |
| 794 | |
| 795 | /* |
| 796 | * Handle the pending perf events. |
| 797 | * |
| 798 | * Note: this call *must* be run with interrupts disabled. For |
| 799 | * platforms that can have the PMU interrupts raised as an NMI, this |
| 800 | * will not work. |
| 801 | */ |
| 802 | irq_work_run(); |
| 803 | |
| 804 | return IRQ_HANDLED; |
| 805 | } |
| 806 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 807 | static void armv8pmu_start(struct arm_pmu *cpu_pmu) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 808 | { |
| 809 | unsigned long flags; |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 810 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 811 | |
| 812 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
| 813 | /* Enable all counters */ |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 814 | armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 815 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
| 816 | } |
| 817 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 818 | static void armv8pmu_stop(struct arm_pmu *cpu_pmu) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 819 | { |
| 820 | unsigned long flags; |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 821 | struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 822 | |
| 823 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
| 824 | /* Disable all counters */ |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 825 | armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 826 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
| 827 | } |
| 828 | |
| 829 | static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 830 | struct perf_event *event) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 831 | { |
| 832 | int idx; |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 833 | struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); |
| 834 | struct hw_perf_event *hwc = &event->hw; |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 835 | unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 836 | |
| 837 | /* Always place a cycle counter into the cycle counter. */ |
Ashok Kumar | 03598fd | 2016-04-21 05:58:41 -0700 | [diff] [blame] | 838 | if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) { |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 839 | if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) |
| 840 | return -EAGAIN; |
| 841 | |
| 842 | return ARMV8_IDX_CYCLE_COUNTER; |
| 843 | } |
| 844 | |
| 845 | /* |
| 846 | * For anything other than a cycle counter, try and use |
| 847 | * the events counters |
| 848 | */ |
| 849 | for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) { |
| 850 | if (!test_and_set_bit(idx, cpuc->used_mask)) |
| 851 | return idx; |
| 852 | } |
| 853 | |
| 854 | /* The counters are all in use. */ |
| 855 | return -EAGAIN; |
| 856 | } |
| 857 | |
| 858 | /* |
| 859 | * Add an event filter to a given event. This will only work for PMUv2 PMUs. |
| 860 | */ |
| 861 | static int armv8pmu_set_event_filter(struct hw_perf_event *event, |
| 862 | struct perf_event_attr *attr) |
| 863 | { |
| 864 | unsigned long config_base = 0; |
| 865 | |
| 866 | if (attr->exclude_idle) |
| 867 | return -EPERM; |
Marc Zyngier | d98ecda | 2016-01-25 17:31:13 +0000 | [diff] [blame] | 868 | if (is_kernel_in_hyp_mode() && |
| 869 | attr->exclude_kernel != attr->exclude_hv) |
| 870 | return -EINVAL; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 871 | if (attr->exclude_user) |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 872 | config_base |= ARMV8_PMU_EXCLUDE_EL0; |
Marc Zyngier | d98ecda | 2016-01-25 17:31:13 +0000 | [diff] [blame] | 873 | if (!is_kernel_in_hyp_mode() && attr->exclude_kernel) |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 874 | config_base |= ARMV8_PMU_EXCLUDE_EL1; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 875 | if (!attr->exclude_hv) |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 876 | config_base |= ARMV8_PMU_INCLUDE_EL2; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 877 | |
| 878 | /* |
| 879 | * Install the filter into config_base as this is used to |
| 880 | * construct the event type. |
| 881 | */ |
| 882 | event->config_base = config_base; |
| 883 | |
| 884 | return 0; |
| 885 | } |
| 886 | |
| 887 | static void armv8pmu_reset(void *info) |
| 888 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 889 | struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 890 | u32 idx, nb_cnt = cpu_pmu->num_events; |
| 891 | |
| 892 | /* The counter and interrupt enable registers are unknown at reset. */ |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 893 | for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { |
| 894 | armv8pmu_disable_counter(idx); |
| 895 | armv8pmu_disable_intens(idx); |
| 896 | } |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 897 | |
Jan Glauber | 7175f05 | 2016-02-18 17:50:13 +0100 | [diff] [blame] | 898 | /* |
| 899 | * Initialize & Reset PMNC. Request overflow interrupt for |
| 900 | * 64 bit cycle counter but cheat in armv8pmu_write_counter(). |
| 901 | */ |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 902 | armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | |
| 903 | ARMV8_PMU_PMCR_LC); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 904 | } |
| 905 | |
| 906 | static int armv8_pmuv3_map_event(struct perf_event *event) |
| 907 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 908 | return armpmu_map_event(event, &armv8_pmuv3_perf_map, |
Vinayak Kale | c019de3 | 2013-10-18 13:59:06 +0100 | [diff] [blame] | 909 | &armv8_pmuv3_perf_cache_map, |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 910 | ARMV8_PMU_EVTYPE_EVENT); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 911 | } |
| 912 | |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 913 | static int armv8_a53_map_event(struct perf_event *event) |
| 914 | { |
| 915 | return armpmu_map_event(event, &armv8_a53_perf_map, |
| 916 | &armv8_a53_perf_cache_map, |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 917 | ARMV8_PMU_EVTYPE_EVENT); |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 918 | } |
| 919 | |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 920 | static int armv8_a57_map_event(struct perf_event *event) |
| 921 | { |
| 922 | return armpmu_map_event(event, &armv8_a57_perf_map, |
| 923 | &armv8_a57_perf_cache_map, |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 924 | ARMV8_PMU_EVTYPE_EVENT); |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 925 | } |
| 926 | |
Jan Glauber | d0aa2bf | 2016-02-18 17:50:11 +0100 | [diff] [blame] | 927 | static int armv8_thunder_map_event(struct perf_event *event) |
| 928 | { |
| 929 | return armpmu_map_event(event, &armv8_thunder_perf_map, |
| 930 | &armv8_thunder_perf_cache_map, |
Shannon Zhao | b8cfadf | 2016-03-24 16:01:16 +0000 | [diff] [blame] | 931 | ARMV8_PMU_EVTYPE_EVENT); |
Jan Glauber | d0aa2bf | 2016-02-18 17:50:11 +0100 | [diff] [blame] | 932 | } |
| 933 | |
Ashok Kumar | 201a72b | 2016-04-21 05:58:45 -0700 | [diff] [blame] | 934 | static int armv8_vulcan_map_event(struct perf_event *event) |
| 935 | { |
| 936 | return armpmu_map_event(event, &armv8_vulcan_perf_map, |
| 937 | &armv8_vulcan_perf_cache_map, |
| 938 | ARMV8_PMU_EVTYPE_EVENT); |
| 939 | } |
| 940 | |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 941 | static void __armv8pmu_probe_pmu(void *info) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 942 | { |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 943 | struct arm_pmu *cpu_pmu = info; |
| 944 | u32 pmceid[2]; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 945 | |
| 946 | /* Read the nb of CNTx counters supported from PMNC */ |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 947 | cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT) |
| 948 | & ARMV8_PMU_PMCR_N_MASK; |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 949 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 950 | /* Add the CPU cycles counter */ |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 951 | cpu_pmu->num_events += 1; |
| 952 | |
| 953 | pmceid[0] = read_sysreg(pmceid0_el0); |
| 954 | pmceid[1] = read_sysreg(pmceid1_el0); |
| 955 | |
| 956 | bitmap_from_u32array(cpu_pmu->pmceid_bitmap, |
| 957 | ARMV8_PMUV3_MAX_COMMON_EVENTS, pmceid, |
| 958 | ARRAY_SIZE(pmceid)); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 959 | } |
| 960 | |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 961 | static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 962 | { |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 963 | return smp_call_function_any(&cpu_pmu->supported_cpus, |
| 964 | __armv8pmu_probe_pmu, |
| 965 | cpu_pmu, 1); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 966 | } |
| 967 | |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 968 | static void armv8_pmu_init(struct arm_pmu *cpu_pmu) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 969 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 970 | cpu_pmu->handle_irq = armv8pmu_handle_irq, |
| 971 | cpu_pmu->enable = armv8pmu_enable_event, |
| 972 | cpu_pmu->disable = armv8pmu_disable_event, |
| 973 | cpu_pmu->read_counter = armv8pmu_read_counter, |
| 974 | cpu_pmu->write_counter = armv8pmu_write_counter, |
| 975 | cpu_pmu->get_event_idx = armv8pmu_get_event_idx, |
| 976 | cpu_pmu->start = armv8pmu_start, |
| 977 | cpu_pmu->stop = armv8pmu_stop, |
| 978 | cpu_pmu->reset = armv8pmu_reset, |
| 979 | cpu_pmu->max_period = (1LLU << 32) - 1, |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 980 | cpu_pmu->set_event_filter = armv8pmu_set_event_filter; |
| 981 | } |
| 982 | |
| 983 | static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu) |
| 984 | { |
| 985 | armv8_pmu_init(cpu_pmu); |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 986 | cpu_pmu->name = "armv8_pmuv3"; |
| 987 | cpu_pmu->map_event = armv8_pmuv3_map_event; |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 988 | cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups; |
| 989 | return armv8pmu_probe_pmu(cpu_pmu); |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 990 | } |
| 991 | |
| 992 | static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu) |
| 993 | { |
| 994 | armv8_pmu_init(cpu_pmu); |
| 995 | cpu_pmu->name = "armv8_cortex_a53"; |
| 996 | cpu_pmu->map_event = armv8_a53_map_event; |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 997 | cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups; |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 998 | return armv8pmu_probe_pmu(cpu_pmu); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 999 | } |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1000 | |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 1001 | static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu) |
| 1002 | { |
| 1003 | armv8_pmu_init(cpu_pmu); |
| 1004 | cpu_pmu->name = "armv8_cortex_a57"; |
| 1005 | cpu_pmu->map_event = armv8_a57_map_event; |
Drew Richardson | 9e9caa6 | 2015-10-22 07:07:32 -0700 | [diff] [blame] | 1006 | cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups; |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 1007 | return armv8pmu_probe_pmu(cpu_pmu); |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 1008 | } |
| 1009 | |
Will Deacon | 5d7ee87 | 2015-12-22 14:45:35 +0000 | [diff] [blame] | 1010 | static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu) |
| 1011 | { |
| 1012 | armv8_pmu_init(cpu_pmu); |
| 1013 | cpu_pmu->name = "armv8_cortex_a72"; |
| 1014 | cpu_pmu->map_event = armv8_a57_map_event; |
| 1015 | cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups; |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 1016 | return armv8pmu_probe_pmu(cpu_pmu); |
Will Deacon | 5d7ee87 | 2015-12-22 14:45:35 +0000 | [diff] [blame] | 1017 | } |
| 1018 | |
Jan Glauber | d0aa2bf | 2016-02-18 17:50:11 +0100 | [diff] [blame] | 1019 | static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu) |
| 1020 | { |
| 1021 | armv8_pmu_init(cpu_pmu); |
| 1022 | cpu_pmu->name = "armv8_cavium_thunder"; |
| 1023 | cpu_pmu->map_event = armv8_thunder_map_event; |
| 1024 | cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups; |
Ashok Kumar | 4b1a9e6 | 2016-04-21 05:58:44 -0700 | [diff] [blame] | 1025 | return armv8pmu_probe_pmu(cpu_pmu); |
Jan Glauber | d0aa2bf | 2016-02-18 17:50:11 +0100 | [diff] [blame] | 1026 | } |
| 1027 | |
Ashok Kumar | 201a72b | 2016-04-21 05:58:45 -0700 | [diff] [blame] | 1028 | static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu) |
| 1029 | { |
| 1030 | armv8_pmu_init(cpu_pmu); |
| 1031 | cpu_pmu->name = "armv8_brcm_vulcan"; |
| 1032 | cpu_pmu->map_event = armv8_vulcan_map_event; |
| 1033 | cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups; |
| 1034 | return armv8pmu_probe_pmu(cpu_pmu); |
| 1035 | } |
| 1036 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 1037 | static const struct of_device_id armv8_pmu_of_device_ids[] = { |
| 1038 | {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init}, |
Mark Rutland | ac82d12 | 2015-10-02 10:55:04 +0100 | [diff] [blame] | 1039 | {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init}, |
Mark Rutland | 62a4dda | 2015-10-02 10:55:05 +0100 | [diff] [blame] | 1040 | {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init}, |
Will Deacon | 5d7ee87 | 2015-12-22 14:45:35 +0000 | [diff] [blame] | 1041 | {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init}, |
Jan Glauber | d0aa2bf | 2016-02-18 17:50:11 +0100 | [diff] [blame] | 1042 | {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init}, |
Ashok Kumar | 201a72b | 2016-04-21 05:58:45 -0700 | [diff] [blame] | 1043 | {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init}, |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1044 | {}, |
| 1045 | }; |
| 1046 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 1047 | static int armv8_pmu_device_probe(struct platform_device *pdev) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1048 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 1049 | return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1050 | } |
| 1051 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 1052 | static struct platform_driver armv8_pmu_driver = { |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1053 | .driver = { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 1054 | .name = "armv8-pmu", |
| 1055 | .of_match_table = armv8_pmu_of_device_ids, |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1056 | }, |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 1057 | .probe = armv8_pmu_device_probe, |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1058 | }; |
| 1059 | |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 1060 | static int __init register_armv8_pmu_driver(void) |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1061 | { |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 1062 | return platform_driver_register(&armv8_pmu_driver); |
Will Deacon | 0308968 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1063 | } |
Mark Rutland | 6475b2d | 2015-10-02 10:55:03 +0100 | [diff] [blame] | 1064 | device_initcall(register_armv8_pmu_driver); |