Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Local APIC handling, local APIC timers |
| 3 | * |
Ingo Molnar | 8f47e16 | 2009-01-31 02:03:42 +0100 | [diff] [blame] | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * Fixes |
| 7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
| 8 | * thanks to Eric Gilmore |
| 9 | * and Rolf G. Tews |
| 10 | * for testing these extensively. |
| 11 | * Maciej W. Rozycki : Various updates and fixes. |
| 12 | * Mikael Pettersson : Power Management for UP-APIC. |
| 13 | * Pavel Machek and |
| 14 | * Mikael Pettersson : PM converted to driver model. |
| 15 | */ |
| 16 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 17 | #include <linux/perf_event.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/kernel_stat.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 19 | #include <linux/mc146818rtc.h> |
Thomas Gleixner | 70a2002 | 2008-01-30 13:30:18 +0100 | [diff] [blame] | 20 | #include <linux/acpi_pmtmr.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 21 | #include <linux/clockchips.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/bootmem.h> |
Frederic Weisbecker | bcbc4f2 | 2008-12-09 23:54:20 +0100 | [diff] [blame] | 24 | #include <linux/ftrace.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 25 | #include <linux/ioport.h> |
Paul Gortmaker | 186f436 | 2016-07-13 20:18:56 -0400 | [diff] [blame] | 26 | #include <linux/export.h> |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 27 | #include <linux/syscore_ops.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 28 | #include <linux/delay.h> |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 29 | #include <linux/timex.h> |
Ralf Baechle | 334955e | 2011-06-01 19:04:57 +0100 | [diff] [blame] | 30 | #include <linux/i8253.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 31 | #include <linux/dmar.h> |
| 32 | #include <linux/init.h> |
| 33 | #include <linux/cpu.h> |
| 34 | #include <linux/dmi.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 35 | #include <linux/smp.h> |
| 36 | #include <linux/mm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
Steven Rostedt (Red Hat) | 83ab851 | 2013-06-21 10:29:05 -0400 | [diff] [blame] | 38 | #include <asm/trace/irq_vectors.h> |
Suresh Siddha | 8a8f422 | 2012-03-30 11:47:08 -0700 | [diff] [blame] | 39 | #include <asm/irq_remapping.h> |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 40 | #include <asm/perf_event.h> |
Thomas Gleixner | 736deca | 2009-08-19 12:35:53 +0200 | [diff] [blame] | 41 | #include <asm/x86_init.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | #include <asm/pgalloc.h> |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 43 | #include <linux/atomic.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 44 | #include <asm/mpspec.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 45 | #include <asm/i8259.h> |
Andi Kleen | 73dea47 | 2006-02-03 21:50:50 +0100 | [diff] [blame] | 46 | #include <asm/proto.h> |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 47 | #include <asm/apic.h> |
Henrik Kretzschmar | 7167d08 | 2011-02-22 15:38:05 +0100 | [diff] [blame] | 48 | #include <asm/io_apic.h> |
Ingo Molnar | d1de36f | 2009-01-31 01:59:14 +0100 | [diff] [blame] | 49 | #include <asm/desc.h> |
| 50 | #include <asm/hpet.h> |
| 51 | #include <asm/idle.h> |
| 52 | #include <asm/mtrr.h> |
Ralf Baechle | 16f871b | 2011-06-01 19:05:06 +0100 | [diff] [blame] | 53 | #include <asm/time.h> |
Jaswinder Singh Rajput | 2bc1379 | 2009-01-11 20:34:47 +0530 | [diff] [blame] | 54 | #include <asm/smp.h> |
Andi Kleen | be71b85 | 2009-02-12 13:49:38 +0100 | [diff] [blame] | 55 | #include <asm/mce.h> |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 56 | #include <asm/tsc.h> |
Sheng Yang | 2904ed8 | 2010-12-21 14:18:48 +0800 | [diff] [blame] | 57 | #include <asm/hypervisor.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 59 | unsigned int num_processors; |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 60 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 61 | unsigned disabled_cpus; |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 62 | |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 63 | /* Processor that is doing the boot up */ |
| 64 | unsigned int boot_cpu_physical_apicid = -1U; |
David Rientjes | cc08e04 | 2013-11-14 15:05:32 -0800 | [diff] [blame] | 65 | EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); |
Glauber Costa | 5af5573 | 2008-03-25 13:28:56 -0300 | [diff] [blame] | 66 | |
Cyrill Gorcunov | 80e5609 | 2008-08-24 02:01:42 -0700 | [diff] [blame] | 67 | /* |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 68 | * The highest APIC ID seen during enumeration. |
Cyrill Gorcunov | 80e5609 | 2008-08-24 02:01:42 -0700 | [diff] [blame] | 69 | */ |
Jiang Liu | a491cc902 | 2014-06-09 16:19:32 +0800 | [diff] [blame] | 70 | static unsigned int max_physical_apicid; |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 71 | |
Ingo Molnar | fdbecd9 | 2009-01-31 03:57:12 +0100 | [diff] [blame] | 72 | /* |
| 73 | * Bitmask of physically existing CPUs: |
| 74 | */ |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 75 | physid_mask_t phys_cpu_present_map; |
| 76 | |
| 77 | /* |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 78 | * Processor to be disabled specified by kernel parameter |
| 79 | * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to |
| 80 | * avoid undefined behaviour caused by sending INIT from AP to BSP. |
| 81 | */ |
H. Peter Anvin | 5b4d1db | 2014-01-15 13:02:08 -0800 | [diff] [blame] | 82 | static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 83 | |
| 84 | /* |
Hidehiro Kawai | b7c4948 | 2015-12-14 11:19:12 +0100 | [diff] [blame] | 85 | * This variable controls which CPUs receive external NMIs. By default, |
| 86 | * external NMIs are delivered only to the BSP. |
| 87 | */ |
| 88 | static int apic_extnmi = APIC_EXTNMI_BSP; |
| 89 | |
| 90 | /* |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 91 | * Map cpu index to physical APIC ID |
| 92 | */ |
Vlad Zolotarov | 0816b0f | 2012-06-11 12:56:52 +0300 | [diff] [blame] | 93 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); |
| 94 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); |
Vitaly Kuznetsov | 3e9e57f | 2016-06-30 17:56:36 +0200 | [diff] [blame] | 95 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); |
Brian Gerst | ec70de8 | 2009-01-27 12:56:47 +0900 | [diff] [blame] | 96 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); |
| 97 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); |
Vitaly Kuznetsov | 3e9e57f | 2016-06-30 17:56:36 +0200 | [diff] [blame] | 98 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); |
Cyrill Gorcunov | 80e5609 | 2008-08-24 02:01:42 -0700 | [diff] [blame] | 99 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 100 | #ifdef CONFIG_X86_32 |
Tejun Heo | 4c321ff | 2011-01-23 14:37:30 +0100 | [diff] [blame] | 101 | |
Tejun Heo | 4c321ff | 2011-01-23 14:37:30 +0100 | [diff] [blame] | 102 | /* |
| 103 | * On x86_32, the mapping between cpu and logical apicid may vary |
| 104 | * depending on apic in use. The following early percpu variable is |
| 105 | * used for the mapping. This is where the behaviors of x86_64 and 32 |
| 106 | * actually diverge. Let's keep it ugly for now. |
| 107 | */ |
Vlad Zolotarov | 0816b0f | 2012-06-11 12:56:52 +0300 | [diff] [blame] | 108 | DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); |
Tejun Heo | 4c321ff | 2011-01-23 14:37:30 +0100 | [diff] [blame] | 109 | |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 110 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
| 111 | static int enabled_via_apicbase; |
| 112 | |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 113 | /* |
| 114 | * Handle interrupt mode configuration register (IMCR). |
| 115 | * This register controls whether the interrupt signals |
| 116 | * that reach the BSP come from the master PIC or from the |
| 117 | * local APIC. Before entering Symmetric I/O Mode, either |
| 118 | * the BIOS or the operating system must switch out of |
| 119 | * PIC Mode by changing the IMCR. |
| 120 | */ |
Alexander van Heukelum | 5cda395 | 2009-04-13 17:39:24 +0200 | [diff] [blame] | 121 | static inline void imcr_pic_to_apic(void) |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 122 | { |
| 123 | /* select IMCR register */ |
| 124 | outb(0x70, 0x22); |
| 125 | /* NMI and 8259 INTR go through APIC */ |
| 126 | outb(0x01, 0x23); |
| 127 | } |
| 128 | |
Alexander van Heukelum | 5cda395 | 2009-04-13 17:39:24 +0200 | [diff] [blame] | 129 | static inline void imcr_apic_to_pic(void) |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 130 | { |
| 131 | /* select IMCR register */ |
| 132 | outb(0x70, 0x22); |
| 133 | /* NMI and 8259 INTR go directly to BSP */ |
| 134 | outb(0x00, 0x23); |
| 135 | } |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 136 | #endif |
| 137 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 138 | /* |
| 139 | * Knob to control our willingness to enable the local APIC. |
| 140 | * |
| 141 | * +1=force-enable |
| 142 | */ |
| 143 | static int force_enable_local_apic __initdata; |
David Rientjes | dc9788f | 2014-02-04 23:55:06 -0800 | [diff] [blame] | 144 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 145 | /* |
| 146 | * APIC command line parameters |
| 147 | */ |
| 148 | static int __init parse_lapic(char *arg) |
| 149 | { |
Masahiro Yamada | 97f2645 | 2016-08-03 13:45:50 -0700 | [diff] [blame] | 150 | if (IS_ENABLED(CONFIG_X86_32) && !arg) |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 151 | force_enable_local_apic = 1; |
Mathias Krause | 27cf929 | 2013-02-19 20:47:07 +0100 | [diff] [blame] | 152 | else if (arg && !strncmp(arg, "notscdeadline", 13)) |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 153 | setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); |
| 154 | return 0; |
| 155 | } |
| 156 | early_param("lapic", parse_lapic); |
| 157 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 158 | #ifdef CONFIG_X86_64 |
Chris Wright | bc1d99c | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 159 | static int apic_calibrate_pmtmr __initdata; |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 160 | static __init int setup_apicpmtimer(char *s) |
| 161 | { |
| 162 | apic_calibrate_pmtmr = 1; |
| 163 | notsc_setup(NULL); |
| 164 | return 0; |
| 165 | } |
| 166 | __setup("apicpmtimer", setup_apicpmtimer); |
| 167 | #endif |
| 168 | |
Yinghai Lu | b3c5117 | 2008-08-24 02:01:46 -0700 | [diff] [blame] | 169 | unsigned long mp_lapic_addr; |
| 170 | int disable_apic; |
| 171 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 172 | static int disable_apic_timer __initdata; |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 173 | /* Local APIC timer works in C2 */ |
Linus Torvalds | 2e7c283 | 2007-03-23 11:32:31 -0700 | [diff] [blame] | 174 | int local_apic_timer_c2_ok; |
| 175 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); |
| 176 | |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 177 | int first_system_vector = FIRST_SYSTEM_VECTOR; |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 178 | |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 179 | /* |
| 180 | * Debug level, exported for io_apic.c |
| 181 | */ |
Maciej W. Rozycki | baa1318 | 2008-07-14 18:44:51 +0100 | [diff] [blame] | 182 | unsigned int apic_verbosity; |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 183 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 184 | int pic_mode; |
| 185 | |
Alexey Starikovskiy | bab4b27 | 2008-05-19 19:47:03 +0400 | [diff] [blame] | 186 | /* Have we found an MP table */ |
| 187 | int smp_found_config; |
| 188 | |
Aaron Durbin | 3992872 | 2006-12-07 02:14:01 +0100 | [diff] [blame] | 189 | static struct resource lapic_resource = { |
| 190 | .name = "Local APIC", |
| 191 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, |
| 192 | }; |
| 193 | |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 194 | unsigned int lapic_timer_frequency = 0; |
Thomas Gleixner | d03030e | 2007-10-12 23:04:06 +0200 | [diff] [blame] | 195 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 196 | static void apic_pm_activate(void); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 197 | |
Andi Kleen | d343289 | 2008-01-30 13:33:17 +0100 | [diff] [blame] | 198 | static unsigned long apic_phys; |
| 199 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 200 | /* |
| 201 | * Get the LAPIC version |
| 202 | */ |
| 203 | static inline int lapic_get_version(void) |
| 204 | { |
| 205 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 206 | } |
| 207 | |
| 208 | /* |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 209 | * Check, if the APIC is integrated or a separate chip |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 210 | */ |
| 211 | static inline int lapic_is_integrated(void) |
| 212 | { |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 213 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 214 | return 1; |
Cyrill Gorcunov | 9c80386 | 2008-08-16 23:21:54 +0400 | [diff] [blame] | 215 | #else |
| 216 | return APIC_INTEGRATED(lapic_get_version()); |
| 217 | #endif |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | /* |
| 221 | * Check, whether this is a modern or a first generation APIC |
| 222 | */ |
| 223 | static int modern_apic(void) |
| 224 | { |
| 225 | /* AMD systems use old APIC versions, so check the CPU */ |
| 226 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
| 227 | boot_cpu_data.x86 >= 0xf) |
| 228 | return 1; |
| 229 | return lapic_get_version() >= 0x14; |
| 230 | } |
| 231 | |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 232 | /* |
Cyrill Gorcunov | a933c61 | 2009-10-14 00:07:04 +0400 | [diff] [blame] | 233 | * right after this call apic become NOOP driven |
| 234 | * so apic->write/read doesn't do anything |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 235 | */ |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 236 | static void __init apic_disable(void) |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 237 | { |
Cyrill Gorcunov | f88f2b4 | 2009-10-15 19:04:16 +0400 | [diff] [blame] | 238 | pr_info("APIC: switched to apic NOOP\n"); |
Cyrill Gorcunov | a933c61 | 2009-10-14 00:07:04 +0400 | [diff] [blame] | 239 | apic = &apic_noop; |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 240 | } |
| 241 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 242 | void native_apic_wait_icr_idle(void) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 243 | { |
| 244 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) |
| 245 | cpu_relax(); |
| 246 | } |
| 247 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 248 | u32 native_safe_apic_wait_icr_idle(void) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 249 | { |
| 250 | u32 send_status; |
| 251 | int timeout; |
| 252 | |
| 253 | timeout = 0; |
| 254 | do { |
| 255 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; |
| 256 | if (!send_status) |
| 257 | break; |
Fernando Luis Vazquez Cao | b49d7d8 | 2011-12-15 11:32:24 +0900 | [diff] [blame] | 258 | inc_irq_stat(icr_read_retry_count); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 259 | udelay(100); |
| 260 | } while (timeout++ < 1000); |
| 261 | |
| 262 | return send_status; |
| 263 | } |
| 264 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 265 | void native_apic_icr_write(u32 low, u32 id) |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 266 | { |
Jan Kiszka | ea7bdc6 | 2014-01-27 20:14:06 +0100 | [diff] [blame] | 267 | unsigned long flags; |
| 268 | |
| 269 | local_irq_save(flags); |
Cyrill Gorcunov | ed4e5ec | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 270 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 271 | apic_write(APIC_ICR, low); |
Jan Kiszka | ea7bdc6 | 2014-01-27 20:14:06 +0100 | [diff] [blame] | 272 | local_irq_restore(flags); |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 273 | } |
| 274 | |
Yinghai Lu | c1eeb2d | 2009-02-16 23:02:14 -0800 | [diff] [blame] | 275 | u64 native_apic_icr_read(void) |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 276 | { |
| 277 | u32 icr1, icr2; |
| 278 | |
| 279 | icr2 = apic_read(APIC_ICR2); |
| 280 | icr1 = apic_read(APIC_ICR); |
| 281 | |
Cyrill Gorcunov | cf9768d7 | 2008-08-16 23:21:55 +0400 | [diff] [blame] | 282 | return icr1 | ((u64)icr2 << 32); |
Suresh Siddha | 1b374e4 | 2008-07-10 11:16:49 -0700 | [diff] [blame] | 283 | } |
| 284 | |
Cyrill Gorcunov | 7c37e48 | 2008-08-24 02:01:40 -0700 | [diff] [blame] | 285 | #ifdef CONFIG_X86_32 |
| 286 | /** |
| 287 | * get_physical_broadcast - Get number of physical broadcast IDs |
| 288 | */ |
| 289 | int get_physical_broadcast(void) |
| 290 | { |
| 291 | return modern_apic() ? 0xff : 0xf; |
| 292 | } |
| 293 | #endif |
| 294 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 295 | /** |
| 296 | * lapic_get_maxlvt - get the maximum number of local vector table entries |
| 297 | */ |
| 298 | int lapic_get_maxlvt(void) |
| 299 | { |
Cyrill Gorcunov | 36a028d | 2008-07-24 13:52:28 +0200 | [diff] [blame] | 300 | unsigned int v; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 301 | |
| 302 | v = apic_read(APIC_LVR); |
Cyrill Gorcunov | 36a028d | 2008-07-24 13:52:28 +0200 | [diff] [blame] | 303 | /* |
| 304 | * - we always have APIC integrated on 64bit mode |
| 305 | * - 82489DXs do not report # of LVT entries |
| 306 | */ |
| 307 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 308 | } |
| 309 | |
| 310 | /* |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 311 | * Local APIC timer |
| 312 | */ |
| 313 | |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 314 | /* Clock divisor */ |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 315 | #define APIC_DIVISOR 16 |
Nicolai Stange | 1a9e4c5 | 2016-07-14 17:22:54 +0200 | [diff] [blame] | 316 | #define TSC_DIVISOR 8 |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 317 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 318 | /* |
| 319 | * This function sets up the local APIC timer, with a timeout of |
| 320 | * 'clocks' APIC bus clock. During calibration we actually call |
| 321 | * this function twice on the boot CPU, once with a bogus timeout |
| 322 | * value, second time for real. The other (noncalibrating) CPUs |
| 323 | * call this function only once, with the real, calibrated value. |
| 324 | * |
| 325 | * We do reads before writes even if unnecessary, to get around the |
| 326 | * P5 APIC double write bug. |
| 327 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 328 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
| 329 | { |
| 330 | unsigned int lvtt_value, tmp_value; |
| 331 | |
| 332 | lvtt_value = LOCAL_TIMER_VECTOR; |
| 333 | if (!oneshot) |
| 334 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 335 | else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
| 336 | lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; |
| 337 | |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 338 | if (!lapic_is_integrated()) |
| 339 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); |
| 340 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 341 | if (!irqen) |
| 342 | lvtt_value |= APIC_LVT_MASKED; |
| 343 | |
| 344 | apic_write(APIC_LVTT, lvtt_value); |
| 345 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 346 | if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { |
Shaohua Li | 5d7c631 | 2015-07-30 16:24:43 -0700 | [diff] [blame] | 347 | /* |
| 348 | * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, |
| 349 | * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. |
| 350 | * According to Intel, MFENCE can do the serialization here. |
| 351 | */ |
| 352 | asm volatile("mfence" : : : "memory"); |
| 353 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 354 | printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); |
| 355 | return; |
| 356 | } |
| 357 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 358 | /* |
| 359 | * Divide PICLK by 16 |
| 360 | */ |
| 361 | tmp_value = apic_read(APIC_TDCR); |
Cyrill Gorcunov | c40aaec | 2008-08-18 20:45:55 +0400 | [diff] [blame] | 362 | apic_write(APIC_TDCR, |
| 363 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
| 364 | APIC_TDR_DIV_16); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 365 | |
| 366 | if (!oneshot) |
Cyrill Gorcunov | f07f4f9 | 2008-08-15 13:51:21 +0200 | [diff] [blame] | 367 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 368 | } |
| 369 | |
| 370 | /* |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 371 | * Setup extended LVT, AMD specific |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 372 | * |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 373 | * Software should use the LVT offsets the BIOS provides. The offsets |
| 374 | * are determined by the subsystems using it like those for MCE |
| 375 | * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts |
| 376 | * are supported. Beginning with family 10h at least 4 offsets are |
| 377 | * available. |
Robert Richter | 286f571 | 2008-07-22 21:08:46 +0200 | [diff] [blame] | 378 | * |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 379 | * Since the offsets must be consistent for all cores, we keep track |
| 380 | * of the LVT offsets in software and reserve the offset for the same |
| 381 | * vector also to be used on other cores. An offset is freed by |
| 382 | * setting the entry to APIC_EILVT_MASKED. |
| 383 | * |
| 384 | * If the BIOS is right, there should be no conflicts. Otherwise a |
| 385 | * "[Firmware Bug]: ..." error message is generated. However, if |
| 386 | * software does not properly determines the offsets, it is not |
| 387 | * necessarily a BIOS bug. |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 388 | */ |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 389 | |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 390 | static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 391 | |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 392 | static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) |
| 393 | { |
| 394 | return (old & APIC_EILVT_MASKED) |
| 395 | || (new == APIC_EILVT_MASKED) |
| 396 | || ((new & ~APIC_EILVT_MASKED) == old); |
| 397 | } |
| 398 | |
| 399 | static unsigned int reserve_eilvt_offset(int offset, unsigned int new) |
| 400 | { |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 401 | unsigned int rsvd, vector; |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 402 | |
| 403 | if (offset >= APIC_EILVT_NR_MAX) |
| 404 | return ~0; |
| 405 | |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 406 | rsvd = atomic_read(&eilvt_offsets[offset]); |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 407 | do { |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 408 | vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ |
| 409 | if (vector && !eilvt_entry_is_changeable(vector, new)) |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 410 | /* may not change if vectors are different */ |
| 411 | return rsvd; |
| 412 | rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); |
| 413 | } while (rsvd != new); |
| 414 | |
Robert Richter | 8abc312 | 2012-03-27 20:04:02 +0200 | [diff] [blame] | 415 | rsvd &= ~APIC_EILVT_MASKED; |
| 416 | if (rsvd && rsvd != vector) |
| 417 | pr_info("LVT offset %d assigned for vector 0x%02x\n", |
| 418 | offset, rsvd); |
| 419 | |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 420 | return new; |
| 421 | } |
| 422 | |
| 423 | /* |
| 424 | * If mask=1, the LVT entry does not generate interrupts while mask=0 |
Robert Richter | cbf74ce | 2011-05-30 16:31:11 +0200 | [diff] [blame] | 425 | * enables the vector. See also the BKDGs. Must be called with |
| 426 | * preemption disabled. |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 427 | */ |
| 428 | |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 429 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 430 | { |
| 431 | unsigned long reg = APIC_EILVTn(offset); |
| 432 | unsigned int new, old, reserved; |
| 433 | |
| 434 | new = (mask << 16) | (msg_type << 8) | vector; |
| 435 | old = apic_read(reg); |
| 436 | reserved = reserve_eilvt_offset(offset, new); |
| 437 | |
| 438 | if (reserved != new) { |
Robert Richter | eb48c9c | 2010-10-25 16:03:39 +0200 | [diff] [blame] | 439 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
| 440 | "vector 0x%x, but the register is already in use for " |
| 441 | "vector 0x%x on another cpu\n", |
| 442 | smp_processor_id(), reg, offset, new, reserved); |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 443 | return -EINVAL; |
| 444 | } |
| 445 | |
| 446 | if (!eilvt_entry_is_changeable(old, new)) { |
Robert Richter | eb48c9c | 2010-10-25 16:03:39 +0200 | [diff] [blame] | 447 | pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " |
| 448 | "vector 0x%x, but the register is already in use for " |
| 449 | "vector 0x%x on this cpu\n", |
| 450 | smp_processor_id(), reg, offset, new, old); |
Robert Richter | a68c439 | 2010-10-06 12:27:53 +0200 | [diff] [blame] | 451 | return -EBUSY; |
| 452 | } |
| 453 | |
| 454 | apic_write(reg, new); |
| 455 | |
| 456 | return 0; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 457 | } |
Robert Richter | 27afdf2 | 2010-10-06 12:27:54 +0200 | [diff] [blame] | 458 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt); |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 459 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 460 | /* |
| 461 | * Program the next event, relative to now |
| 462 | */ |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 463 | static int lapic_next_event(unsigned long delta, |
| 464 | struct clock_event_device *evt) |
| 465 | { |
| 466 | apic_write(APIC_TMICT, delta); |
| 467 | return 0; |
| 468 | } |
| 469 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 470 | static int lapic_next_deadline(unsigned long delta, |
| 471 | struct clock_event_device *evt) |
| 472 | { |
| 473 | u64 tsc; |
| 474 | |
Andy Lutomirski | 4ea1636 | 2015-06-25 18:44:07 +0200 | [diff] [blame] | 475 | tsc = rdtsc(); |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 476 | wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); |
| 477 | return 0; |
| 478 | } |
| 479 | |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 480 | static int lapic_timer_shutdown(struct clock_event_device *evt) |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 481 | { |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 482 | unsigned int v; |
| 483 | |
| 484 | /* Lapic used as dummy for broadcast ? */ |
| 485 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 486 | return 0; |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 487 | |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 488 | v = apic_read(APIC_LVTT); |
| 489 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); |
| 490 | apic_write(APIC_LVTT, v); |
| 491 | apic_write(APIC_TMICT, 0); |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 492 | return 0; |
| 493 | } |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 494 | |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 495 | static inline int |
| 496 | lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) |
| 497 | { |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 498 | /* Lapic used as dummy for broadcast ? */ |
| 499 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) |
| 500 | return 0; |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 501 | |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 502 | __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 503 | return 0; |
| 504 | } |
| 505 | |
| 506 | static int lapic_timer_set_periodic(struct clock_event_device *evt) |
| 507 | { |
| 508 | return lapic_timer_set_periodic_oneshot(evt, false); |
| 509 | } |
| 510 | |
| 511 | static int lapic_timer_set_oneshot(struct clock_event_device *evt) |
| 512 | { |
| 513 | return lapic_timer_set_periodic_oneshot(evt, true); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 514 | } |
| 515 | |
| 516 | /* |
| 517 | * Local APIC timer broadcast function |
| 518 | */ |
Mike Travis | 9628937 | 2008-12-31 18:08:46 -0800 | [diff] [blame] | 519 | static void lapic_timer_broadcast(const struct cpumask *mask) |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 520 | { |
| 521 | #ifdef CONFIG_SMP |
Ingo Molnar | dac5f41 | 2009-01-28 15:42:24 +0100 | [diff] [blame] | 522 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
Thomas Gleixner | ba7eda4 | 2007-10-12 23:04:07 +0200 | [diff] [blame] | 523 | #endif |
| 524 | } |
| 525 | |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 526 | |
| 527 | /* |
| 528 | * The local apic timer can be used for any function which is CPU local. |
| 529 | */ |
| 530 | static struct clock_event_device lapic_clockevent = { |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 531 | .name = "lapic", |
| 532 | .features = CLOCK_EVT_FEAT_PERIODIC | |
| 533 | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP |
| 534 | | CLOCK_EVT_FEAT_DUMMY, |
| 535 | .shift = 32, |
| 536 | .set_state_shutdown = lapic_timer_shutdown, |
| 537 | .set_state_periodic = lapic_timer_set_periodic, |
| 538 | .set_state_oneshot = lapic_timer_set_oneshot, |
| 539 | .set_next_event = lapic_next_event, |
| 540 | .broadcast = lapic_timer_broadcast, |
| 541 | .rating = 100, |
| 542 | .irq = -1, |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 543 | }; |
| 544 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); |
| 545 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 546 | /* |
Uwe Kleine-König | 421f91d | 2010-06-11 12:17:00 +0200 | [diff] [blame] | 547 | * Setup the local APIC timer for this CPU. Copy the initialized values |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 548 | * of the boot CPU and register the clock event in the framework. |
| 549 | */ |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 550 | static void setup_APIC_timer(void) |
Fernando Luis VazquezCao | 8339e9f | 2007-05-02 19:27:17 +0200 | [diff] [blame] | 551 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 552 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 553 | |
Christoph Lameter | 349c004 | 2011-03-12 12:50:10 +0100 | [diff] [blame] | 554 | if (this_cpu_has(X86_FEATURE_ARAT)) { |
Venkatesh Pallipadi | db954b5 | 2009-04-06 18:51:29 -0700 | [diff] [blame] | 555 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; |
| 556 | /* Make LAPIC timer preferrable over percpu HPET */ |
| 557 | lapic_clockevent.rating = 150; |
| 558 | } |
| 559 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 560 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
Rusty Russell | 320ab2b | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 561 | levt->cpumask = cpumask_of(smp_processor_id()); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 562 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 563 | if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
| 564 | levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | |
| 565 | CLOCK_EVT_FEAT_DUMMY); |
| 566 | levt->set_next_event = lapic_next_deadline; |
| 567 | clockevents_config_and_register(levt, |
Nicolai Stange | 1a9e4c5 | 2016-07-14 17:22:54 +0200 | [diff] [blame] | 568 | tsc_khz * (1000 / TSC_DIVISOR), |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 569 | 0xF, ~0UL); |
| 570 | } else |
| 571 | clockevents_register_device(levt); |
Fernando Luis VazquezCao | 8339e9f | 2007-05-02 19:27:17 +0200 | [diff] [blame] | 572 | } |
| 573 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 574 | /* |
Nicolai Stange | 6731b0d | 2016-07-14 17:22:55 +0200 | [diff] [blame] | 575 | * Install the updated TSC frequency from recalibration at the TSC |
| 576 | * deadline clockevent devices. |
| 577 | */ |
| 578 | static void __lapic_update_tsc_freq(void *info) |
| 579 | { |
| 580 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
| 581 | |
| 582 | if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) |
| 583 | return; |
| 584 | |
| 585 | clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); |
| 586 | } |
| 587 | |
| 588 | void lapic_update_tsc_freq(void) |
| 589 | { |
| 590 | /* |
| 591 | * The clockevent device's ->mult and ->shift can both be |
| 592 | * changed. In order to avoid races, schedule the frequency |
| 593 | * update code on each CPU. |
| 594 | */ |
| 595 | on_each_cpu(__lapic_update_tsc_freq, NULL, 0); |
| 596 | } |
| 597 | |
| 598 | /* |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 599 | * In this functions we calibrate APIC bus clocks to the external timer. |
| 600 | * |
| 601 | * We want to do the calibration only once since we want to have local timer |
| 602 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus |
| 603 | * frequency. |
| 604 | * |
| 605 | * This was previously done by reading the PIT/HPET and waiting for a wrap |
| 606 | * around to find out, that a tick has elapsed. I have a box, where the PIT |
| 607 | * readout is broken, so it never gets out of the wait loop again. This was |
| 608 | * also reported by others. |
| 609 | * |
| 610 | * Monitoring the jiffies value is inaccurate and the clockevents |
| 611 | * infrastructure allows us to do a simple substitution of the interrupt |
| 612 | * handler. |
| 613 | * |
| 614 | * The calibration routine also uses the pm_timer when possible, as the PIT |
| 615 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes |
| 616 | * back to normal later in the boot process). |
| 617 | */ |
| 618 | |
| 619 | #define LAPIC_CAL_LOOPS (HZ/10) |
| 620 | |
| 621 | static __initdata int lapic_cal_loops = -1; |
| 622 | static __initdata long lapic_cal_t1, lapic_cal_t2; |
| 623 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; |
| 624 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; |
| 625 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; |
| 626 | |
| 627 | /* |
| 628 | * Temporary interrupt handler. |
| 629 | */ |
| 630 | static void __init lapic_cal_handler(struct clock_event_device *dev) |
| 631 | { |
| 632 | unsigned long long tsc = 0; |
| 633 | long tapic = apic_read(APIC_TMCCT); |
| 634 | unsigned long pm = acpi_pm_read_early(); |
| 635 | |
Borislav Petkov | 59e21e3 | 2016-04-04 22:24:59 +0200 | [diff] [blame] | 636 | if (boot_cpu_has(X86_FEATURE_TSC)) |
Andy Lutomirski | 4ea1636 | 2015-06-25 18:44:07 +0200 | [diff] [blame] | 637 | tsc = rdtsc(); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 638 | |
| 639 | switch (lapic_cal_loops++) { |
| 640 | case 0: |
| 641 | lapic_cal_t1 = tapic; |
| 642 | lapic_cal_tsc1 = tsc; |
| 643 | lapic_cal_pm1 = pm; |
| 644 | lapic_cal_j1 = jiffies; |
| 645 | break; |
| 646 | |
| 647 | case LAPIC_CAL_LOOPS: |
| 648 | lapic_cal_t2 = tapic; |
| 649 | lapic_cal_tsc2 = tsc; |
| 650 | if (pm < lapic_cal_pm1) |
| 651 | pm += ACPI_PM_OVRRUN; |
| 652 | lapic_cal_pm2 = pm; |
| 653 | lapic_cal_j2 = jiffies; |
| 654 | break; |
| 655 | } |
| 656 | } |
| 657 | |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 658 | static int __init |
| 659 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 660 | { |
| 661 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; |
| 662 | const long pm_thresh = pm_100ms / 100; |
| 663 | unsigned long mult; |
| 664 | u64 res; |
| 665 | |
| 666 | #ifndef CONFIG_X86_PM_TIMER |
| 667 | return -1; |
| 668 | #endif |
| 669 | |
Yasuaki Ishimatsu | 39ba5d4 | 2009-01-28 12:52:24 +0900 | [diff] [blame] | 670 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 671 | |
| 672 | /* Check, if the PM timer is available */ |
| 673 | if (!deltapm) |
| 674 | return -1; |
| 675 | |
| 676 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); |
| 677 | |
| 678 | if (deltapm > (pm_100ms - pm_thresh) && |
| 679 | deltapm < (pm_100ms + pm_thresh)) { |
Yasuaki Ishimatsu | 39ba5d4 | 2009-01-28 12:52:24 +0900 | [diff] [blame] | 680 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 681 | return 0; |
| 682 | } |
| 683 | |
| 684 | res = (((u64)deltapm) * mult) >> 22; |
| 685 | do_div(res, 1000000); |
| 686 | pr_warning("APIC calibration not consistent " |
Yasuaki Ishimatsu | 39ba5d4 | 2009-01-28 12:52:24 +0900 | [diff] [blame] | 687 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 688 | |
| 689 | /* Correct the lapic counter value */ |
| 690 | res = (((u64)(*delta)) * pm_100ms); |
| 691 | do_div(res, deltapm); |
| 692 | pr_info("APIC delta adjusted to PM-Timer: " |
| 693 | "%lu (%ld)\n", (unsigned long)res, *delta); |
| 694 | *delta = (long)res; |
| 695 | |
| 696 | /* Correct the tsc counter value */ |
Borislav Petkov | 59e21e3 | 2016-04-04 22:24:59 +0200 | [diff] [blame] | 697 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 698 | res = (((u64)(*deltatsc)) * pm_100ms); |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 699 | do_div(res, deltapm); |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 700 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
Frans Pop | 3235dc3 | 2010-02-06 18:47:17 +0100 | [diff] [blame] | 701 | "PM-Timer: %lu (%ld)\n", |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 702 | (unsigned long)res, *deltatsc); |
| 703 | *deltatsc = (long)res; |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 704 | } |
| 705 | |
| 706 | return 0; |
| 707 | } |
| 708 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 709 | static int __init calibrate_APIC_clock(void) |
| 710 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 711 | struct clock_event_device *levt = this_cpu_ptr(&lapic_events); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 712 | void (*real_handler)(struct clock_event_device *dev); |
| 713 | unsigned long deltaj; |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 714 | long delta, deltatsc; |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 715 | int pm_referenced = 0; |
| 716 | |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 717 | /** |
| 718 | * check if lapic timer has already been calibrated by platform |
| 719 | * specific routine, such as tsc calibration code. if so, we just fill |
| 720 | * in the clockevent structure and return. |
| 721 | */ |
| 722 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 723 | if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { |
| 724 | return 0; |
| 725 | } else if (lapic_timer_frequency) { |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 726 | apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", |
| 727 | lapic_timer_frequency); |
| 728 | lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, |
| 729 | TICK_NSEC, lapic_clockevent.shift); |
| 730 | lapic_clockevent.max_delta_ns = |
| 731 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); |
| 732 | lapic_clockevent.min_delta_ns = |
| 733 | clockevent_delta2ns(0xF, &lapic_clockevent); |
| 734 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
| 735 | return 0; |
| 736 | } |
| 737 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 738 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
| 739 | "calibrating APIC timer ...\n"); |
| 740 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 741 | local_irq_disable(); |
| 742 | |
| 743 | /* Replace the global interrupt handler */ |
| 744 | real_handler = global_clock_event->event_handler; |
| 745 | global_clock_event->event_handler = lapic_cal_handler; |
| 746 | |
| 747 | /* |
Cyrill Gorcunov | 81608f3 | 2008-10-10 19:00:17 +0400 | [diff] [blame] | 748 | * Setup the APIC counter to maximum. There is no way the lapic |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 749 | * can underflow in the 100ms detection time frame |
| 750 | */ |
Cyrill Gorcunov | 81608f3 | 2008-10-10 19:00:17 +0400 | [diff] [blame] | 751 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 752 | |
| 753 | /* Let the interrupts run */ |
| 754 | local_irq_enable(); |
| 755 | |
| 756 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
| 757 | cpu_relax(); |
| 758 | |
| 759 | local_irq_disable(); |
| 760 | |
| 761 | /* Restore the real event handler */ |
| 762 | global_clock_event->event_handler = real_handler; |
| 763 | |
| 764 | /* Build delta t1-t2 as apic timer counts down */ |
| 765 | delta = lapic_cal_t1 - lapic_cal_t2; |
| 766 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); |
| 767 | |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 768 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
| 769 | |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 770 | /* we trust the PM based calibration if possible */ |
| 771 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 772 | &delta, &deltatsc); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 773 | |
| 774 | /* Calculate the scaled math multiplication factor */ |
| 775 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, |
| 776 | lapic_clockevent.shift); |
| 777 | lapic_clockevent.max_delta_ns = |
Pierre Tardy | 4aed89d | 2011-01-06 16:23:29 +0100 | [diff] [blame] | 778 | clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 779 | lapic_clockevent.min_delta_ns = |
| 780 | clockevent_delta2ns(0xF, &lapic_clockevent); |
| 781 | |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 782 | lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 783 | |
| 784 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); |
Thomas Gleixner | 411462f | 2009-11-16 11:52:39 +0100 | [diff] [blame] | 785 | apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 786 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 787 | lapic_timer_frequency); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 788 | |
Borislav Petkov | 59e21e3 | 2016-04-04 22:24:59 +0200 | [diff] [blame] | 789 | if (boot_cpu_has(X86_FEATURE_TSC)) { |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 790 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
| 791 | "%ld.%04ld MHz.\n", |
Yasuaki Ishimatsu | 754ef0c | 2009-01-28 12:51:09 +0900 | [diff] [blame] | 792 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
| 793 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 794 | } |
| 795 | |
| 796 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " |
| 797 | "%u.%04u MHz.\n", |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 798 | lapic_timer_frequency / (1000000 / HZ), |
| 799 | lapic_timer_frequency % (1000000 / HZ)); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 800 | |
| 801 | /* |
| 802 | * Do a sanity check on the APIC calibration result |
| 803 | */ |
Jacob Pan | 1ade93e | 2011-11-10 13:42:40 +0000 | [diff] [blame] | 804 | if (lapic_timer_frequency < (1000000 / HZ)) { |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 805 | local_irq_enable(); |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 806 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 807 | return -1; |
| 808 | } |
| 809 | |
| 810 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; |
| 811 | |
Cyrill Gorcunov | b189892 | 2008-09-12 23:58:24 +0400 | [diff] [blame] | 812 | /* |
| 813 | * PM timer calibration failed or not turned on |
| 814 | * so lets try APIC timer based calibration |
| 815 | */ |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 816 | if (!pm_referenced) { |
| 817 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); |
| 818 | |
| 819 | /* |
| 820 | * Setup the apic timer manually |
| 821 | */ |
| 822 | levt->event_handler = lapic_cal_handler; |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 823 | lapic_timer_set_periodic(levt); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 824 | lapic_cal_loops = -1; |
| 825 | |
| 826 | /* Let the interrupts run */ |
| 827 | local_irq_enable(); |
| 828 | |
| 829 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) |
| 830 | cpu_relax(); |
| 831 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 832 | /* Stop the lapic timer */ |
Thomas Gleixner | c948c26 | 2015-07-30 00:30:51 +0200 | [diff] [blame] | 833 | local_irq_disable(); |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 834 | lapic_timer_shutdown(levt); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 835 | |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 836 | /* Jiffies delta */ |
| 837 | deltaj = lapic_cal_j2 - lapic_cal_j1; |
| 838 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); |
| 839 | |
| 840 | /* Check, if the jiffies result is consistent */ |
| 841 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) |
| 842 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); |
| 843 | else |
| 844 | levt->features |= CLOCK_EVT_FEAT_DUMMY; |
Thomas Gleixner | c948c26 | 2015-07-30 00:30:51 +0200 | [diff] [blame] | 845 | } |
| 846 | local_irq_enable(); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 847 | |
| 848 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { |
Jaswinder Singh Rajput | e423e33 | 2009-01-04 16:16:25 +0530 | [diff] [blame] | 849 | pr_warning("APIC timer disabled due to verification failure\n"); |
Yinghai Lu | 2f04fa8 | 2008-08-24 02:01:54 -0700 | [diff] [blame] | 850 | return -1; |
| 851 | } |
| 852 | |
| 853 | return 0; |
| 854 | } |
| 855 | |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 856 | /* |
| 857 | * Setup the boot APIC |
| 858 | * |
| 859 | * Calibrate and verify the result. |
| 860 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 861 | void __init setup_boot_APIC_clock(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 862 | { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 863 | /* |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 864 | * The local apic timer can be disabled via the kernel |
| 865 | * commandline or from the CPU detection code. Register the lapic |
| 866 | * timer as a dummy clock event source on SMP systems, so the |
| 867 | * broadcast mechanism is used. On UP systems simply ignore it. |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 868 | */ |
| 869 | if (disable_apic_timer) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 870 | pr_info("Disabling APIC timer\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 871 | /* No broadcast on UP ! */ |
Thomas Gleixner | 9d09951 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 872 | if (num_possible_cpus() > 1) { |
| 873 | lapic_clockevent.mult = 1; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 874 | setup_APIC_timer(); |
Thomas Gleixner | 9d09951 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 875 | } |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 876 | return; |
| 877 | } |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 878 | |
Cyrill Gorcunov | 89b3b1f4 | 2008-07-15 21:02:54 +0400 | [diff] [blame] | 879 | if (calibrate_APIC_clock()) { |
Thomas Gleixner | c2b84b3 | 2008-01-30 13:33:04 +0100 | [diff] [blame] | 880 | /* No broadcast on UP ! */ |
| 881 | if (num_possible_cpus() > 1) |
| 882 | setup_APIC_timer(); |
| 883 | return; |
| 884 | } |
| 885 | |
| 886 | /* |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 887 | * If nmi_watchdog is set to IO_APIC, we need the |
| 888 | * PIT/HPET going. Otherwise register lapic as a dummy |
| 889 | * device. |
| 890 | */ |
Don Zickus | 072b198 | 2010-11-12 11:22:24 -0500 | [diff] [blame] | 891 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 892 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 893 | /* Setup the lapic or request the broadcast */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 894 | setup_APIC_timer(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 895 | } |
| 896 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 897 | void setup_secondary_APIC_clock(void) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 898 | { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 899 | setup_APIC_timer(); |
| 900 | } |
| 901 | |
| 902 | /* |
| 903 | * The guts of the apic timer interrupt |
| 904 | */ |
| 905 | static void local_apic_timer_interrupt(void) |
| 906 | { |
| 907 | int cpu = smp_processor_id(); |
| 908 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); |
| 909 | |
| 910 | /* |
| 911 | * Normally we should not be here till LAPIC has been initialized but |
| 912 | * in some cases like kdump, its possible that there is a pending LAPIC |
| 913 | * timer interrupt from previous kernel's context and is delivered in |
| 914 | * new kernel the moment interrupts are enabled. |
| 915 | * |
| 916 | * Interrupts are enabled early and LAPIC is setup much later, hence |
| 917 | * its possible that when we get here evt->event_handler is NULL. |
| 918 | * Check for event_handler being NULL and discard the interrupt as |
| 919 | * spurious. |
| 920 | */ |
| 921 | if (!evt->event_handler) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 922 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 923 | /* Switch it off */ |
Viresh Kumar | b23d8e5 | 2015-07-16 16:28:44 +0530 | [diff] [blame] | 924 | lapic_timer_shutdown(evt); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 925 | return; |
| 926 | } |
| 927 | |
| 928 | /* |
| 929 | * the NMI deadlock-detector uses this. |
| 930 | */ |
Hiroshi Shimamoto | 915b0d0 | 2008-12-08 19:19:26 -0800 | [diff] [blame] | 931 | inc_irq_stat(apic_timer_irqs); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 932 | |
| 933 | evt->event_handler(evt); |
| 934 | } |
| 935 | |
| 936 | /* |
| 937 | * Local APIC timer interrupt. This is the most natural way for doing |
| 938 | * local interrupts, but local timer interrupts can be emulated by |
| 939 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] |
| 940 | * |
| 941 | * [ if a single-CPU system runs an SMP kernel then we call the local |
| 942 | * interrupt as well. Thus we cannot inline the local irq ... ] |
| 943 | */ |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 944 | __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 945 | { |
| 946 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 947 | |
| 948 | /* |
| 949 | * NOTE! We'd better ACK the irq immediately, |
| 950 | * because timer handling can be slow. |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 951 | * |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 952 | * update_process_times() expects us to have done irq_enter(). |
| 953 | * Besides, if we don't timer interrupts ignore the global |
| 954 | * interrupt lock, which is the WrongThing (tm) to do. |
| 955 | */ |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 956 | entering_ack_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 957 | local_apic_timer_interrupt(); |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 958 | exiting_irq(); |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 959 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 960 | set_irq_regs(old_regs); |
| 961 | } |
| 962 | |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 963 | __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) |
Seiji Aguchi | cf910e8 | 2013-06-20 11:46:53 -0400 | [diff] [blame] | 964 | { |
| 965 | struct pt_regs *old_regs = set_irq_regs(regs); |
| 966 | |
| 967 | /* |
| 968 | * NOTE! We'd better ACK the irq immediately, |
| 969 | * because timer handling can be slow. |
| 970 | * |
| 971 | * update_process_times() expects us to have done irq_enter(). |
| 972 | * Besides, if we don't timer interrupts ignore the global |
| 973 | * interrupt lock, which is the WrongThing (tm) to do. |
| 974 | */ |
| 975 | entering_ack_irq(); |
| 976 | trace_local_timer_entry(LOCAL_TIMER_VECTOR); |
| 977 | local_apic_timer_interrupt(); |
| 978 | trace_local_timer_exit(LOCAL_TIMER_VECTOR); |
| 979 | exiting_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 980 | |
| 981 | set_irq_regs(old_regs); |
| 982 | } |
| 983 | |
| 984 | int setup_profiling_timer(unsigned int multiplier) |
| 985 | { |
| 986 | return -EINVAL; |
| 987 | } |
| 988 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 989 | /* |
| 990 | * Local APIC start and shutdown |
| 991 | */ |
| 992 | |
| 993 | /** |
| 994 | * clear_local_APIC - shutdown the local APIC |
| 995 | * |
| 996 | * This is called, when a CPU is disabled and before rebooting, so the state of |
| 997 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS |
| 998 | * leftovers during boot. |
| 999 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1000 | void clear_local_APIC(void) |
| 1001 | { |
Chuck Ebbert | 2584a82 | 2008-05-20 18:18:12 -0400 | [diff] [blame] | 1002 | int maxlvt; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1003 | u32 v; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1004 | |
Andi Kleen | d343289 | 2008-01-30 13:33:17 +0100 | [diff] [blame] | 1005 | /* APIC hasn't been mapped yet */ |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 1006 | if (!x2apic_mode && !apic_phys) |
Andi Kleen | d343289 | 2008-01-30 13:33:17 +0100 | [diff] [blame] | 1007 | return; |
| 1008 | |
| 1009 | maxlvt = lapic_get_maxlvt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1010 | /* |
Siddha, Suresh B | 704fc59 | 2006-06-26 13:59:53 +0200 | [diff] [blame] | 1011 | * Masking an LVT entry can trigger a local APIC error |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1012 | * if the vector is zero. Mask LVTERR first to prevent this. |
| 1013 | */ |
| 1014 | if (maxlvt >= 3) { |
| 1015 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1016 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1017 | } |
| 1018 | /* |
| 1019 | * Careful: we have to set masks only first to deassert |
| 1020 | * any level-triggered sources. |
| 1021 | */ |
| 1022 | v = apic_read(APIC_LVTT); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1023 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1024 | v = apic_read(APIC_LVT0); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1025 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1026 | v = apic_read(APIC_LVT1); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1027 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1028 | if (maxlvt >= 4) { |
| 1029 | v = apic_read(APIC_LVTPC); |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1030 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1031 | } |
| 1032 | |
Cyrill Gorcunov | 6764014 | 2008-08-16 23:21:50 +0400 | [diff] [blame] | 1033 | /* lets not touch this if we didn't frob it */ |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 1034 | #ifdef CONFIG_X86_THERMAL_VECTOR |
Cyrill Gorcunov | 6764014 | 2008-08-16 23:21:50 +0400 | [diff] [blame] | 1035 | if (maxlvt >= 5) { |
| 1036 | v = apic_read(APIC_LVTTHMR); |
| 1037 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
| 1038 | } |
| 1039 | #endif |
Andi Kleen | 5ca8681 | 2009-02-12 13:49:37 +0100 | [diff] [blame] | 1040 | #ifdef CONFIG_X86_MCE_INTEL |
| 1041 | if (maxlvt >= 6) { |
| 1042 | v = apic_read(APIC_LVTCMCI); |
| 1043 | if (!(v & APIC_LVT_MASKED)) |
| 1044 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); |
| 1045 | } |
| 1046 | #endif |
| 1047 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1048 | /* |
| 1049 | * Clean APIC state for other OSs: |
| 1050 | */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1051 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
| 1052 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
| 1053 | apic_write(APIC_LVT1, APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1054 | if (maxlvt >= 3) |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1055 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1056 | if (maxlvt >= 4) |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1057 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
Cyrill Gorcunov | 6764014 | 2008-08-16 23:21:50 +0400 | [diff] [blame] | 1058 | |
| 1059 | /* Integrated APIC (!82489DX) ? */ |
| 1060 | if (lapic_is_integrated()) { |
| 1061 | if (maxlvt > 3) |
| 1062 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
| 1063 | apic_write(APIC_ESR, 0); |
| 1064 | apic_read(APIC_ESR); |
| 1065 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1066 | } |
| 1067 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1068 | /** |
| 1069 | * disable_local_APIC - clear and disable the local APIC |
| 1070 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1071 | void disable_local_APIC(void) |
| 1072 | { |
| 1073 | unsigned int value; |
| 1074 | |
Jan Beulich | 4a13ad0 | 2009-01-14 12:28:51 +0000 | [diff] [blame] | 1075 | /* APIC hasn't been mapped yet */ |
Yinghai Lu | fd19dce | 2010-07-15 00:00:59 -0700 | [diff] [blame] | 1076 | if (!x2apic_mode && !apic_phys) |
Jan Beulich | 4a13ad0 | 2009-01-14 12:28:51 +0000 | [diff] [blame] | 1077 | return; |
| 1078 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1079 | clear_local_APIC(); |
| 1080 | |
| 1081 | /* |
| 1082 | * Disable APIC (implies clearing of registers |
| 1083 | * for 82489DX!). |
| 1084 | */ |
| 1085 | value = apic_read(APIC_SPIV); |
| 1086 | value &= ~APIC_SPIV_APIC_ENABLED; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1087 | apic_write(APIC_SPIV, value); |
Cyrill Gorcunov | 990b183 | 2008-08-18 20:45:51 +0400 | [diff] [blame] | 1088 | |
| 1089 | #ifdef CONFIG_X86_32 |
| 1090 | /* |
| 1091 | * When LAPIC was disabled by the BIOS and enabled by the kernel, |
| 1092 | * restore the disabled state. |
| 1093 | */ |
| 1094 | if (enabled_via_apicbase) { |
| 1095 | unsigned int l, h; |
| 1096 | |
| 1097 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 1098 | l &= ~MSR_IA32_APICBASE_ENABLE; |
| 1099 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 1100 | } |
| 1101 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1102 | } |
| 1103 | |
Cyrill Gorcunov | fe4024d | 2008-08-18 20:45:52 +0400 | [diff] [blame] | 1104 | /* |
| 1105 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
| 1106 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and |
| 1107 | * not power-off. Additionally clear all LVT entries before disable_local_APIC |
| 1108 | * for the case where Linux didn't enable the LAPIC. |
| 1109 | */ |
Hiroshi Shimamoto | 9b7711f | 2007-10-19 18:21:11 -0700 | [diff] [blame] | 1110 | void lapic_shutdown(void) |
| 1111 | { |
| 1112 | unsigned long flags; |
| 1113 | |
Borislav Petkov | 93984fb | 2016-04-04 22:25:00 +0200 | [diff] [blame] | 1114 | if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) |
Hiroshi Shimamoto | 9b7711f | 2007-10-19 18:21:11 -0700 | [diff] [blame] | 1115 | return; |
| 1116 | |
| 1117 | local_irq_save(flags); |
| 1118 | |
Cyrill Gorcunov | fe4024d | 2008-08-18 20:45:52 +0400 | [diff] [blame] | 1119 | #ifdef CONFIG_X86_32 |
| 1120 | if (!enabled_via_apicbase) |
| 1121 | clear_local_APIC(); |
| 1122 | else |
| 1123 | #endif |
| 1124 | disable_local_APIC(); |
| 1125 | |
Hiroshi Shimamoto | 9b7711f | 2007-10-19 18:21:11 -0700 | [diff] [blame] | 1126 | |
| 1127 | local_irq_restore(flags); |
| 1128 | } |
| 1129 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1130 | /** |
| 1131 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs |
| 1132 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1133 | void __init sync_Arb_IDs(void) |
| 1134 | { |
Cyrill Gorcunov | 296cb95 | 2008-08-15 13:51:23 +0200 | [diff] [blame] | 1135 | /* |
| 1136 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not |
| 1137 | * needed on AMD. |
| 1138 | */ |
| 1139 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1140 | return; |
| 1141 | |
| 1142 | /* |
| 1143 | * Wait for idle. |
| 1144 | */ |
| 1145 | apic_wait_icr_idle(); |
| 1146 | |
| 1147 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
Cyrill Gorcunov | 6f6da97 | 2008-08-15 23:05:19 +0400 | [diff] [blame] | 1148 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
| 1149 | APIC_INT_LEVELTRIG | APIC_DM_INIT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1150 | } |
| 1151 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1152 | /* |
| 1153 | * An initial setup of the virtual wire mode. |
| 1154 | */ |
| 1155 | void __init init_bsp_APIC(void) |
| 1156 | { |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1157 | unsigned int value; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1158 | |
| 1159 | /* |
| 1160 | * Don't do the setup now if we have a SMP BIOS as the |
| 1161 | * through-I/O-APIC virtual wire mode might be active. |
| 1162 | */ |
Borislav Petkov | 93984fb | 2016-04-04 22:25:00 +0200 | [diff] [blame] | 1163 | if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1164 | return; |
| 1165 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1166 | /* |
| 1167 | * Do not trust the local APIC being empty at bootup. |
| 1168 | */ |
| 1169 | clear_local_APIC(); |
| 1170 | |
| 1171 | /* |
| 1172 | * Enable APIC. |
| 1173 | */ |
| 1174 | value = apic_read(APIC_SPIV); |
| 1175 | value &= ~APIC_VECTOR_MASK; |
| 1176 | value |= APIC_SPIV_APIC_ENABLED; |
Cyrill Gorcunov | 638c041 | 2008-08-15 23:05:18 +0400 | [diff] [blame] | 1177 | |
| 1178 | #ifdef CONFIG_X86_32 |
| 1179 | /* This bit is reserved on P4/Xeon and should be cleared */ |
| 1180 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && |
| 1181 | (boot_cpu_data.x86 == 15)) |
| 1182 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
| 1183 | else |
| 1184 | #endif |
| 1185 | value |= APIC_SPIV_FOCUS_DISABLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1186 | value |= SPURIOUS_APIC_VECTOR; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1187 | apic_write(APIC_SPIV, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1188 | |
| 1189 | /* |
| 1190 | * Set up the virtual wire mode. |
| 1191 | */ |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1192 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1193 | value = APIC_DM_NMI; |
Cyrill Gorcunov | 638c041 | 2008-08-15 23:05:18 +0400 | [diff] [blame] | 1194 | if (!lapic_is_integrated()) /* 82489DX */ |
| 1195 | value |= APIC_LVT_LEVEL_TRIGGER; |
Hidehiro Kawai | b7c4948 | 2015-12-14 11:19:12 +0100 | [diff] [blame] | 1196 | if (apic_extnmi == APIC_EXTNMI_NONE) |
| 1197 | value |= APIC_LVT_MASKED; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1198 | apic_write(APIC_LVT1, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1199 | } |
| 1200 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 1201 | static void lapic_setup_esr(void) |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1202 | { |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1203 | unsigned int oldvalue, value, maxlvt; |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1204 | |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1205 | if (!lapic_is_integrated()) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1206 | pr_info("No ESR for 82489DX.\n"); |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1207 | return; |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1208 | } |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1209 | |
Ingo Molnar | 08125d3 | 2009-01-28 05:08:44 +0100 | [diff] [blame] | 1210 | if (apic->disable_esr) { |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1211 | /* |
| 1212 | * Something untraceable is creating bad interrupts on |
| 1213 | * secondary quads ... for the moment, just leave the |
| 1214 | * ESR disabled - we can't do anything useful with the |
| 1215 | * errors anyway - mbligh |
| 1216 | */ |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1217 | pr_info("Leaving ESR disabled.\n"); |
Cyrill Gorcunov | 9df08f1 | 2008-09-14 11:55:37 +0400 | [diff] [blame] | 1218 | return; |
| 1219 | } |
| 1220 | |
| 1221 | maxlvt = lapic_get_maxlvt(); |
| 1222 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
| 1223 | apic_write(APIC_ESR, 0); |
| 1224 | oldvalue = apic_read(APIC_ESR); |
| 1225 | |
| 1226 | /* enables sending errors */ |
| 1227 | value = ERROR_APIC_VECTOR; |
| 1228 | apic_write(APIC_LVTERR, value); |
| 1229 | |
| 1230 | /* |
| 1231 | * spec says clear errors after enabling vector. |
| 1232 | */ |
| 1233 | if (maxlvt > 3) |
| 1234 | apic_write(APIC_ESR, 0); |
| 1235 | value = apic_read(APIC_ESR); |
| 1236 | if (value != oldvalue) |
| 1237 | apic_printk(APIC_VERBOSE, "ESR value before enabling " |
| 1238 | "vector: 0x%08x after: 0x%08x\n", |
| 1239 | oldvalue, value); |
Cyrill Gorcunov | c43da2f | 2008-08-18 20:45:54 +0400 | [diff] [blame] | 1240 | } |
| 1241 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1242 | /** |
| 1243 | * setup_local_APIC - setup the local APIC |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1244 | * |
| 1245 | * Used to setup local APIC while initializing BSP or bringin up APs. |
| 1246 | * Always called with preemption disabled. |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1247 | */ |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 1248 | void setup_local_APIC(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1249 | { |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1250 | int cpu = smp_processor_id(); |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1251 | unsigned int value, queued; |
| 1252 | int i, j, acked = 0; |
| 1253 | unsigned long long tsc = 0, ntsc; |
Andy Lutomirski | b47dcbd | 2014-10-15 10:12:07 -0700 | [diff] [blame] | 1254 | long long max_loops = cpu_khz ? cpu_khz : 1000000; |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1255 | |
Borislav Petkov | 59e21e3 | 2016-04-04 22:24:59 +0200 | [diff] [blame] | 1256 | if (boot_cpu_has(X86_FEATURE_TSC)) |
Andy Lutomirski | 4ea1636 | 2015-06-25 18:44:07 +0200 | [diff] [blame] | 1257 | tsc = rdtsc(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1258 | |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 1259 | if (disable_apic) { |
Henrik Kretzschmar | 7167d08 | 2011-02-22 15:38:05 +0100 | [diff] [blame] | 1260 | disable_ioapic_support(); |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 1261 | return; |
| 1262 | } |
| 1263 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1264 | #ifdef CONFIG_X86_32 |
| 1265 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
Ingo Molnar | 08125d3 | 2009-01-28 05:08:44 +0100 | [diff] [blame] | 1266 | if (lapic_is_integrated() && apic->disable_esr) { |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1267 | apic_write(APIC_ESR, 0); |
| 1268 | apic_write(APIC_ESR, 0); |
| 1269 | apic_write(APIC_ESR, 0); |
| 1270 | apic_write(APIC_ESR, 0); |
| 1271 | } |
| 1272 | #endif |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1273 | perf_events_lapic_init(); |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1274 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1275 | /* |
| 1276 | * Double-check whether this APIC is really registered. |
| 1277 | * This is meaningless in clustered apic mode, so we skip it. |
| 1278 | */ |
Daniel Walker | c2777f9 | 2009-09-12 10:40:20 -0700 | [diff] [blame] | 1279 | BUG_ON(!apic->apic_id_registered()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1280 | |
| 1281 | /* |
| 1282 | * Intel recommends to set DFR, LDR and TPR before enabling |
| 1283 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel |
| 1284 | * document number 292116). So here it goes... |
| 1285 | */ |
Ingo Molnar | a5c4329 | 2009-01-28 06:50:47 +0100 | [diff] [blame] | 1286 | apic->init_apic_ldr(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1287 | |
Tejun Heo | 6f802c4 | 2011-01-23 14:37:31 +0100 | [diff] [blame] | 1288 | #ifdef CONFIG_X86_32 |
| 1289 | /* |
Tejun Heo | acb8bc0 | 2011-01-23 14:37:33 +0100 | [diff] [blame] | 1290 | * APIC LDR is initialized. If logical_apicid mapping was |
| 1291 | * initialized during get_smp_config(), make sure it matches the |
| 1292 | * actual value. |
Tejun Heo | 6f802c4 | 2011-01-23 14:37:31 +0100 | [diff] [blame] | 1293 | */ |
Tejun Heo | acb8bc0 | 2011-01-23 14:37:33 +0100 | [diff] [blame] | 1294 | i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
| 1295 | WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); |
| 1296 | /* always use the value from LDR */ |
Tejun Heo | 6f802c4 | 2011-01-23 14:37:31 +0100 | [diff] [blame] | 1297 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
| 1298 | logical_smp_processor_id(); |
| 1299 | #endif |
| 1300 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1301 | /* |
| 1302 | * Set Task Priority to 'accept all'. We never change this |
| 1303 | * later on. |
| 1304 | */ |
| 1305 | value = apic_read(APIC_TASKPRI); |
| 1306 | value &= ~APIC_TPRI_MASK; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1307 | apic_write(APIC_TASKPRI, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1308 | |
| 1309 | /* |
Vivek Goyal | da7ed9f | 2006-03-25 16:31:16 +0100 | [diff] [blame] | 1310 | * After a crash, we no longer service the interrupts and a pending |
| 1311 | * interrupt from previous kernel might still have ISR bit set. |
| 1312 | * |
| 1313 | * Most probably by now CPU has serviced that pending interrupt and |
| 1314 | * it might not have done the ack_APIC_irq() because it thought, |
| 1315 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it |
| 1316 | * does not clear the ISR bit and cpu thinks it has already serivced |
| 1317 | * the interrupt. Hence a vector might get locked. It was noticed |
| 1318 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. |
| 1319 | */ |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1320 | do { |
| 1321 | queued = 0; |
| 1322 | for (i = APIC_ISR_NR - 1; i >= 0; i--) |
| 1323 | queued |= apic_read(APIC_IRR + i*0x10); |
| 1324 | |
| 1325 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { |
| 1326 | value = apic_read(APIC_ISR + i*0x10); |
| 1327 | for (j = 31; j >= 0; j--) { |
| 1328 | if (value & (1<<j)) { |
| 1329 | ack_APIC_irq(); |
| 1330 | acked++; |
| 1331 | } |
| 1332 | } |
Vivek Goyal | da7ed9f | 2006-03-25 16:31:16 +0100 | [diff] [blame] | 1333 | } |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1334 | if (acked > 256) { |
| 1335 | printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", |
| 1336 | acked); |
| 1337 | break; |
| 1338 | } |
Shai Fultheim | 42fa425 | 2012-04-20 01:12:32 +0300 | [diff] [blame] | 1339 | if (queued) { |
Borislav Petkov | 59e21e3 | 2016-04-04 22:24:59 +0200 | [diff] [blame] | 1340 | if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { |
Andy Lutomirski | 4ea1636 | 2015-06-25 18:44:07 +0200 | [diff] [blame] | 1341 | ntsc = rdtsc(); |
Shai Fultheim | 42fa425 | 2012-04-20 01:12:32 +0300 | [diff] [blame] | 1342 | max_loops = (cpu_khz << 10) - (ntsc - tsc); |
| 1343 | } else |
| 1344 | max_loops--; |
| 1345 | } |
Kerstin Jonsson | 8c3ba8d | 2010-05-24 12:13:15 -0700 | [diff] [blame] | 1346 | } while (queued && max_loops > 0); |
| 1347 | WARN_ON(max_loops <= 0); |
Vivek Goyal | da7ed9f | 2006-03-25 16:31:16 +0100 | [diff] [blame] | 1348 | |
| 1349 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1350 | * Now that we are all set up, enable the APIC |
| 1351 | */ |
| 1352 | value = apic_read(APIC_SPIV); |
| 1353 | value &= ~APIC_VECTOR_MASK; |
| 1354 | /* |
| 1355 | * Enable APIC |
| 1356 | */ |
| 1357 | value |= APIC_SPIV_APIC_ENABLED; |
| 1358 | |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1359 | #ifdef CONFIG_X86_32 |
| 1360 | /* |
| 1361 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with |
| 1362 | * certain networking cards. If high frequency interrupts are |
| 1363 | * happening on a particular IOAPIC pin, plus the IOAPIC routing |
| 1364 | * entry is masked/unmasked at a high rate as well then sooner or |
| 1365 | * later IOAPIC line gets 'stuck', no more interrupts are received |
| 1366 | * from the device. If focus CPU is disabled then the hang goes |
| 1367 | * away, oh well :-( |
| 1368 | * |
| 1369 | * [ This bug can be reproduced easily with a level-triggered |
| 1370 | * PCI Ne2000 networking cards and PII/PIII processors, dual |
| 1371 | * BX chipset. ] |
| 1372 | */ |
| 1373 | /* |
| 1374 | * Actually disabling the focus CPU check just makes the hang less |
| 1375 | * frequent as it makes the interrupt distributon model be more |
| 1376 | * like LRU than MRU (the short-term load is more even across CPUs). |
| 1377 | * See also the comment in end_level_ioapic_irq(). --macro |
| 1378 | */ |
| 1379 | |
| 1380 | /* |
| 1381 | * - enable focus processor (bit==0) |
| 1382 | * - 64bit mode always use processor focus |
| 1383 | * so no need to set it |
| 1384 | */ |
| 1385 | value &= ~APIC_SPIV_FOCUS_DISABLED; |
| 1386 | #endif |
Andi Kleen | 3f14c74 | 2006-09-26 10:52:29 +0200 | [diff] [blame] | 1387 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1388 | /* |
| 1389 | * Set spurious IRQ vector |
| 1390 | */ |
| 1391 | value |= SPURIOUS_APIC_VECTOR; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1392 | apic_write(APIC_SPIV, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1393 | |
| 1394 | /* |
| 1395 | * Set up LVT0, LVT1: |
| 1396 | * |
| 1397 | * set up through-local-APIC on the BP's LINT0. This is not |
| 1398 | * strictly necessary in pure symmetric-IO mode, but sometimes |
| 1399 | * we delegate interrupts to the 8259A. |
| 1400 | */ |
| 1401 | /* |
| 1402 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro |
| 1403 | */ |
| 1404 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1405 | if (!cpu && (pic_mode || !value)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1406 | value = APIC_DM_EXTINT; |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1407 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1408 | } else { |
| 1409 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1410 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1411 | } |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1412 | apic_write(APIC_LVT0, value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1413 | |
| 1414 | /* |
Hidehiro Kawai | b7c4948 | 2015-12-14 11:19:12 +0100 | [diff] [blame] | 1415 | * Only the BSP sees the LINT1 NMI signal by default. This can be |
| 1416 | * modified by apic_extnmi= boot option. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1417 | */ |
Hidehiro Kawai | b7c4948 | 2015-12-14 11:19:12 +0100 | [diff] [blame] | 1418 | if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || |
| 1419 | apic_extnmi == APIC_EXTNMI_ALL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1420 | value = APIC_DM_NMI; |
| 1421 | else |
| 1422 | value = APIC_DM_NMI | APIC_LVT_MASKED; |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1423 | if (!lapic_is_integrated()) /* 82489DX */ |
| 1424 | value |= APIC_LVT_LEVEL_TRIGGER; |
Andi Kleen | 11a8e77 | 2006-01-11 22:46:51 +0100 | [diff] [blame] | 1425 | apic_write(APIC_LVT1, value); |
Cyrill Gorcunov | 89c38c2 | 2008-08-24 02:01:43 -0700 | [diff] [blame] | 1426 | |
Andi Kleen | be71b85 | 2009-02-12 13:49:38 +0100 | [diff] [blame] | 1427 | #ifdef CONFIG_X86_MCE_INTEL |
| 1428 | /* Recheck CMCI information after local APIC is up on CPU #0 */ |
Tejun Heo | 0aa002f | 2010-12-09 11:47:21 +0100 | [diff] [blame] | 1429 | if (!cpu) |
Andi Kleen | be71b85 | 2009-02-12 13:49:38 +0100 | [diff] [blame] | 1430 | cmci_recheck(); |
| 1431 | #endif |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1432 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1433 | |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 1434 | static void end_local_APIC_setup(void) |
Andi Kleen | 739f33b | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 1435 | { |
| 1436 | lapic_setup_esr(); |
Cyrill Gorcunov | fa6b95f | 2008-08-18 20:45:58 +0400 | [diff] [blame] | 1437 | |
| 1438 | #ifdef CONFIG_X86_32 |
Cyrill Gorcunov | 1b4ee4e | 2008-08-18 23:12:33 +0400 | [diff] [blame] | 1439 | { |
| 1440 | unsigned int value; |
| 1441 | /* Disable the local apic timer */ |
| 1442 | value = apic_read(APIC_LVTT); |
| 1443 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); |
| 1444 | apic_write(APIC_LVTT, value); |
| 1445 | } |
Cyrill Gorcunov | fa6b95f | 2008-08-18 20:45:58 +0400 | [diff] [blame] | 1446 | #endif |
| 1447 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1448 | apic_pm_activate(); |
Jan Beulich | 2fb270f | 2011-02-09 08:21:02 +0000 | [diff] [blame] | 1449 | } |
| 1450 | |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 1451 | /* |
| 1452 | * APIC setup function for application processors. Called from smpboot.c |
| 1453 | */ |
| 1454 | void apic_ap_setup(void) |
Jan Beulich | 2fb270f | 2011-02-09 08:21:02 +0000 | [diff] [blame] | 1455 | { |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 1456 | setup_local_APIC(); |
Jan Beulich | 2fb270f | 2011-02-09 08:21:02 +0000 | [diff] [blame] | 1457 | end_local_APIC_setup(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1458 | } |
| 1459 | |
Yinghai Lu | 06cd9a7 | 2009-02-16 17:29:58 -0800 | [diff] [blame] | 1460 | #ifdef CONFIG_X86_X2APIC |
Thomas Gleixner | bfb0507 | 2015-01-15 21:22:12 +0000 | [diff] [blame] | 1461 | int x2apic_mode; |
Thomas Gleixner | 12e189d | 2015-01-15 21:22:22 +0000 | [diff] [blame] | 1462 | |
| 1463 | enum { |
| 1464 | X2APIC_OFF, |
| 1465 | X2APIC_ON, |
| 1466 | X2APIC_DISABLED, |
| 1467 | }; |
| 1468 | static int x2apic_state; |
| 1469 | |
Denys Vlasenko | d786ad3 | 2015-09-29 22:37:02 +0200 | [diff] [blame] | 1470 | static void __x2apic_disable(void) |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1471 | { |
| 1472 | u64 msr; |
| 1473 | |
Borislav Petkov | 93984fb | 2016-04-04 22:25:00 +0200 | [diff] [blame] | 1474 | if (!boot_cpu_has(X86_FEATURE_APIC)) |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1475 | return; |
| 1476 | |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1477 | rdmsrl(MSR_IA32_APICBASE, msr); |
| 1478 | if (!(msr & X2APIC_ENABLE)) |
| 1479 | return; |
| 1480 | /* Disable xapic and x2apic first and then reenable xapic mode */ |
| 1481 | wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); |
| 1482 | wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); |
| 1483 | printk_once(KERN_INFO "x2apic disabled\n"); |
| 1484 | } |
| 1485 | |
Denys Vlasenko | d786ad3 | 2015-09-29 22:37:02 +0200 | [diff] [blame] | 1486 | static void __x2apic_enable(void) |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1487 | { |
| 1488 | u64 msr; |
| 1489 | |
| 1490 | rdmsrl(MSR_IA32_APICBASE, msr); |
| 1491 | if (msr & X2APIC_ENABLE) |
| 1492 | return; |
| 1493 | wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); |
| 1494 | printk_once(KERN_INFO "x2apic enabled\n"); |
| 1495 | } |
| 1496 | |
Thomas Gleixner | bfb0507 | 2015-01-15 21:22:12 +0000 | [diff] [blame] | 1497 | static int __init setup_nox2apic(char *str) |
| 1498 | { |
| 1499 | if (x2apic_enabled()) { |
| 1500 | int apicid = native_apic_msr_read(APIC_ID); |
| 1501 | |
| 1502 | if (apicid >= 255) { |
| 1503 | pr_warning("Apicid: %08x, cannot enforce nox2apic\n", |
| 1504 | apicid); |
| 1505 | return 0; |
| 1506 | } |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1507 | pr_warning("x2apic already enabled.\n"); |
| 1508 | __x2apic_disable(); |
| 1509 | } |
| 1510 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); |
Thomas Gleixner | 12e189d | 2015-01-15 21:22:22 +0000 | [diff] [blame] | 1511 | x2apic_state = X2APIC_DISABLED; |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1512 | x2apic_mode = 0; |
Thomas Gleixner | bfb0507 | 2015-01-15 21:22:12 +0000 | [diff] [blame] | 1513 | return 0; |
| 1514 | } |
| 1515 | early_param("nox2apic", setup_nox2apic); |
| 1516 | |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1517 | /* Called from cpu_init() to enable x2apic on (secondary) cpus */ |
| 1518 | void x2apic_setup(void) |
| 1519 | { |
| 1520 | /* |
| 1521 | * If x2apic is not in ON state, disable it if already enabled |
| 1522 | * from BIOS. |
| 1523 | */ |
| 1524 | if (x2apic_state != X2APIC_ON) { |
| 1525 | __x2apic_disable(); |
| 1526 | return; |
| 1527 | } |
| 1528 | __x2apic_enable(); |
| 1529 | } |
| 1530 | |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1531 | static __init void x2apic_disable(void) |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1532 | { |
Thomas Gleixner | a57e456 | 2015-08-22 16:41:17 +0200 | [diff] [blame] | 1533 | u32 x2apic_id, state = x2apic_state; |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1534 | |
Thomas Gleixner | a57e456 | 2015-08-22 16:41:17 +0200 | [diff] [blame] | 1535 | x2apic_mode = 0; |
| 1536 | x2apic_state = X2APIC_DISABLED; |
| 1537 | |
| 1538 | if (state != X2APIC_ON) |
| 1539 | return; |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1540 | |
Thomas Gleixner | 6d2d49d | 2015-01-15 21:22:27 +0000 | [diff] [blame] | 1541 | x2apic_id = read_apic_id(); |
| 1542 | if (x2apic_id >= 255) |
| 1543 | panic("Cannot disable x2apic, id: %08x\n", x2apic_id); |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1544 | |
Thomas Gleixner | 6d2d49d | 2015-01-15 21:22:27 +0000 | [diff] [blame] | 1545 | __x2apic_disable(); |
| 1546 | register_lapic_address(mp_lapic_addr); |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1547 | } |
| 1548 | |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1549 | static __init void x2apic_enable(void) |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1550 | { |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1551 | if (x2apic_state != X2APIC_OFF) |
Yinghai Lu | 06cd9a7 | 2009-02-16 17:29:58 -0800 | [diff] [blame] | 1552 | return; |
| 1553 | |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1554 | x2apic_mode = 1; |
Thomas Gleixner | 12e189d | 2015-01-15 21:22:22 +0000 | [diff] [blame] | 1555 | x2apic_state = X2APIC_ON; |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1556 | __x2apic_enable(); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1557 | } |
Thomas Gleixner | d524165 | 2015-01-15 21:22:17 +0000 | [diff] [blame] | 1558 | |
Thomas Gleixner | 62e6163 | 2015-01-15 21:22:21 +0000 | [diff] [blame] | 1559 | static __init void try_to_enable_x2apic(int remap_mode) |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1560 | { |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1561 | if (x2apic_state == X2APIC_DISABLED) |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1562 | return; |
| 1563 | |
Thomas Gleixner | 62e6163 | 2015-01-15 21:22:21 +0000 | [diff] [blame] | 1564 | if (remap_mode != IRQ_REMAP_X2APIC_MODE) { |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1565 | /* IR is required if there is APIC ID > 255 even when running |
| 1566 | * under KVM |
| 1567 | */ |
| 1568 | if (max_physical_apicid > 255 || |
Linus Torvalds | 8329aa9 | 2015-02-13 10:26:18 -0800 | [diff] [blame] | 1569 | !hypervisor_x2apic_available()) { |
Thomas Gleixner | 62e6163 | 2015-01-15 21:22:21 +0000 | [diff] [blame] | 1570 | pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); |
Thomas Gleixner | 44e25ff | 2015-01-15 21:22:24 +0000 | [diff] [blame] | 1571 | x2apic_disable(); |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1572 | return; |
| 1573 | } |
| 1574 | |
| 1575 | /* |
| 1576 | * without IR all CPUs can be addressed by IOAPIC/MSI |
| 1577 | * only in physical mode |
| 1578 | */ |
Thomas Gleixner | 55eae7d | 2015-01-15 21:22:19 +0000 | [diff] [blame] | 1579 | x2apic_phys = 1; |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1580 | } |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1581 | x2apic_enable(); |
Thomas Gleixner | 55eae7d | 2015-01-15 21:22:19 +0000 | [diff] [blame] | 1582 | } |
| 1583 | |
| 1584 | void __init check_x2apic(void) |
| 1585 | { |
| 1586 | if (x2apic_enabled()) { |
| 1587 | pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); |
| 1588 | x2apic_mode = 1; |
Thomas Gleixner | 12e189d | 2015-01-15 21:22:22 +0000 | [diff] [blame] | 1589 | x2apic_state = X2APIC_ON; |
Borislav Petkov | 62436a4 | 2016-03-29 17:41:57 +0200 | [diff] [blame] | 1590 | } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { |
Thomas Gleixner | 12e189d | 2015-01-15 21:22:22 +0000 | [diff] [blame] | 1591 | x2apic_state = X2APIC_DISABLED; |
Thomas Gleixner | 55eae7d | 2015-01-15 21:22:19 +0000 | [diff] [blame] | 1592 | } |
| 1593 | } |
| 1594 | #else /* CONFIG_X86_X2APIC */ |
| 1595 | static int __init validate_x2apic(void) |
| 1596 | { |
| 1597 | if (!apic_is_x2apic_enabled()) |
| 1598 | return 0; |
| 1599 | /* |
| 1600 | * Checkme: Can we simply turn off x2apic here instead of panic? |
| 1601 | */ |
| 1602 | panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); |
| 1603 | } |
| 1604 | early_initcall(validate_x2apic); |
| 1605 | |
Thomas Gleixner | 62e6163 | 2015-01-15 21:22:21 +0000 | [diff] [blame] | 1606 | static inline void try_to_enable_x2apic(int remap_mode) { } |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 1607 | static inline void __x2apic_enable(void) { } |
Thomas Gleixner | 55eae7d | 2015-01-15 21:22:19 +0000 | [diff] [blame] | 1608 | #endif /* !CONFIG_X86_X2APIC */ |
| 1609 | |
| 1610 | static int __init try_to_enable_IR(void) |
| 1611 | { |
| 1612 | #ifdef CONFIG_X86_IO_APIC |
| 1613 | if (!x2apic_enabled() && skip_ioapic_setup) { |
| 1614 | pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); |
| 1615 | return -1; |
| 1616 | } |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1617 | #endif |
Thomas Gleixner | 55eae7d | 2015-01-15 21:22:19 +0000 | [diff] [blame] | 1618 | return irq_remapping_enable(); |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1619 | } |
| 1620 | |
| 1621 | void __init enable_IR_x2apic(void) |
| 1622 | { |
| 1623 | unsigned long flags; |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1624 | int ret, ir_stat; |
Yinghai Lu | b7f42ab | 2009-08-17 11:19:40 -0700 | [diff] [blame] | 1625 | |
Wanpeng Li | 2e63ad4 | 2016-08-23 20:07:19 +0800 | [diff] [blame] | 1626 | if (skip_ioapic_setup) |
| 1627 | return; |
| 1628 | |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1629 | ir_stat = irq_remapping_prepare(); |
| 1630 | if (ir_stat < 0 && !x2apic_supported()) |
Yinghai Lu | e670761 | 2009-11-21 00:23:37 -0800 | [diff] [blame] | 1631 | return; |
Gleb Natapov | ce69a78 | 2009-07-20 15:24:17 +0300 | [diff] [blame] | 1632 | |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 1633 | ret = save_ioapic_entries(); |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1634 | if (ret) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1635 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 1636 | return; |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 1637 | } |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1638 | |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 1639 | local_irq_save(flags); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 1640 | legacy_pic->mask_all(); |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 1641 | mask_ioapic_entries(); |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 1642 | |
Adam Buchbinder | 6a6256f | 2016-02-23 15:34:30 -0800 | [diff] [blame] | 1643 | /* If irq_remapping_prepare() succeeded, try to enable it */ |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1644 | if (ir_stat >= 0) |
| 1645 | ir_stat = try_to_enable_IR(); |
| 1646 | /* ir_stat contains the remap mode or an error code */ |
| 1647 | try_to_enable_x2apic(ir_stat); |
Yinghai Lu | a31bc32 | 2011-12-23 11:01:43 -0800 | [diff] [blame] | 1648 | |
Jiang Liu | 07806c5 | 2015-01-07 15:31:34 +0800 | [diff] [blame] | 1649 | if (ir_stat < 0) |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 1650 | restore_ioapic_entries(); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 1651 | legacy_pic->restore_mask(); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1652 | local_irq_restore(flags); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1653 | } |
Weidong Han | 9375823 | 2009-04-17 16:42:14 +0800 | [diff] [blame] | 1654 | |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1655 | #ifdef CONFIG_X86_64 |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1656 | /* |
| 1657 | * Detect and enable local APICs on non-SMP boards. |
| 1658 | * Original code written by Keir Fraser. |
| 1659 | * On AMD64 we trust the BIOS - if it says no APIC it is likely |
| 1660 | * not correctly set up (usually the APIC timer won't work etc.) |
| 1661 | */ |
| 1662 | static int __init detect_init_APIC(void) |
| 1663 | { |
Borislav Petkov | 93984fb | 2016-04-04 22:25:00 +0200 | [diff] [blame] | 1664 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1665 | pr_info("No local APIC present\n"); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1666 | return -1; |
| 1667 | } |
| 1668 | |
| 1669 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1670 | return 0; |
| 1671 | } |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1672 | #else |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1673 | |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 1674 | static int __init apic_verify(void) |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1675 | { |
| 1676 | u32 features, h, l; |
| 1677 | |
| 1678 | /* |
| 1679 | * The APIC feature bit should now be enabled |
| 1680 | * in `cpuid' |
| 1681 | */ |
| 1682 | features = cpuid_edx(1); |
| 1683 | if (!(features & (1 << X86_FEATURE_APIC))) { |
| 1684 | pr_warning("Could not enable APIC!\n"); |
| 1685 | return -1; |
| 1686 | } |
| 1687 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
| 1688 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
| 1689 | |
| 1690 | /* The BIOS may have set up the APIC at some other address */ |
Bryan O'Donoghue | cbf2829 | 2012-04-18 17:37:39 +0100 | [diff] [blame] | 1691 | if (boot_cpu_data.x86 >= 6) { |
| 1692 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 1693 | if (l & MSR_IA32_APICBASE_ENABLE) |
| 1694 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; |
| 1695 | } |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1696 | |
| 1697 | pr_info("Found and enabled local APIC!\n"); |
| 1698 | return 0; |
| 1699 | } |
| 1700 | |
Henrik Kretzschmar | 25874a2 | 2011-03-11 08:02:36 +0100 | [diff] [blame] | 1701 | int __init apic_force_enable(unsigned long addr) |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1702 | { |
| 1703 | u32 h, l; |
| 1704 | |
| 1705 | if (disable_apic) |
| 1706 | return -1; |
| 1707 | |
| 1708 | /* |
| 1709 | * Some BIOSes disable the local APIC in the APIC_BASE |
| 1710 | * MSR. This can only be done in software for Intel P6 or later |
| 1711 | * and AMD K7 (Model > 1) or later. |
| 1712 | */ |
Bryan O'Donoghue | cbf2829 | 2012-04-18 17:37:39 +0100 | [diff] [blame] | 1713 | if (boot_cpu_data.x86 >= 6) { |
| 1714 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 1715 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { |
| 1716 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
| 1717 | l &= ~MSR_IA32_APICBASE_BASE; |
| 1718 | l |= MSR_IA32_APICBASE_ENABLE | addr; |
| 1719 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 1720 | enabled_via_apicbase = 1; |
| 1721 | } |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1722 | } |
| 1723 | return apic_verify(); |
| 1724 | } |
| 1725 | |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1726 | /* |
| 1727 | * Detect and initialize APIC |
| 1728 | */ |
| 1729 | static int __init detect_init_APIC(void) |
| 1730 | { |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1731 | /* Disabled by kernel option? */ |
| 1732 | if (disable_apic) |
| 1733 | return -1; |
| 1734 | |
| 1735 | switch (boot_cpu_data.x86_vendor) { |
| 1736 | case X86_VENDOR_AMD: |
| 1737 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || |
Borislav Petkov | 8587706 | 2009-02-03 16:24:22 +0100 | [diff] [blame] | 1738 | (boot_cpu_data.x86 >= 15)) |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1739 | break; |
| 1740 | goto no_apic; |
| 1741 | case X86_VENDOR_INTEL: |
| 1742 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || |
Borislav Petkov | 93984fb | 2016-04-04 22:25:00 +0200 | [diff] [blame] | 1743 | (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1744 | break; |
| 1745 | goto no_apic; |
| 1746 | default: |
| 1747 | goto no_apic; |
| 1748 | } |
| 1749 | |
Borislav Petkov | 93984fb | 2016-04-04 22:25:00 +0200 | [diff] [blame] | 1750 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1751 | /* |
| 1752 | * Over-ride BIOS and try to enable the local APIC only if |
| 1753 | * "lapic" specified. |
| 1754 | */ |
| 1755 | if (!force_enable_local_apic) { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1756 | pr_info("Local APIC disabled by BIOS -- " |
| 1757 | "you can enable it with \"lapic\"\n"); |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1758 | return -1; |
| 1759 | } |
Thomas Gleixner | a906fda | 2011-02-25 16:09:31 +0100 | [diff] [blame] | 1760 | if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) |
Thomas Gleixner | 5a7ae78 | 2010-10-19 10:46:28 -0700 | [diff] [blame] | 1761 | return -1; |
| 1762 | } else { |
| 1763 | if (apic_verify()) |
| 1764 | return -1; |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1765 | } |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1766 | |
| 1767 | apic_pm_activate(); |
| 1768 | |
| 1769 | return 0; |
| 1770 | |
| 1771 | no_apic: |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 1772 | pr_info("No local APIC present or hardware disabled\n"); |
Yinghai Lu | be7a656 | 2008-08-24 02:01:51 -0700 | [diff] [blame] | 1773 | return -1; |
| 1774 | } |
| 1775 | #endif |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1776 | |
| 1777 | /** |
| 1778 | * init_apic_mappings - initialize APIC mappings |
| 1779 | */ |
| 1780 | void __init init_apic_mappings(void) |
| 1781 | { |
Yinghai Lu | 4401da6 | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1782 | unsigned int new_apicid; |
| 1783 | |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 1784 | if (x2apic_mode) { |
Yinghai Lu | 4c9961d | 2008-07-11 18:44:16 -0700 | [diff] [blame] | 1785 | boot_cpu_physical_apicid = read_apic_id(); |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 1786 | return; |
| 1787 | } |
| 1788 | |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1789 | /* If no local APIC can be found return early */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1790 | if (!smp_found_config && detect_init_APIC()) { |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1791 | /* lets NOP'ify apic operations */ |
Cyrill Gorcunov | cec6be6 | 2009-05-11 17:41:40 +0400 | [diff] [blame] | 1792 | pr_info("APIC: disable apic facility\n"); |
| 1793 | apic_disable(); |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1794 | } else { |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1795 | apic_phys = mp_lapic_addr; |
| 1796 | |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1797 | /* |
| 1798 | * acpi lapic path already maps that address in |
| 1799 | * acpi_register_lapic_address() |
| 1800 | */ |
Eric W. Biederman | 5989cd6 | 2010-08-04 13:30:27 -0700 | [diff] [blame] | 1801 | if (!acpi_lapic && !smp_found_config) |
Yinghai Lu | 326a2e6 | 2010-12-07 00:55:38 -0800 | [diff] [blame] | 1802 | register_lapic_address(apic_phys); |
Cyrill Gorcunov | cec6be6 | 2009-05-11 17:41:40 +0400 | [diff] [blame] | 1803 | } |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1804 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1805 | /* |
| 1806 | * Fetch the APIC ID of the BSP in case we have a |
| 1807 | * default configuration (or the MP table is broken). |
| 1808 | */ |
Yinghai Lu | 4401da6 | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1809 | new_apicid = read_apic_id(); |
| 1810 | if (boot_cpu_physical_apicid != new_apicid) { |
| 1811 | boot_cpu_physical_apicid = new_apicid; |
Cyrill Gorcunov | 103428e | 2009-06-07 16:48:40 +0400 | [diff] [blame] | 1812 | /* |
| 1813 | * yeah -- we lie about apic_version |
| 1814 | * in case if apic was disabled via boot option |
| 1815 | * but it's not a problem for SMP compiled kernel |
| 1816 | * since smp_sanity_check is prepared for such a case |
| 1817 | * and disable smp mode |
| 1818 | */ |
Yinghai Lu | 4401da6 | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1819 | apic_version[new_apicid] = |
| 1820 | GET_APIC_VERSION(apic_read(APIC_LVR)); |
Cyrill Gorcunov | 08306ce | 2009-04-12 20:47:41 +0400 | [diff] [blame] | 1821 | } |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1822 | } |
| 1823 | |
Yinghai Lu | c0104d3 | 2010-12-07 00:55:17 -0800 | [diff] [blame] | 1824 | void __init register_lapic_address(unsigned long address) |
| 1825 | { |
| 1826 | mp_lapic_addr = address; |
| 1827 | |
Yinghai Lu | 0450193 | 2010-12-07 00:55:56 -0800 | [diff] [blame] | 1828 | if (!x2apic_mode) { |
| 1829 | set_fixmap_nocache(FIX_APIC_BASE, address); |
| 1830 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
| 1831 | APIC_BASE, mp_lapic_addr); |
| 1832 | } |
Yinghai Lu | c0104d3 | 2010-12-07 00:55:17 -0800 | [diff] [blame] | 1833 | if (boot_cpu_physical_apicid == -1U) { |
| 1834 | boot_cpu_physical_apicid = read_apic_id(); |
| 1835 | apic_version[boot_cpu_physical_apicid] = |
| 1836 | GET_APIC_VERSION(apic_read(APIC_LVR)); |
| 1837 | } |
| 1838 | } |
| 1839 | |
Yinghai Lu | 56d91f1 | 2010-12-16 19:09:24 -0800 | [diff] [blame] | 1840 | int apic_version[MAX_LOCAL_APIC]; |
Cyrill Gorcunov | 1b313f4 | 2008-08-18 20:45:57 +0400 | [diff] [blame] | 1841 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1842 | /* |
| 1843 | * Local APIC interrupts |
| 1844 | */ |
| 1845 | |
| 1846 | /* |
| 1847 | * This interrupt should _never_ happen with our APIC/SMP architecture |
| 1848 | */ |
Denys Vlasenko | d786ad3 | 2015-09-29 22:37:02 +0200 | [diff] [blame] | 1849 | static void __smp_spurious_interrupt(u8 vector) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1850 | { |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1851 | u32 v; |
| 1852 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1853 | /* |
| 1854 | * Check if this really is a spurious interrupt and ACK it |
| 1855 | * if it is a vectored one. Just in case... |
| 1856 | * Spurious interrupts should not be ACKed. |
| 1857 | */ |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 1858 | v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); |
| 1859 | if (v & (1 << (vector & 0x1f))) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1860 | ack_APIC_irq(); |
| 1861 | |
Hiroshi Shimamoto | 915b0d0 | 2008-12-08 19:19:26 -0800 | [diff] [blame] | 1862 | inc_irq_stat(irq_spurious_count); |
| 1863 | |
Yinghai Lu | dc1528d | 2008-08-24 02:01:53 -0700 | [diff] [blame] | 1864 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 1865 | pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " |
| 1866 | "should never happen.\n", vector, smp_processor_id()); |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 1867 | } |
| 1868 | |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 1869 | __visible void smp_spurious_interrupt(struct pt_regs *regs) |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 1870 | { |
| 1871 | entering_irq(); |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 1872 | __smp_spurious_interrupt(~regs->orig_ax); |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 1873 | exiting_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1874 | } |
| 1875 | |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 1876 | __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) |
Seiji Aguchi | cf910e8 | 2013-06-20 11:46:53 -0400 | [diff] [blame] | 1877 | { |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 1878 | u8 vector = ~regs->orig_ax; |
| 1879 | |
Seiji Aguchi | cf910e8 | 2013-06-20 11:46:53 -0400 | [diff] [blame] | 1880 | entering_irq(); |
Jan Beulich | 2414e02 | 2014-11-03 08:39:43 +0000 | [diff] [blame] | 1881 | trace_spurious_apic_entry(vector); |
| 1882 | __smp_spurious_interrupt(vector); |
| 1883 | trace_spurious_apic_exit(vector); |
Seiji Aguchi | cf910e8 | 2013-06-20 11:46:53 -0400 | [diff] [blame] | 1884 | exiting_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1885 | } |
| 1886 | |
| 1887 | /* |
| 1888 | * This interrupt should never happen with our APIC/SMP architecture |
| 1889 | */ |
Denys Vlasenko | d786ad3 | 2015-09-29 22:37:02 +0200 | [diff] [blame] | 1890 | static void __smp_error_interrupt(struct pt_regs *regs) |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1891 | { |
Richard Weinberger | 60283df | 2014-01-14 08:44:47 +0100 | [diff] [blame] | 1892 | u32 v; |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1893 | u32 i = 0; |
| 1894 | static const char * const error_interrupt_reason[] = { |
| 1895 | "Send CS error", /* APIC Error Bit 0 */ |
| 1896 | "Receive CS error", /* APIC Error Bit 1 */ |
| 1897 | "Send accept error", /* APIC Error Bit 2 */ |
| 1898 | "Receive accept error", /* APIC Error Bit 3 */ |
| 1899 | "Redirectable IPI", /* APIC Error Bit 4 */ |
| 1900 | "Send illegal vector", /* APIC Error Bit 5 */ |
| 1901 | "Received illegal vector", /* APIC Error Bit 6 */ |
| 1902 | "Illegal register address", /* APIC Error Bit 7 */ |
| 1903 | }; |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1904 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1905 | /* First tickle the hardware, only then report what went on. -- REW */ |
Maciej W. Rozycki | 023de4a | 2014-04-01 13:30:21 +0100 | [diff] [blame] | 1906 | if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ |
| 1907 | apic_write(APIC_ESR, 0); |
Richard Weinberger | 60283df | 2014-01-14 08:44:47 +0100 | [diff] [blame] | 1908 | v = apic_read(APIC_ESR); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1909 | ack_APIC_irq(); |
| 1910 | atomic_inc(&irq_err_count); |
| 1911 | |
Richard Weinberger | 60283df | 2014-01-14 08:44:47 +0100 | [diff] [blame] | 1912 | apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", |
| 1913 | smp_processor_id(), v); |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1914 | |
Richard Weinberger | 60283df | 2014-01-14 08:44:47 +0100 | [diff] [blame] | 1915 | v &= 0xff; |
| 1916 | while (v) { |
| 1917 | if (v & 0x1) |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1918 | apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); |
| 1919 | i++; |
Richard Weinberger | 60283df | 2014-01-14 08:44:47 +0100 | [diff] [blame] | 1920 | v >>= 1; |
Peter Senna Tschudin | 4b8073e | 2012-09-18 18:36:14 +0200 | [diff] [blame] | 1921 | } |
Youquan Song | 2b398bd | 2011-04-14 14:36:08 +0800 | [diff] [blame] | 1922 | |
| 1923 | apic_printk(APIC_DEBUG, KERN_CONT "\n"); |
| 1924 | |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 1925 | } |
| 1926 | |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 1927 | __visible void smp_error_interrupt(struct pt_regs *regs) |
Seiji Aguchi | eddc0e9 | 2013-06-20 11:45:17 -0400 | [diff] [blame] | 1928 | { |
| 1929 | entering_irq(); |
| 1930 | __smp_error_interrupt(regs); |
| 1931 | exiting_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1932 | } |
| 1933 | |
Andi Kleen | 1d9090e | 2013-08-05 15:02:37 -0700 | [diff] [blame] | 1934 | __visible void smp_trace_error_interrupt(struct pt_regs *regs) |
Seiji Aguchi | cf910e8 | 2013-06-20 11:46:53 -0400 | [diff] [blame] | 1935 | { |
| 1936 | entering_irq(); |
| 1937 | trace_error_apic_entry(ERROR_APIC_VECTOR); |
| 1938 | __smp_error_interrupt(regs); |
| 1939 | trace_error_apic_exit(ERROR_APIC_VECTOR); |
| 1940 | exiting_irq(); |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1941 | } |
| 1942 | |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1943 | /** |
Cyrill Gorcunov | 36c9d67 | 2008-08-18 20:45:53 +0400 | [diff] [blame] | 1944 | * connect_bsp_APIC - attach the APIC to the interrupt system |
| 1945 | */ |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 1946 | static void __init connect_bsp_APIC(void) |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1947 | { |
Cyrill Gorcunov | 36c9d67 | 2008-08-18 20:45:53 +0400 | [diff] [blame] | 1948 | #ifdef CONFIG_X86_32 |
| 1949 | if (pic_mode) { |
| 1950 | /* |
| 1951 | * Do not trust the local APIC being empty at bootup. |
| 1952 | */ |
| 1953 | clear_local_APIC(); |
| 1954 | /* |
| 1955 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's |
| 1956 | * local APIC to INT and NMI lines. |
| 1957 | */ |
| 1958 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " |
| 1959 | "enabling APIC mode.\n"); |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 1960 | imcr_pic_to_apic(); |
Cyrill Gorcunov | 36c9d67 | 2008-08-18 20:45:53 +0400 | [diff] [blame] | 1961 | } |
| 1962 | #endif |
Glauber Costa | b584176 | 2008-05-28 13:38:28 -0300 | [diff] [blame] | 1963 | } |
| 1964 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 1965 | /** |
| 1966 | * disconnect_bsp_APIC - detach the APIC from the interrupt system |
| 1967 | * @virt_wire_setup: indicates, whether virtual wire mode is selected |
| 1968 | * |
| 1969 | * Virtual wire mode is necessary to deliver legacy interrupts even when the |
| 1970 | * APIC is disabled. |
| 1971 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1972 | void disconnect_bsp_APIC(int virt_wire_setup) |
| 1973 | { |
Cyrill Gorcunov | 1b4ee4e | 2008-08-18 23:12:33 +0400 | [diff] [blame] | 1974 | unsigned int value; |
| 1975 | |
Cyrill Gorcunov | c177b0b | 2008-08-18 20:45:56 +0400 | [diff] [blame] | 1976 | #ifdef CONFIG_X86_32 |
| 1977 | if (pic_mode) { |
| 1978 | /* |
| 1979 | * Put the board back into PIC mode (has an effect only on |
| 1980 | * certain older boards). Note that APIC interrupts, including |
| 1981 | * IPIs, won't work beyond this point! The only exception are |
| 1982 | * INIT IPIs. |
| 1983 | */ |
| 1984 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " |
| 1985 | "entering PIC mode.\n"); |
Cyrill Gorcunov | c0eaa45 | 2009-04-12 20:47:40 +0400 | [diff] [blame] | 1986 | imcr_apic_to_pic(); |
Cyrill Gorcunov | c177b0b | 2008-08-18 20:45:56 +0400 | [diff] [blame] | 1987 | return; |
| 1988 | } |
| 1989 | #endif |
| 1990 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1991 | /* Go back to Virtual Wire compatibility mode */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 1992 | |
| 1993 | /* For the spurious interrupt use vector F, and enable it */ |
| 1994 | value = apic_read(APIC_SPIV); |
| 1995 | value &= ~APIC_VECTOR_MASK; |
| 1996 | value |= APIC_SPIV_APIC_ENABLED; |
| 1997 | value |= 0xf; |
| 1998 | apic_write(APIC_SPIV, value); |
| 1999 | |
| 2000 | if (!virt_wire_setup) { |
| 2001 | /* |
| 2002 | * For LVT0 make it edge triggered, active high, |
| 2003 | * external and enabled |
| 2004 | */ |
| 2005 | value = apic_read(APIC_LVT0); |
| 2006 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | |
| 2007 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 2008 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
| 2009 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 2010 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
| 2011 | apic_write(APIC_LVT0, value); |
| 2012 | } else { |
| 2013 | /* Disable LVT0 */ |
| 2014 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
| 2015 | } |
| 2016 | |
Cyrill Gorcunov | c177b0b | 2008-08-18 20:45:56 +0400 | [diff] [blame] | 2017 | /* |
| 2018 | * For LVT1 make it edge triggered, active high, |
| 2019 | * nmi and enabled |
| 2020 | */ |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2021 | value = apic_read(APIC_LVT1); |
| 2022 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | |
| 2023 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
| 2024 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); |
| 2025 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
| 2026 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); |
| 2027 | apic_write(APIC_LVT1, value); |
| 2028 | } |
| 2029 | |
Jiang Liu | 7e1f85f | 2013-09-02 11:57:36 +0800 | [diff] [blame] | 2030 | int generic_processor_info(int apicid, int version) |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2031 | { |
Vivek Goyal | 14cb6dc | 2011-07-08 13:19:26 -0400 | [diff] [blame] | 2032 | int cpu, max = nr_cpu_ids; |
| 2033 | bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, |
| 2034 | phys_cpu_present_map); |
| 2035 | |
| 2036 | /* |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 2037 | * boot_cpu_physical_apicid is designed to have the apicid |
| 2038 | * returned by read_apic_id(), i.e, the apicid of the |
| 2039 | * currently booting-up processor. However, on some platforms, |
H. Peter Anvin | 5b4d1db | 2014-01-15 13:02:08 -0800 | [diff] [blame] | 2040 | * it is temporarily modified by the apicid reported as BSP |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 2041 | * through MP table. Concretely: |
| 2042 | * |
| 2043 | * - arch/x86/kernel/mpparse.c: MP_processor_info() |
| 2044 | * - arch/x86/mm/amdtopology.c: amd_numa_init() |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 2045 | * |
| 2046 | * This function is executed with the modified |
| 2047 | * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel |
| 2048 | * parameter doesn't work to disable APs on kdump 2nd kernel. |
| 2049 | * |
| 2050 | * Since fixing handling of boot_cpu_physical_apicid requires |
| 2051 | * another discussion and tests on each platform, we leave it |
| 2052 | * for now and here we use read_apic_id() directly in this |
| 2053 | * function, generic_processor_info(). |
| 2054 | */ |
| 2055 | if (disabled_cpu_apicid != BAD_APICID && |
| 2056 | disabled_cpu_apicid != read_apic_id() && |
| 2057 | disabled_cpu_apicid == apicid) { |
| 2058 | int thiscpu = num_processors + disabled_cpus; |
| 2059 | |
H. Peter Anvin | 5b4d1db | 2014-01-15 13:02:08 -0800 | [diff] [blame] | 2060 | pr_warning("APIC: Disabling requested cpu." |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 2061 | " Processor %d/0x%x ignored.\n", |
| 2062 | thiscpu, apicid); |
| 2063 | |
| 2064 | disabled_cpus++; |
| 2065 | return -ENODEV; |
| 2066 | } |
| 2067 | |
| 2068 | /* |
Vivek Goyal | 14cb6dc | 2011-07-08 13:19:26 -0400 | [diff] [blame] | 2069 | * If boot cpu has not been detected yet, then only allow upto |
| 2070 | * nr_cpu_ids - 1 processors and keep one slot free for boot cpu |
| 2071 | */ |
| 2072 | if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && |
| 2073 | apicid != boot_cpu_physical_apicid) { |
| 2074 | int thiscpu = max + disabled_cpus - 1; |
| 2075 | |
| 2076 | pr_warning( |
Claudio Fontana | 3c8fad9 | 2016-06-09 12:31:58 +0200 | [diff] [blame] | 2077 | "APIC: NR_CPUS/possible_cpus limit of %i almost" |
Vivek Goyal | 14cb6dc | 2011-07-08 13:19:26 -0400 | [diff] [blame] | 2078 | " reached. Keeping one slot for boot cpu." |
| 2079 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); |
| 2080 | |
| 2081 | disabled_cpus++; |
Jiang Liu | 7e1f85f | 2013-09-02 11:57:36 +0800 | [diff] [blame] | 2082 | return -ENODEV; |
Vivek Goyal | 14cb6dc | 2011-07-08 13:19:26 -0400 | [diff] [blame] | 2083 | } |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2084 | |
Mike Travis | 3b11ce7 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 2085 | if (num_processors >= nr_cpu_ids) { |
Mike Travis | 3b11ce7 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 2086 | int thiscpu = max + disabled_cpus; |
| 2087 | |
| 2088 | pr_warning( |
Claudio Fontana | 3c8fad9 | 2016-06-09 12:31:58 +0200 | [diff] [blame] | 2089 | "APIC: NR_CPUS/possible_cpus limit of %i reached." |
Mike Travis | 3b11ce7 | 2008-12-17 15:21:39 -0800 | [diff] [blame] | 2090 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); |
| 2091 | |
| 2092 | disabled_cpus++; |
Jiang Liu | 7e1f85f | 2013-09-02 11:57:36 +0800 | [diff] [blame] | 2093 | return -EINVAL; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2094 | } |
| 2095 | |
| 2096 | num_processors++; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2097 | if (apicid == boot_cpu_physical_apicid) { |
| 2098 | /* |
| 2099 | * x86_bios_cpu_apicid is required to have processors listed |
| 2100 | * in same order as logical cpu numbers. Hence the first |
| 2101 | * entry is BSP, and so on. |
Yinghai Lu | e5fea86 | 2011-02-08 23:22:17 -0800 | [diff] [blame] | 2102 | * boot_cpu_init() already hold bit 0 in cpu_present_mask |
| 2103 | * for BSP. |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2104 | */ |
| 2105 | cpu = 0; |
Yinghai Lu | e5fea86 | 2011-02-08 23:22:17 -0800 | [diff] [blame] | 2106 | } else |
| 2107 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
| 2108 | |
| 2109 | /* |
Thomas Gleixner | 1f12e32 | 2016-02-22 22:19:15 +0000 | [diff] [blame] | 2110 | * This can happen on physical hotplug. The sanity check at boot time |
| 2111 | * is done from native_smp_prepare_cpus() after num_possible_cpus() is |
| 2112 | * established. |
| 2113 | */ |
| 2114 | if (topology_update_package_map(apicid, cpu) < 0) { |
| 2115 | int thiscpu = max + disabled_cpus; |
| 2116 | |
Claudio Fontana | 3c8fad9 | 2016-06-09 12:31:58 +0200 | [diff] [blame] | 2117 | pr_warning("APIC: Package limit reached. Processor %d/0x%x ignored.\n", |
Thomas Gleixner | 1f12e32 | 2016-02-22 22:19:15 +0000 | [diff] [blame] | 2118 | thiscpu, apicid); |
| 2119 | disabled_cpus++; |
| 2120 | return -ENOSPC; |
| 2121 | } |
| 2122 | |
| 2123 | /* |
Yinghai Lu | e5fea86 | 2011-02-08 23:22:17 -0800 | [diff] [blame] | 2124 | * Validate version |
| 2125 | */ |
| 2126 | if (version == 0x0) { |
| 2127 | pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", |
| 2128 | cpu, apicid); |
| 2129 | version = 0x10; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2130 | } |
Yinghai Lu | e5fea86 | 2011-02-08 23:22:17 -0800 | [diff] [blame] | 2131 | apic_version[apicid] = version; |
| 2132 | |
| 2133 | if (version != apic_version[boot_cpu_physical_apicid]) { |
| 2134 | pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", |
| 2135 | apic_version[boot_cpu_physical_apicid], cpu, version); |
| 2136 | } |
| 2137 | |
| 2138 | physid_set(apicid, phys_cpu_present_map); |
Yinghai Lu | e0da336 | 2008-06-08 18:29:22 -0700 | [diff] [blame] | 2139 | if (apicid > max_physical_apicid) |
| 2140 | max_physical_apicid = apicid; |
| 2141 | |
Ingo Molnar | 3e5095d | 2009-01-27 17:07:08 +0100 | [diff] [blame] | 2142 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
Tejun Heo | f10fcd4 | 2009-01-13 20:41:34 +0900 | [diff] [blame] | 2143 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
| 2144 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; |
Cyrill Gorcunov | 1b313f4 | 2008-08-18 20:45:57 +0400 | [diff] [blame] | 2145 | #endif |
Tejun Heo | acb8bc0 | 2011-01-23 14:37:33 +0100 | [diff] [blame] | 2146 | #ifdef CONFIG_X86_32 |
| 2147 | early_per_cpu(x86_cpu_to_logical_apicid, cpu) = |
| 2148 | apic->x86_32_early_logical_apicid(cpu); |
| 2149 | #endif |
Mike Travis | 1de88cd | 2008-12-16 17:34:02 -0800 | [diff] [blame] | 2150 | set_cpu_possible(cpu, true); |
| 2151 | set_cpu_present(cpu, true); |
Jiang Liu | 7e1f85f | 2013-09-02 11:57:36 +0800 | [diff] [blame] | 2152 | |
| 2153 | return cpu; |
Alexey Starikovskiy | be8a568 | 2008-03-27 23:56:19 +0300 | [diff] [blame] | 2154 | } |
| 2155 | |
Suresh Siddha | 0c81c74 | 2008-07-10 11:16:48 -0700 | [diff] [blame] | 2156 | int hard_smp_processor_id(void) |
| 2157 | { |
| 2158 | return read_apic_id(); |
| 2159 | } |
Ingo Molnar | 1dcdd3d | 2009-01-28 17:55:37 +0100 | [diff] [blame] | 2160 | |
| 2161 | void default_init_apic_ldr(void) |
| 2162 | { |
| 2163 | unsigned long val; |
| 2164 | |
| 2165 | apic_write(APIC_DFR, APIC_DFR_VALUE); |
| 2166 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
| 2167 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); |
| 2168 | apic_write(APIC_LDR, val); |
| 2169 | } |
| 2170 | |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 2171 | int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
| 2172 | const struct cpumask *andmask, |
| 2173 | unsigned int *apicid) |
Alexander Gordeev | 6398268 | 2012-06-05 13:23:44 +0200 | [diff] [blame] | 2174 | { |
Alexander Gordeev | ea3807e | 2012-06-14 09:49:55 +0200 | [diff] [blame] | 2175 | unsigned int cpu; |
Alexander Gordeev | 6398268 | 2012-06-05 13:23:44 +0200 | [diff] [blame] | 2176 | |
| 2177 | for_each_cpu_and(cpu, cpumask, andmask) { |
| 2178 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
| 2179 | break; |
| 2180 | } |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 2181 | |
Alexander Gordeev | ea3807e | 2012-06-14 09:49:55 +0200 | [diff] [blame] | 2182 | if (likely(cpu < nr_cpu_ids)) { |
Alexander Gordeev | a5a3915 | 2012-06-14 09:49:35 +0200 | [diff] [blame] | 2183 | *apicid = per_cpu(x86_cpu_to_apicid, cpu); |
| 2184 | return 0; |
Alexander Gordeev | a5a3915 | 2012-06-14 09:49:35 +0200 | [diff] [blame] | 2185 | } |
Alexander Gordeev | ea3807e | 2012-06-14 09:49:55 +0200 | [diff] [blame] | 2186 | |
| 2187 | return -EINVAL; |
Alexander Gordeev | 6398268 | 2012-06-05 13:23:44 +0200 | [diff] [blame] | 2188 | } |
| 2189 | |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2190 | /* |
Michael S. Tsirkin | 1551df6 | 2012-07-15 15:56:46 +0300 | [diff] [blame] | 2191 | * Override the generic EOI implementation with an optimized version. |
| 2192 | * Only called during early boot when only one CPU is active and with |
| 2193 | * interrupts disabled, so we know this does not race with actual APIC driver |
| 2194 | * use. |
| 2195 | */ |
| 2196 | void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) |
| 2197 | { |
| 2198 | struct apic **drv; |
| 2199 | |
| 2200 | for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { |
| 2201 | /* Should happen once for each apic */ |
| 2202 | WARN_ON((*drv)->eoi_write == eoi_write); |
| 2203 | (*drv)->eoi_write = eoi_write; |
| 2204 | } |
| 2205 | } |
| 2206 | |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2207 | static void __init apic_bsp_up_setup(void) |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2208 | { |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2209 | #ifdef CONFIG_X86_64 |
| 2210 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
| 2211 | #else |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2212 | /* |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2213 | * Hack: In case of kdump, after a crash, kernel might be booting |
| 2214 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid |
| 2215 | * might be zero if read from MP tables. Get it from LAPIC. |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2216 | */ |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2217 | # ifdef CONFIG_CRASH_DUMP |
| 2218 | boot_cpu_physical_apicid = read_apic_id(); |
| 2219 | # endif |
| 2220 | #endif |
| 2221 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2222 | } |
| 2223 | |
| 2224 | /** |
| 2225 | * apic_bsp_setup - Setup function for local apic and io-apic |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2226 | * @upmode: Force UP mode (for APIC_init_uniprocessor) |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2227 | * |
| 2228 | * Returns: |
| 2229 | * apic_id of BSP APIC |
| 2230 | */ |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2231 | int __init apic_bsp_setup(bool upmode) |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2232 | { |
| 2233 | int id; |
| 2234 | |
| 2235 | connect_bsp_APIC(); |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2236 | if (upmode) |
| 2237 | apic_bsp_up_setup(); |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2238 | setup_local_APIC(); |
| 2239 | |
| 2240 | if (x2apic_mode) |
| 2241 | id = apic_read(APIC_LDR); |
| 2242 | else |
| 2243 | id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); |
| 2244 | |
| 2245 | enable_IO_APIC(); |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2246 | end_local_APIC_setup(); |
| 2247 | irq_remap_enable_fault_handling(); |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2248 | setup_IO_APIC(); |
Thomas Gleixner | 9c4d9c7 | 2015-01-15 21:22:45 +0000 | [diff] [blame] | 2249 | /* Setup local timer */ |
| 2250 | x86_init.timers.setup_percpu_clockev(); |
Thomas Gleixner | 05f7e46 | 2015-01-15 21:22:40 +0000 | [diff] [blame] | 2251 | return id; |
| 2252 | } |
| 2253 | |
Michael S. Tsirkin | 1551df6 | 2012-07-15 15:56:46 +0300 | [diff] [blame] | 2254 | /* |
Thomas Gleixner | e714a91 | 2015-01-15 21:22:37 +0000 | [diff] [blame] | 2255 | * This initializes the IO-APIC and APIC hardware if this is |
| 2256 | * a UP kernel. |
| 2257 | */ |
| 2258 | int __init APIC_init_uniprocessor(void) |
| 2259 | { |
| 2260 | if (disable_apic) { |
| 2261 | pr_info("Apic disabled\n"); |
| 2262 | return -1; |
| 2263 | } |
| 2264 | #ifdef CONFIG_X86_64 |
Borislav Petkov | 93984fb | 2016-04-04 22:25:00 +0200 | [diff] [blame] | 2265 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
Thomas Gleixner | e714a91 | 2015-01-15 21:22:37 +0000 | [diff] [blame] | 2266 | disable_apic = 1; |
| 2267 | pr_info("Apic disabled by BIOS\n"); |
| 2268 | return -1; |
| 2269 | } |
| 2270 | #else |
Borislav Petkov | 93984fb | 2016-04-04 22:25:00 +0200 | [diff] [blame] | 2271 | if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC)) |
Thomas Gleixner | e714a91 | 2015-01-15 21:22:37 +0000 | [diff] [blame] | 2272 | return -1; |
| 2273 | |
| 2274 | /* |
| 2275 | * Complain if the BIOS pretends there is one. |
| 2276 | */ |
Borislav Petkov | 93984fb | 2016-04-04 22:25:00 +0200 | [diff] [blame] | 2277 | if (!boot_cpu_has(X86_FEATURE_APIC) && |
Thomas Gleixner | e714a91 | 2015-01-15 21:22:37 +0000 | [diff] [blame] | 2278 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
| 2279 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
| 2280 | boot_cpu_physical_apicid); |
| 2281 | return -1; |
| 2282 | } |
| 2283 | #endif |
| 2284 | |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2285 | if (!smp_found_config) |
| 2286 | disable_ioapic_support(); |
| 2287 | |
Thomas Gleixner | e714a91 | 2015-01-15 21:22:37 +0000 | [diff] [blame] | 2288 | default_setup_apic_routing(); |
Thomas Gleixner | 374aab3 | 2015-01-15 21:22:44 +0000 | [diff] [blame] | 2289 | apic_bsp_setup(true); |
Thomas Gleixner | e714a91 | 2015-01-15 21:22:37 +0000 | [diff] [blame] | 2290 | return 0; |
| 2291 | } |
| 2292 | |
Thomas Gleixner | 30b8b00 | 2015-01-15 21:22:39 +0000 | [diff] [blame] | 2293 | #ifdef CONFIG_UP_LATE_INIT |
| 2294 | void __init up_late_init(void) |
| 2295 | { |
| 2296 | APIC_init_uniprocessor(); |
| 2297 | } |
| 2298 | #endif |
| 2299 | |
Thomas Gleixner | e714a91 | 2015-01-15 21:22:37 +0000 | [diff] [blame] | 2300 | /* |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2301 | * Power management |
| 2302 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2303 | #ifdef CONFIG_PM |
| 2304 | |
| 2305 | static struct { |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 2306 | /* |
| 2307 | * 'active' is true if the local APIC was enabled by us and |
| 2308 | * not the BIOS; this signifies that we are also responsible |
| 2309 | * for disabling it before entering apm/acpi suspend |
| 2310 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2311 | int active; |
| 2312 | /* r/w apic fields */ |
| 2313 | unsigned int apic_id; |
| 2314 | unsigned int apic_taskpri; |
| 2315 | unsigned int apic_ldr; |
| 2316 | unsigned int apic_dfr; |
| 2317 | unsigned int apic_spiv; |
| 2318 | unsigned int apic_lvtt; |
| 2319 | unsigned int apic_lvtpc; |
| 2320 | unsigned int apic_lvt0; |
| 2321 | unsigned int apic_lvt1; |
| 2322 | unsigned int apic_lvterr; |
| 2323 | unsigned int apic_tmict; |
| 2324 | unsigned int apic_tdcr; |
| 2325 | unsigned int apic_thmr; |
Juergen Gross | 42baa25 | 2015-11-23 11:59:24 +0100 | [diff] [blame] | 2326 | unsigned int apic_cmci; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2327 | } apic_pm_state; |
| 2328 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2329 | static int lapic_suspend(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2330 | { |
| 2331 | unsigned long flags; |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2332 | int maxlvt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2333 | |
| 2334 | if (!apic_pm_state.active) |
| 2335 | return 0; |
| 2336 | |
Thomas Gleixner | 37e650c | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 2337 | maxlvt = lapic_get_maxlvt(); |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2338 | |
Suresh Siddha | 2d7a66d | 2008-07-11 14:24:19 -0700 | [diff] [blame] | 2339 | apic_pm_state.apic_id = apic_read(APIC_ID); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2340 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
| 2341 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); |
| 2342 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); |
| 2343 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); |
| 2344 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2345 | if (maxlvt >= 4) |
| 2346 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2347 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); |
| 2348 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); |
| 2349 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); |
| 2350 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); |
| 2351 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); |
Andi Kleen | 4efc067 | 2009-04-28 19:07:31 +0200 | [diff] [blame] | 2352 | #ifdef CONFIG_X86_THERMAL_VECTOR |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2353 | if (maxlvt >= 5) |
| 2354 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); |
| 2355 | #endif |
Juergen Gross | 42baa25 | 2015-11-23 11:59:24 +0100 | [diff] [blame] | 2356 | #ifdef CONFIG_X86_MCE_INTEL |
| 2357 | if (maxlvt >= 6) |
| 2358 | apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); |
| 2359 | #endif |
Cyrill Gorcunov | 24968cf | 2008-08-16 23:21:52 +0400 | [diff] [blame] | 2360 | |
Fernando Luis Vázquez Cao | 2b94ab2 | 2006-09-26 10:52:33 +0200 | [diff] [blame] | 2361 | local_irq_save(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2362 | disable_local_APIC(); |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 2363 | |
Joerg Roedel | 70733e0 | 2012-09-26 12:44:33 +0200 | [diff] [blame] | 2364 | irq_remapping_disable(); |
Suresh Siddha | fc1edaf | 2009-04-20 13:02:27 -0700 | [diff] [blame] | 2365 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2366 | local_irq_restore(flags); |
| 2367 | return 0; |
| 2368 | } |
| 2369 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2370 | static void lapic_resume(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2371 | { |
| 2372 | unsigned int l, h; |
| 2373 | unsigned long flags; |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 2374 | int maxlvt; |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2375 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2376 | if (!apic_pm_state.active) |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2377 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2378 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2379 | local_irq_save(flags); |
Joerg Roedel | 336224b | 2012-09-26 12:44:34 +0200 | [diff] [blame] | 2380 | |
| 2381 | /* |
| 2382 | * IO-APIC and PIC have their own resume routines. |
| 2383 | * We just mask them here to make sure the interrupt |
| 2384 | * subsystem is completely quiet while we enable x2apic |
| 2385 | * and interrupt-remapping. |
| 2386 | */ |
| 2387 | mask_ioapic_entries(); |
| 2388 | legacy_pic->mask_all(); |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2389 | |
Thomas Gleixner | 659006b | 2015-01-15 21:22:26 +0000 | [diff] [blame] | 2390 | if (x2apic_mode) { |
| 2391 | __x2apic_enable(); |
| 2392 | } else { |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2393 | /* |
| 2394 | * Make sure the APICBASE points to the right address |
| 2395 | * |
| 2396 | * FIXME! This will be wrong if we ever support suspend on |
| 2397 | * SMP! We'll need to do this as part of the CPU restore! |
| 2398 | */ |
Bryan O'Donoghue | cbf2829 | 2012-04-18 17:37:39 +0100 | [diff] [blame] | 2399 | if (boot_cpu_data.x86 >= 6) { |
| 2400 | rdmsr(MSR_IA32_APICBASE, l, h); |
| 2401 | l &= ~MSR_IA32_APICBASE_BASE; |
| 2402 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; |
| 2403 | wrmsr(MSR_IA32_APICBASE, l, h); |
| 2404 | } |
Yinghai Lu | d5e629a | 2008-08-17 21:12:27 -0700 | [diff] [blame] | 2405 | } |
Suresh Siddha | 6e1cb38 | 2008-07-10 11:16:58 -0700 | [diff] [blame] | 2406 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2407 | maxlvt = lapic_get_maxlvt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2408 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
| 2409 | apic_write(APIC_ID, apic_pm_state.apic_id); |
| 2410 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); |
| 2411 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); |
| 2412 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); |
| 2413 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); |
| 2414 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); |
| 2415 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); |
Juergen Gross | 42baa25 | 2015-11-23 11:59:24 +0100 | [diff] [blame] | 2416 | #ifdef CONFIG_X86_THERMAL_VECTOR |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2417 | if (maxlvt >= 5) |
| 2418 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); |
| 2419 | #endif |
Juergen Gross | 42baa25 | 2015-11-23 11:59:24 +0100 | [diff] [blame] | 2420 | #ifdef CONFIG_X86_MCE_INTEL |
| 2421 | if (maxlvt >= 6) |
| 2422 | apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); |
| 2423 | #endif |
Karsten Wiese | f990fff | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2424 | if (maxlvt >= 4) |
| 2425 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2426 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); |
| 2427 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); |
| 2428 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); |
| 2429 | apic_write(APIC_ESR, 0); |
| 2430 | apic_read(APIC_ESR); |
| 2431 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); |
| 2432 | apic_write(APIC_ESR, 0); |
| 2433 | apic_read(APIC_ESR); |
Cyrill Gorcunov | 92206c9 | 2008-08-16 23:21:51 +0400 | [diff] [blame] | 2434 | |
Joerg Roedel | 70733e0 | 2012-09-26 12:44:33 +0200 | [diff] [blame] | 2435 | irq_remapping_reenable(x2apic_mode); |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 2436 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2437 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2438 | } |
| 2439 | |
Cyrill Gorcunov | 274cfe5 | 2008-08-16 23:21:53 +0400 | [diff] [blame] | 2440 | /* |
| 2441 | * This device has no shutdown method - fully functioning local APICs |
| 2442 | * are needed on every CPU up until machine_halt/restart/poweroff. |
| 2443 | */ |
| 2444 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2445 | static struct syscore_ops lapic_syscore_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2446 | .resume = lapic_resume, |
| 2447 | .suspend = lapic_suspend, |
| 2448 | }; |
| 2449 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2450 | static void apic_pm_activate(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2451 | { |
| 2452 | apic_pm_state.active = 1; |
| 2453 | } |
| 2454 | |
| 2455 | static int __init init_lapic_sysfs(void) |
| 2456 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2457 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ |
Borislav Petkov | 93984fb | 2016-04-04 22:25:00 +0200 | [diff] [blame] | 2458 | if (boot_cpu_has(X86_FEATURE_APIC)) |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2459 | register_syscore_ops(&lapic_syscore_ops); |
Hiroshi Shimamoto | e83a5fd | 2008-01-30 13:32:35 +0100 | [diff] [blame] | 2460 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2461 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2462 | } |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 2463 | |
| 2464 | /* local apic needs to resume before other devices access its registers. */ |
| 2465 | core_initcall(init_lapic_sysfs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2466 | |
| 2467 | #else /* CONFIG_PM */ |
| 2468 | |
| 2469 | static void apic_pm_activate(void) { } |
| 2470 | |
| 2471 | #endif /* CONFIG_PM */ |
| 2472 | |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 2473 | #ifdef CONFIG_X86_64 |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2474 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2475 | static int multi_checked; |
| 2476 | static int multi; |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2477 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2478 | static int set_multi(const struct dmi_system_id *d) |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2479 | { |
| 2480 | if (multi) |
| 2481 | return 0; |
Cyrill Gorcunov | 6f0aced | 2009-05-01 23:54:25 +0400 | [diff] [blame] | 2482 | pr_info("APIC: %s detected, Multi Chassis\n", d->ident); |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2483 | multi = 1; |
| 2484 | return 0; |
| 2485 | } |
| 2486 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2487 | static const struct dmi_system_id multi_dmi_table[] = { |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2488 | { |
| 2489 | .callback = set_multi, |
| 2490 | .ident = "IBM System Summit2", |
| 2491 | .matches = { |
| 2492 | DMI_MATCH(DMI_SYS_VENDOR, "IBM"), |
| 2493 | DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), |
| 2494 | }, |
| 2495 | }, |
| 2496 | {} |
| 2497 | }; |
| 2498 | |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2499 | static void dmi_check_multi(void) |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2500 | { |
| 2501 | if (multi_checked) |
| 2502 | return; |
| 2503 | |
| 2504 | dmi_check_system(multi_dmi_table); |
| 2505 | multi_checked = 1; |
| 2506 | } |
| 2507 | |
| 2508 | /* |
| 2509 | * apic_is_clustered_box() -- Check if we can expect good TSC |
| 2510 | * |
| 2511 | * Thus far, the major user of this is IBM's Summit2 series: |
| 2512 | * Clustered boxes may have unsynced TSC problems if they are |
| 2513 | * multi-chassis. |
| 2514 | * Use DMI to check them |
| 2515 | */ |
Paul Gortmaker | 148f9bb | 2013-06-18 18:23:59 -0400 | [diff] [blame] | 2516 | int apic_is_clustered_box(void) |
Yinghai Lu | e0e4214 | 2009-04-26 23:39:38 -0700 | [diff] [blame] | 2517 | { |
| 2518 | dmi_check_multi(); |
Oren Twaig | 411cf9e | 2014-06-29 13:01:08 +0300 | [diff] [blame] | 2519 | return multi; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2520 | } |
Yinghai Lu | f28c0ae | 2008-08-24 02:01:49 -0700 | [diff] [blame] | 2521 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2522 | |
| 2523 | /* |
Thomas Gleixner | 0e078e2 | 2008-01-30 13:30:20 +0100 | [diff] [blame] | 2524 | * APIC command line parameters |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2525 | */ |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2526 | static int __init setup_disableapic(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2527 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2528 | disable_apic = 1; |
Yinghai Lu | 9175fc0 | 2008-07-21 01:38:14 -0700 | [diff] [blame] | 2529 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2530 | return 0; |
| 2531 | } |
| 2532 | early_param("disableapic", setup_disableapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2533 | |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2534 | /* same as disableapic, for compatibility */ |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2535 | static int __init setup_nolapic(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2536 | { |
Cyrill Gorcunov | 789fa73 | 2008-08-18 20:46:01 +0400 | [diff] [blame] | 2537 | return setup_disableapic(arg); |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2538 | } |
Andi Kleen | 2c8c0e6 | 2006-09-26 10:52:32 +0200 | [diff] [blame] | 2539 | early_param("nolapic", setup_nolapic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2540 | |
Linus Torvalds | 2e7c283 | 2007-03-23 11:32:31 -0700 | [diff] [blame] | 2541 | static int __init parse_lapic_timer_c2_ok(char *arg) |
| 2542 | { |
| 2543 | local_apic_timer_c2_ok = 1; |
| 2544 | return 0; |
| 2545 | } |
| 2546 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); |
| 2547 | |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2548 | static int __init parse_disable_apic_timer(char *arg) |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2549 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2550 | disable_apic_timer = 1; |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2551 | return 0; |
Thomas Gleixner | 6935d1f | 2007-07-21 17:10:17 +0200 | [diff] [blame] | 2552 | } |
Cyrill Gorcunov | 36fef09 | 2008-08-15 13:51:20 +0200 | [diff] [blame] | 2553 | early_param("noapictimer", parse_disable_apic_timer); |
| 2554 | |
| 2555 | static int __init parse_nolapic_timer(char *arg) |
| 2556 | { |
| 2557 | disable_apic_timer = 1; |
| 2558 | return 0; |
| 2559 | } |
| 2560 | early_param("nolapic_timer", parse_nolapic_timer); |
Andi Kleen | 73dea47 | 2006-02-03 21:50:50 +0100 | [diff] [blame] | 2561 | |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2562 | static int __init apic_set_verbosity(char *arg) |
| 2563 | { |
| 2564 | if (!arg) { |
| 2565 | #ifdef CONFIG_X86_64 |
| 2566 | skip_ioapic_setup = 0; |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2567 | return 0; |
| 2568 | #endif |
| 2569 | return -EINVAL; |
| 2570 | } |
| 2571 | |
| 2572 | if (strcmp("debug", arg) == 0) |
| 2573 | apic_verbosity = APIC_DEBUG; |
| 2574 | else if (strcmp("verbose", arg) == 0) |
| 2575 | apic_verbosity = APIC_VERBOSE; |
| 2576 | else { |
Cyrill Gorcunov | ba21ebb | 2008-11-10 09:16:41 +0100 | [diff] [blame] | 2577 | pr_warning("APIC Verbosity level %s not recognised" |
Cyrill Gorcunov | 79af9be | 2008-08-18 20:46:00 +0400 | [diff] [blame] | 2578 | " use apic=verbose or apic=debug\n", arg); |
| 2579 | return -EINVAL; |
| 2580 | } |
| 2581 | |
| 2582 | return 0; |
| 2583 | } |
| 2584 | early_param("apic", apic_set_verbosity); |
| 2585 | |
Yinghai Lu | 1e934dd | 2008-02-22 13:37:26 -0800 | [diff] [blame] | 2586 | static int __init lapic_insert_resource(void) |
| 2587 | { |
| 2588 | if (!apic_phys) |
| 2589 | return -1; |
| 2590 | |
| 2591 | /* Put local APIC into the resource map. */ |
| 2592 | lapic_resource.start = apic_phys; |
| 2593 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; |
| 2594 | insert_resource(&iomem_resource, &lapic_resource); |
| 2595 | |
| 2596 | return 0; |
| 2597 | } |
| 2598 | |
| 2599 | /* |
| 2600 | * need call insert after e820_reserve_resources() |
| 2601 | * that is using request_resource |
| 2602 | */ |
| 2603 | late_initcall(lapic_insert_resource); |
HATAYAMA Daisuke | 151e0c7 | 2014-01-15 15:44:58 +0900 | [diff] [blame] | 2604 | |
| 2605 | static int __init apic_set_disabled_cpu_apicid(char *arg) |
| 2606 | { |
| 2607 | if (!arg || !get_option(&arg, &disabled_cpu_apicid)) |
| 2608 | return -EINVAL; |
| 2609 | |
| 2610 | return 0; |
| 2611 | } |
| 2612 | early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); |
Hidehiro Kawai | b7c4948 | 2015-12-14 11:19:12 +0100 | [diff] [blame] | 2613 | |
| 2614 | static int __init apic_set_extnmi(char *arg) |
| 2615 | { |
| 2616 | if (!arg) |
| 2617 | return -EINVAL; |
| 2618 | |
| 2619 | if (!strncmp("all", arg, 3)) |
| 2620 | apic_extnmi = APIC_EXTNMI_ALL; |
| 2621 | else if (!strncmp("none", arg, 4)) |
| 2622 | apic_extnmi = APIC_EXTNMI_NONE; |
| 2623 | else if (!strncmp("bsp", arg, 3)) |
| 2624 | apic_extnmi = APIC_EXTNMI_BSP; |
| 2625 | else { |
| 2626 | pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); |
| 2627 | return -EINVAL; |
| 2628 | } |
| 2629 | |
| 2630 | return 0; |
| 2631 | } |
| 2632 | early_param("apic_extnmi", apic_set_extnmi); |