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Boris BREZILLON1a748d22013-10-11 10:48:26 +02001/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
Boris Brezillon1bdf0232014-09-07 08:14:29 +020015#include <linux/mfd/syscon.h>
16#include <linux/regmap.h>
Boris BREZILLON1a748d22013-10-11 10:48:26 +020017
18#include "pmc.h"
19
20#define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
21
22struct clk_plldiv {
23 struct clk_hw hw;
Boris Brezillon1bdf0232014-09-07 08:14:29 +020024 struct regmap *regmap;
Boris BREZILLON1a748d22013-10-11 10:48:26 +020025};
26
27static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
28 unsigned long parent_rate)
29{
30 struct clk_plldiv *plldiv = to_clk_plldiv(hw);
Boris Brezillon1bdf0232014-09-07 08:14:29 +020031 unsigned int mckr;
Boris BREZILLON1a748d22013-10-11 10:48:26 +020032
Boris Brezillon1bdf0232014-09-07 08:14:29 +020033 regmap_read(plldiv->regmap, AT91_PMC_MCKR, &mckr);
34
35 if (mckr & AT91_PMC_PLLADIV2)
Boris BREZILLON1a748d22013-10-11 10:48:26 +020036 return parent_rate / 2;
37
38 return parent_rate;
39}
40
41static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
42 unsigned long *parent_rate)
43{
44 unsigned long div;
45
46 if (rate > *parent_rate)
47 return *parent_rate;
48 div = *parent_rate / 2;
49 if (rate < div)
50 return div;
51
52 if (rate - div < *parent_rate - rate)
53 return div;
54
55 return *parent_rate;
56}
57
58static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long parent_rate)
60{
61 struct clk_plldiv *plldiv = to_clk_plldiv(hw);
Boris BREZILLON1a748d22013-10-11 10:48:26 +020062
Boris Brezillon1bdf0232014-09-07 08:14:29 +020063 if ((parent_rate != rate) && (parent_rate / 2 != rate))
Boris BREZILLON1a748d22013-10-11 10:48:26 +020064 return -EINVAL;
65
Boris Brezillon1bdf0232014-09-07 08:14:29 +020066 regmap_update_bits(plldiv->regmap, AT91_PMC_MCKR, AT91_PMC_PLLADIV2,
67 parent_rate != rate ? AT91_PMC_PLLADIV2 : 0);
Boris BREZILLON1a748d22013-10-11 10:48:26 +020068
69 return 0;
70}
71
72static const struct clk_ops plldiv_ops = {
73 .recalc_rate = clk_plldiv_recalc_rate,
74 .round_rate = clk_plldiv_round_rate,
75 .set_rate = clk_plldiv_set_rate,
76};
77
78static struct clk * __init
Boris Brezillon1bdf0232014-09-07 08:14:29 +020079at91_clk_register_plldiv(struct regmap *regmap, const char *name,
Boris BREZILLON1a748d22013-10-11 10:48:26 +020080 const char *parent_name)
81{
82 struct clk_plldiv *plldiv;
83 struct clk *clk = NULL;
84 struct clk_init_data init;
85
86 plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
87 if (!plldiv)
88 return ERR_PTR(-ENOMEM);
89
90 init.name = name;
91 init.ops = &plldiv_ops;
92 init.parent_names = parent_name ? &parent_name : NULL;
93 init.num_parents = parent_name ? 1 : 0;
94 init.flags = CLK_SET_RATE_GATE;
95
96 plldiv->hw.init = &init;
Boris Brezillon1bdf0232014-09-07 08:14:29 +020097 plldiv->regmap = regmap;
Boris BREZILLON1a748d22013-10-11 10:48:26 +020098
99 clk = clk_register(NULL, &plldiv->hw);
100
101 if (IS_ERR(clk))
102 kfree(plldiv);
103
104 return clk;
105}
106
107static void __init
Boris Brezillon1bdf0232014-09-07 08:14:29 +0200108of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
Boris BREZILLON1a748d22013-10-11 10:48:26 +0200109{
110 struct clk *clk;
111 const char *parent_name;
112 const char *name = np->name;
Boris Brezillon1bdf0232014-09-07 08:14:29 +0200113 struct regmap *regmap;
Boris BREZILLON1a748d22013-10-11 10:48:26 +0200114
115 parent_name = of_clk_get_parent_name(np, 0);
116
117 of_property_read_string(np, "clock-output-names", &name);
118
Boris Brezillon1bdf0232014-09-07 08:14:29 +0200119 regmap = syscon_node_to_regmap(of_get_parent(np));
120 if (IS_ERR(regmap))
121 return;
Boris BREZILLON1a748d22013-10-11 10:48:26 +0200122
Boris Brezillon1bdf0232014-09-07 08:14:29 +0200123 clk = at91_clk_register_plldiv(regmap, name, parent_name);
Boris BREZILLON1a748d22013-10-11 10:48:26 +0200124 if (IS_ERR(clk))
125 return;
126
127 of_clk_add_provider(np, of_clk_src_simple_get, clk);
128 return;
129}
Boris Brezillon1bdf0232014-09-07 08:14:29 +0200130CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
131 of_at91sam9x5_clk_plldiv_setup);