Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 1 | /* |
| 2 | * H8S2678 clock driver |
| 3 | * |
| 4 | * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp> |
| 5 | */ |
| 6 | |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 7 | #include <linux/clk-provider.h> |
| 8 | #include <linux/err.h> |
| 9 | #include <linux/device.h> |
| 10 | #include <linux/of_address.h> |
Guenter Roeck | ac0e137 | 2015-08-31 20:27:32 -0700 | [diff] [blame] | 11 | #include <linux/slab.h> |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 12 | |
| 13 | static DEFINE_SPINLOCK(clklock); |
| 14 | |
| 15 | #define MAX_FREQ 33333333 |
| 16 | #define MIN_FREQ 8000000 |
| 17 | |
| 18 | struct pll_clock { |
| 19 | struct clk_hw hw; |
| 20 | void __iomem *sckcr; |
| 21 | void __iomem *pllcr; |
| 22 | }; |
| 23 | |
| 24 | #define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw) |
| 25 | |
| 26 | static unsigned long pll_recalc_rate(struct clk_hw *hw, |
| 27 | unsigned long parent_rate) |
| 28 | { |
| 29 | struct pll_clock *pll_clock = to_pll_clock(hw); |
Stephen Boyd | 006cb8b | 2015-07-13 17:06:53 -0700 | [diff] [blame] | 30 | int mul = 1 << (readb(pll_clock->pllcr) & 3); |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 31 | |
| 32 | return parent_rate * mul; |
| 33 | } |
| 34 | |
| 35 | static long pll_round_rate(struct clk_hw *hw, unsigned long rate, |
| 36 | unsigned long *prate) |
| 37 | { |
| 38 | int i, m = -1; |
| 39 | long offset[3]; |
| 40 | |
| 41 | if (rate > MAX_FREQ) |
| 42 | rate = MAX_FREQ; |
| 43 | if (rate < MIN_FREQ) |
| 44 | rate = MIN_FREQ; |
| 45 | |
| 46 | for (i = 0; i < 3; i++) |
| 47 | offset[i] = abs(rate - (*prate * (1 << i))); |
| 48 | for (i = 0; i < 3; i++) |
| 49 | if (m < 0) |
| 50 | m = i; |
| 51 | else |
| 52 | m = (offset[i] < offset[m])?i:m; |
| 53 | |
| 54 | return *prate * (1 << m); |
| 55 | } |
| 56 | |
| 57 | static int pll_set_rate(struct clk_hw *hw, unsigned long rate, |
| 58 | unsigned long parent_rate) |
| 59 | { |
| 60 | int pll; |
| 61 | unsigned char val; |
| 62 | unsigned long flags; |
| 63 | struct pll_clock *pll_clock = to_pll_clock(hw); |
| 64 | |
| 65 | pll = ((rate / parent_rate) / 2) & 0x03; |
| 66 | spin_lock_irqsave(&clklock, flags); |
Stephen Boyd | 006cb8b | 2015-07-13 17:06:53 -0700 | [diff] [blame] | 67 | val = readb(pll_clock->sckcr); |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 68 | val |= 0x08; |
Stephen Boyd | 006cb8b | 2015-07-13 17:06:53 -0700 | [diff] [blame] | 69 | writeb(val, pll_clock->sckcr); |
| 70 | val = readb(pll_clock->pllcr); |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 71 | val &= ~0x03; |
| 72 | val |= pll; |
Stephen Boyd | 006cb8b | 2015-07-13 17:06:53 -0700 | [diff] [blame] | 73 | writeb(val, pll_clock->pllcr); |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 74 | spin_unlock_irqrestore(&clklock, flags); |
| 75 | return 0; |
| 76 | } |
| 77 | |
| 78 | static const struct clk_ops pll_ops = { |
| 79 | .recalc_rate = pll_recalc_rate, |
| 80 | .round_rate = pll_round_rate, |
| 81 | .set_rate = pll_set_rate, |
| 82 | }; |
| 83 | |
| 84 | static void __init h8s2678_pll_clk_setup(struct device_node *node) |
| 85 | { |
Stephen Boyd | ebf3f9a | 2016-02-19 17:36:51 -0800 | [diff] [blame] | 86 | unsigned int num_parents; |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 87 | struct clk *clk; |
| 88 | const char *clk_name = node->name; |
| 89 | const char *parent_name; |
| 90 | struct pll_clock *pll_clock; |
| 91 | struct clk_init_data init; |
| 92 | |
| 93 | num_parents = of_clk_get_parent_count(node); |
Stephen Boyd | ebf3f9a | 2016-02-19 17:36:51 -0800 | [diff] [blame] | 94 | if (!num_parents) { |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 95 | pr_err("%s: no parent found", clk_name); |
| 96 | return; |
| 97 | } |
| 98 | |
| 99 | |
Stephen Boyd | 9298f02 | 2015-07-13 16:54:04 -0700 | [diff] [blame] | 100 | pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL); |
| 101 | if (!pll_clock) |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 102 | return; |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 103 | |
| 104 | pll_clock->sckcr = of_iomap(node, 0); |
| 105 | if (pll_clock->sckcr == NULL) { |
| 106 | pr_err("%s: failed to map divide register", clk_name); |
Dan Carpenter | ded515a | 2015-05-14 13:05:00 +0300 | [diff] [blame] | 107 | goto free_clock; |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | pll_clock->pllcr = of_iomap(node, 1); |
| 111 | if (pll_clock->pllcr == NULL) { |
| 112 | pr_err("%s: failed to map multiply register", clk_name); |
Dan Carpenter | ded515a | 2015-05-14 13:05:00 +0300 | [diff] [blame] | 113 | goto unmap_sckcr; |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 114 | } |
| 115 | |
| 116 | parent_name = of_clk_get_parent_name(node, 0); |
| 117 | init.name = clk_name; |
| 118 | init.ops = &pll_ops; |
| 119 | init.flags = CLK_IS_BASIC; |
| 120 | init.parent_names = &parent_name; |
| 121 | init.num_parents = 1; |
| 122 | pll_clock->hw.init = &init; |
| 123 | |
| 124 | clk = clk_register(NULL, &pll_clock->hw); |
Dan Carpenter | ded515a | 2015-05-14 13:05:00 +0300 | [diff] [blame] | 125 | if (IS_ERR(clk)) { |
| 126 | pr_err("%s: failed to register %s div clock (%ld)\n", |
| 127 | __func__, clk_name, PTR_ERR(clk)); |
| 128 | goto unmap_pllcr; |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 129 | } |
Dan Carpenter | ded515a | 2015-05-14 13:05:00 +0300 | [diff] [blame] | 130 | |
| 131 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 132 | return; |
| 133 | |
| 134 | unmap_pllcr: |
| 135 | iounmap(pll_clock->pllcr); |
| 136 | unmap_sckcr: |
| 137 | iounmap(pll_clock->sckcr); |
| 138 | free_clock: |
| 139 | kfree(pll_clock); |
Yoshinori Sato | 7b5bb89 | 2015-05-08 23:31:57 +0900 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock", |
| 143 | h8s2678_pll_clk_setup); |