Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _CORESIGHT_PRIV_H |
| 14 | #define _CORESIGHT_PRIV_H |
| 15 | |
| 16 | #include <linux/bitops.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/coresight.h> |
| 19 | |
| 20 | /* |
| 21 | * Coresight management registers (0xf00-0xfcc) |
| 22 | * 0xfa0 - 0xfa4: Management registers in PFTv1.0 |
| 23 | * Trace registers in PFTv1.1 |
| 24 | */ |
| 25 | #define CORESIGHT_ITCTRL 0xf00 |
| 26 | #define CORESIGHT_CLAIMSET 0xfa0 |
| 27 | #define CORESIGHT_CLAIMCLR 0xfa4 |
| 28 | #define CORESIGHT_LAR 0xfb0 |
| 29 | #define CORESIGHT_LSR 0xfb4 |
| 30 | #define CORESIGHT_AUTHSTATUS 0xfb8 |
| 31 | #define CORESIGHT_DEVID 0xfc8 |
| 32 | #define CORESIGHT_DEVTYPE 0xfcc |
| 33 | |
| 34 | #define TIMEOUT_US 100 |
| 35 | #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) |
| 36 | |
Mathieu Poirier | 2127154 | 2016-02-17 17:51:56 -0700 | [diff] [blame] | 37 | #define ETM_MODE_EXCL_KERN BIT(30) |
| 38 | #define ETM_MODE_EXCL_USER BIT(31) |
| 39 | |
Mathieu Poirier | 154f3520 | 2016-04-05 11:53:50 -0600 | [diff] [blame] | 40 | #define coresight_simple_func(type, name, offset) \ |
| 41 | static ssize_t name##_show(struct device *_dev, \ |
| 42 | struct device_attribute *attr, char *buf) \ |
| 43 | { \ |
| 44 | type *drvdata = dev_get_drvdata(_dev->parent); \ |
| 45 | return scnprintf(buf, PAGE_SIZE, "0x%x\n", \ |
| 46 | readl_relaxed(drvdata->base + offset)); \ |
| 47 | } \ |
| 48 | static DEVICE_ATTR_RO(name) |
| 49 | |
Mathieu Poirier | 22fd532 | 2016-02-17 17:51:52 -0700 | [diff] [blame] | 50 | enum cs_mode { |
| 51 | CS_MODE_DISABLED, |
| 52 | CS_MODE_SYSFS, |
| 53 | CS_MODE_PERF, |
| 54 | }; |
| 55 | |
Mathieu Poirier | a02e81f | 2016-05-03 11:33:58 -0600 | [diff] [blame] | 56 | /** |
| 57 | * struct cs_buffer - keep track of a recording session' specifics |
| 58 | * @cur: index of the current buffer |
| 59 | * @nr_pages: max number of pages granted to us |
| 60 | * @offset: offset within the current buffer |
| 61 | * @data_size: how much we collected in this run |
| 62 | * @lost: other than zero if we had a HW buffer wrap around |
| 63 | * @snapshot: is this run in snapshot mode |
| 64 | * @data_pages: a handle the ring buffer |
| 65 | */ |
| 66 | struct cs_buffers { |
| 67 | unsigned int cur; |
| 68 | unsigned int nr_pages; |
| 69 | unsigned long offset; |
| 70 | local_t data_size; |
| 71 | local_t lost; |
| 72 | bool snapshot; |
| 73 | void **data_pages; |
| 74 | }; |
| 75 | |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 76 | static inline void CS_LOCK(void __iomem *addr) |
| 77 | { |
| 78 | do { |
| 79 | /* Wait for things to settle */ |
| 80 | mb(); |
| 81 | writel_relaxed(0x0, addr + CORESIGHT_LAR); |
| 82 | } while (0); |
| 83 | } |
| 84 | |
| 85 | static inline void CS_UNLOCK(void __iomem *addr) |
| 86 | { |
| 87 | do { |
| 88 | writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR); |
Pankaj Dubey | 84b763d | 2014-11-13 14:12:47 +0530 | [diff] [blame] | 89 | /* Make sure everyone has seen this */ |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 90 | mb(); |
| 91 | } while (0); |
| 92 | } |
| 93 | |
Mathieu Poirier | b3e9440 | 2016-02-17 17:51:45 -0700 | [diff] [blame] | 94 | void coresight_disable_path(struct list_head *path); |
Mathieu Poirier | e827d45 | 2016-02-17 17:51:59 -0700 | [diff] [blame] | 95 | int coresight_enable_path(struct list_head *path, u32 mode); |
Mathieu Poirier | b6404e2 | 2016-02-17 17:51:46 -0700 | [diff] [blame] | 96 | struct coresight_device *coresight_get_sink(struct list_head *path); |
Mathieu Poirier | b3e9440 | 2016-02-17 17:51:45 -0700 | [diff] [blame] | 97 | struct list_head *coresight_build_path(struct coresight_device *csdev); |
| 98 | void coresight_release_path(struct list_head *path); |
| 99 | |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 100 | #ifdef CONFIG_CORESIGHT_SOURCE_ETM3X |
| 101 | extern int etm_readl_cp14(u32 off, unsigned int *val); |
| 102 | extern int etm_writel_cp14(u32 off, u32 val); |
| 103 | #else |
| 104 | static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } |
Kaixu Xia | 5fb31cd | 2015-01-26 09:22:25 -0700 | [diff] [blame] | 105 | static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } |
Pratik Patel | a06ae86 | 2014-11-03 11:07:35 -0700 | [diff] [blame] | 106 | #endif |
| 107 | |
| 108 | #endif |