Jacob Keller | 8664109 | 2016-04-07 08:21:21 -0700 | [diff] [blame] | 1 | /* Intel(R) Ethernet Switch Host Interface Driver |
Jacob Keller | 9de6a1a | 2016-04-01 16:17:31 -0700 | [diff] [blame] | 2 | * Copyright(c) 2013 - 2016 Intel Corporation. |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * The full GNU General Public License is included in this distribution in |
| 14 | * the file called "COPYING". |
| 15 | * |
| 16 | * Contact Information: |
| 17 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 18 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 19 | */ |
| 20 | |
| 21 | #include "fm10k_pf.h" |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 22 | #include "fm10k_vf.h" |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 23 | |
| 24 | /** |
| 25 | * fm10k_reset_hw_pf - PF hardware reset |
| 26 | * @hw: pointer to hardware structure |
| 27 | * |
| 28 | * This function should return the hardware to a state similar to the |
| 29 | * one it is in after being powered on. |
| 30 | **/ |
| 31 | static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw) |
| 32 | { |
| 33 | s32 err; |
| 34 | u32 reg; |
| 35 | u16 i; |
| 36 | |
| 37 | /* Disable interrupts */ |
| 38 | fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL)); |
| 39 | |
| 40 | /* Lock ITR2 reg 0 into itself and disable interrupt moderation */ |
| 41 | fm10k_write_reg(hw, FM10K_ITR2(0), 0); |
| 42 | fm10k_write_reg(hw, FM10K_INT_CTRL, 0); |
| 43 | |
| 44 | /* We assume here Tx and Rx queue 0 are owned by the PF */ |
| 45 | |
| 46 | /* Shut off VF access to their queues forcing them to queue 0 */ |
| 47 | for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) { |
| 48 | fm10k_write_reg(hw, FM10K_TQMAP(i), 0); |
| 49 | fm10k_write_reg(hw, FM10K_RQMAP(i), 0); |
| 50 | } |
| 51 | |
| 52 | /* shut down all rings */ |
| 53 | err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES); |
Jacob Keller | ce33624 | 2016-06-07 16:08:47 -0700 | [diff] [blame] | 54 | if (err == FM10K_ERR_REQUESTS_PENDING) { |
| 55 | hw->mac.reset_while_pending++; |
| 56 | goto force_reset; |
| 57 | } else if (err) { |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 58 | return err; |
Jacob Keller | ce33624 | 2016-06-07 16:08:47 -0700 | [diff] [blame] | 59 | } |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 60 | |
| 61 | /* Verify that DMA is no longer active */ |
| 62 | reg = fm10k_read_reg(hw, FM10K_DMA_CTRL); |
| 63 | if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE)) |
| 64 | return FM10K_ERR_DMA_PENDING; |
| 65 | |
Jacob Keller | ce33624 | 2016-06-07 16:08:47 -0700 | [diff] [blame] | 66 | force_reset: |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 67 | /* Inititate data path reset */ |
Jacob Keller | ce33624 | 2016-06-07 16:08:47 -0700 | [diff] [blame] | 68 | reg = FM10K_DMA_CTRL_DATAPATH_RESET; |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 69 | fm10k_write_reg(hw, FM10K_DMA_CTRL, reg); |
| 70 | |
| 71 | /* Flush write and allow 100us for reset to complete */ |
| 72 | fm10k_write_flush(hw); |
| 73 | udelay(FM10K_RESET_TIMEOUT); |
| 74 | |
Ngai-Mint Kwan | 5e93cba | 2016-06-07 16:08:46 -0700 | [diff] [blame] | 75 | /* Reset mailbox global interrupts */ |
| 76 | reg = FM10K_MBX_GLOBAL_REQ_INTERRUPT | FM10K_MBX_GLOBAL_ACK_INTERRUPT; |
| 77 | fm10k_write_reg(hw, FM10K_GMBX, reg); |
| 78 | |
Jacob Keller | ce33624 | 2016-06-07 16:08:47 -0700 | [diff] [blame] | 79 | /* Verify we made it out of reset */ |
| 80 | reg = fm10k_read_reg(hw, FM10K_IP); |
| 81 | if (!(reg & FM10K_IP_NOTINRESET)) |
| 82 | return FM10K_ERR_RESET_FAILED; |
| 83 | |
| 84 | return 0; |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | /** |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 88 | * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support |
| 89 | * @hw: pointer to hardware structure |
| 90 | * |
| 91 | * Looks at the ARI hierarchy bit to determine whether ARI is supported or not. |
| 92 | **/ |
| 93 | static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw) |
| 94 | { |
| 95 | u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL); |
| 96 | |
| 97 | return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI); |
| 98 | } |
| 99 | |
| 100 | /** |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 101 | * fm10k_init_hw_pf - PF hardware initialization |
| 102 | * @hw: pointer to hardware structure |
| 103 | * |
| 104 | **/ |
| 105 | static s32 fm10k_init_hw_pf(struct fm10k_hw *hw) |
| 106 | { |
| 107 | u32 dma_ctrl, txqctl; |
| 108 | u16 i; |
| 109 | |
| 110 | /* Establish default VSI as valid */ |
| 111 | fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0); |
| 112 | fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default), |
| 113 | FM10K_DGLORTMAP_ANY); |
| 114 | |
| 115 | /* Invalidate all other GLORT entries */ |
| 116 | for (i = 1; i < FM10K_DGLORT_COUNT; i++) |
| 117 | fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE); |
| 118 | |
| 119 | /* reset ITR2(0) to point to itself */ |
| 120 | fm10k_write_reg(hw, FM10K_ITR2(0), 0); |
| 121 | |
| 122 | /* reset VF ITR2(0) to point to 0 avoid PF registers */ |
| 123 | fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0); |
| 124 | |
| 125 | /* loop through all PF ITR2 registers pointing them to the previous */ |
| 126 | for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++) |
| 127 | fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); |
| 128 | |
| 129 | /* Enable interrupt moderator if not already enabled */ |
| 130 | fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); |
| 131 | |
| 132 | /* compute the default txqctl configuration */ |
| 133 | txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW | |
| 134 | (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT); |
| 135 | |
| 136 | for (i = 0; i < FM10K_MAX_QUEUES; i++) { |
| 137 | /* configure rings for 256 Queue / 32 Descriptor cache mode */ |
| 138 | fm10k_write_reg(hw, FM10K_TQDLOC(i), |
| 139 | (i * FM10K_TQDLOC_BASE_32_DESC) | |
| 140 | FM10K_TQDLOC_SIZE_32_DESC); |
| 141 | fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); |
| 142 | |
| 143 | /* configure rings to provide TPH processing hints */ |
| 144 | fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i), |
| 145 | FM10K_TPH_TXCTRL_DESC_TPHEN | |
| 146 | FM10K_TPH_TXCTRL_DESC_RROEN | |
| 147 | FM10K_TPH_TXCTRL_DESC_WROEN | |
| 148 | FM10K_TPH_TXCTRL_DATA_RROEN); |
| 149 | fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i), |
| 150 | FM10K_TPH_RXCTRL_DESC_TPHEN | |
| 151 | FM10K_TPH_RXCTRL_DESC_RROEN | |
| 152 | FM10K_TPH_RXCTRL_DATA_WROEN | |
| 153 | FM10K_TPH_RXCTRL_HDR_WROEN); |
| 154 | } |
| 155 | |
Jacob Keller | 20076fa | 2015-10-16 10:57:05 -0700 | [diff] [blame] | 156 | /* set max hold interval to align with 1.024 usec in all modes and |
| 157 | * store ITR scale |
| 158 | */ |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 159 | switch (hw->bus.speed) { |
| 160 | case fm10k_bus_speed_2500: |
| 161 | dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1; |
Jacob Keller | 20076fa | 2015-10-16 10:57:05 -0700 | [diff] [blame] | 162 | hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN1; |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 163 | break; |
| 164 | case fm10k_bus_speed_5000: |
| 165 | dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2; |
Jacob Keller | 20076fa | 2015-10-16 10:57:05 -0700 | [diff] [blame] | 166 | hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN2; |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 167 | break; |
| 168 | case fm10k_bus_speed_8000: |
| 169 | dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3; |
Jacob Keller | 20076fa | 2015-10-16 10:57:05 -0700 | [diff] [blame] | 170 | hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3; |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 171 | break; |
| 172 | default: |
| 173 | dma_ctrl = 0; |
Jacob Keller | 20076fa | 2015-10-16 10:57:05 -0700 | [diff] [blame] | 174 | /* just in case, assume Gen3 ITR scale */ |
| 175 | hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3; |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 176 | break; |
| 177 | } |
| 178 | |
| 179 | /* Configure TSO flags */ |
| 180 | fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW); |
| 181 | fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI); |
| 182 | |
| 183 | /* Enable DMA engine |
| 184 | * Set Rx Descriptor size to 32 |
| 185 | * Set Minimum MSS to 64 |
| 186 | * Set Maximum number of Rx queues to 256 / 32 Descriptor |
| 187 | */ |
| 188 | dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE | |
| 189 | FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 | |
| 190 | FM10K_DMA_CTRL_32_DESC; |
| 191 | |
| 192 | fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl); |
| 193 | |
| 194 | /* record maximum queue count, we limit ourselves to 128 */ |
| 195 | hw->mac.max_queues = FM10K_MAX_QUEUES_PF; |
| 196 | |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 197 | /* We support either 64 VFs or 7 VFs depending on if we have ARI */ |
| 198 | hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7; |
| 199 | |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 200 | return 0; |
| 201 | } |
| 202 | |
| 203 | /** |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 204 | * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table |
| 205 | * @hw: pointer to hardware structure |
| 206 | * @vid: VLAN ID to add to table |
| 207 | * @vsi: Index indicating VF ID or PF ID in table |
| 208 | * @set: Indicates if this is a set or clear operation |
| 209 | * |
| 210 | * This function adds or removes the corresponding VLAN ID from the VLAN |
| 211 | * filter table for the corresponding function. In addition to the |
| 212 | * standard set/clear that supports one bit a multi-bit write is |
| 213 | * supported to set 64 bits at a time. |
| 214 | **/ |
| 215 | static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set) |
| 216 | { |
| 217 | u32 vlan_table, reg, mask, bit, len; |
| 218 | |
| 219 | /* verify the VSI index is valid */ |
| 220 | if (vsi > FM10K_VLAN_TABLE_VSI_MAX) |
| 221 | return FM10K_ERR_PARAM; |
| 222 | |
| 223 | /* VLAN multi-bit write: |
| 224 | * The multi-bit write has several parts to it. |
Jacob Keller | d057d9a | 2016-04-01 16:17:36 -0700 | [diff] [blame] | 225 | * 24 16 8 0 |
| 226 | * 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 227 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 228 | * | RSVD0 | Length |C|RSVD0| VLAN ID | |
| 229 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 230 | * |
| 231 | * VLAN ID: Vlan Starting value |
| 232 | * RSVD0: Reserved section, must be 0 |
| 233 | * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message) |
| 234 | * Length: Number of times to repeat the bit being set |
| 235 | */ |
| 236 | len = vid >> 16; |
| 237 | vid = (vid << 17) >> 17; |
| 238 | |
| 239 | /* verify the reserved 0 fields are 0 */ |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 240 | if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX) |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 241 | return FM10K_ERR_PARAM; |
| 242 | |
| 243 | /* Loop through the table updating all required VLANs */ |
| 244 | for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32; |
| 245 | len < FM10K_VLAN_TABLE_VID_MAX; |
| 246 | len -= 32 - bit, reg++, bit = 0) { |
| 247 | /* record the initial state of the register */ |
| 248 | vlan_table = fm10k_read_reg(hw, reg); |
| 249 | |
| 250 | /* truncate mask if we are at the start or end of the run */ |
| 251 | mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit; |
| 252 | |
| 253 | /* make necessary modifications to the register */ |
| 254 | mask &= set ? ~vlan_table : vlan_table; |
| 255 | if (mask) |
| 256 | fm10k_write_reg(hw, reg, vlan_table ^ mask); |
| 257 | } |
| 258 | |
| 259 | return 0; |
| 260 | } |
| 261 | |
| 262 | /** |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 263 | * fm10k_read_mac_addr_pf - Read device MAC address |
| 264 | * @hw: pointer to the HW structure |
| 265 | * |
| 266 | * Reads the device MAC address from the SM_AREA and stores the value. |
| 267 | **/ |
| 268 | static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw) |
| 269 | { |
| 270 | u8 perm_addr[ETH_ALEN]; |
| 271 | u32 serial_num; |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 272 | |
| 273 | serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1)); |
| 274 | |
| 275 | /* last byte should be all 1's */ |
| 276 | if ((~serial_num) << 24) |
| 277 | return FM10K_ERR_INVALID_MAC_ADDR; |
| 278 | |
| 279 | perm_addr[0] = (u8)(serial_num >> 24); |
| 280 | perm_addr[1] = (u8)(serial_num >> 16); |
| 281 | perm_addr[2] = (u8)(serial_num >> 8); |
| 282 | |
| 283 | serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0)); |
| 284 | |
| 285 | /* first byte should be all 1's */ |
| 286 | if ((~serial_num) >> 24) |
| 287 | return FM10K_ERR_INVALID_MAC_ADDR; |
| 288 | |
| 289 | perm_addr[3] = (u8)(serial_num >> 16); |
| 290 | perm_addr[4] = (u8)(serial_num >> 8); |
| 291 | perm_addr[5] = (u8)(serial_num); |
| 292 | |
Jacob Keller | f0cf5c9 | 2015-10-26 16:32:02 -0700 | [diff] [blame] | 293 | ether_addr_copy(hw->mac.perm_addr, perm_addr); |
| 294 | ether_addr_copy(hw->mac.addr, perm_addr); |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 295 | |
| 296 | return 0; |
| 297 | } |
| 298 | |
| 299 | /** |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 300 | * fm10k_glort_valid_pf - Validate that the provided glort is valid |
| 301 | * @hw: pointer to the HW structure |
| 302 | * @glort: base glort to be validated |
| 303 | * |
| 304 | * This function will return an error if the provided glort is invalid |
| 305 | **/ |
| 306 | bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort) |
| 307 | { |
| 308 | glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT; |
| 309 | |
| 310 | return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE); |
| 311 | } |
| 312 | |
| 313 | /** |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 314 | * fm10k_update_xc_addr_pf - Update device addresses |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 315 | * @hw: pointer to the HW structure |
| 316 | * @glort: base resource tag for this request |
| 317 | * @mac: MAC address to add/remove from table |
| 318 | * @vid: VLAN ID to add/remove from table |
| 319 | * @add: Indicates if this is an add or remove operation |
| 320 | * @flags: flags field to indicate add and secure |
| 321 | * |
| 322 | * This function generates a message to the Switch API requesting |
| 323 | * that the given logical port add/remove the given L2 MAC/VLAN address. |
| 324 | **/ |
| 325 | static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort, |
| 326 | const u8 *mac, u16 vid, bool add, u8 flags) |
| 327 | { |
| 328 | struct fm10k_mbx_info *mbx = &hw->mbx; |
| 329 | struct fm10k_mac_update mac_update; |
| 330 | u32 msg[5]; |
| 331 | |
Jeff Kirsher | b32d15b | 2015-04-03 13:27:15 -0700 | [diff] [blame] | 332 | /* clear set bit from VLAN ID */ |
| 333 | vid &= ~FM10K_VLAN_CLEAR; |
| 334 | |
Jacob Keller | aa502b4 | 2015-11-02 12:10:22 -0800 | [diff] [blame] | 335 | /* if glort or VLAN are not valid return error */ |
Matthew Vick | 33a44c2 | 2015-01-27 02:33:26 +0000 | [diff] [blame] | 336 | if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX) |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 337 | return FM10K_ERR_PARAM; |
| 338 | |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 339 | /* record fields */ |
| 340 | mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) | |
| 341 | ((u32)mac[3] << 16) | |
| 342 | ((u32)mac[4] << 8) | |
| 343 | ((u32)mac[5])); |
Jacob Keller | 9d4955b | 2015-10-16 10:57:00 -0700 | [diff] [blame] | 344 | mac_update.mac_upper = cpu_to_le16(((u16)mac[0] << 8) | |
| 345 | ((u16)mac[1])); |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 346 | mac_update.vlan = cpu_to_le16(vid); |
| 347 | mac_update.glort = cpu_to_le16(glort); |
| 348 | mac_update.action = add ? 0 : 1; |
| 349 | mac_update.flags = flags; |
| 350 | |
| 351 | /* populate mac_update fields */ |
| 352 | fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE); |
| 353 | fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE, |
| 354 | &mac_update, sizeof(mac_update)); |
| 355 | |
| 356 | /* load onto outgoing mailbox */ |
| 357 | return mbx->ops.enqueue_tx(hw, mbx, msg); |
| 358 | } |
| 359 | |
| 360 | /** |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 361 | * fm10k_update_uc_addr_pf - Update device unicast addresses |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 362 | * @hw: pointer to the HW structure |
| 363 | * @glort: base resource tag for this request |
| 364 | * @mac: MAC address to add/remove from table |
| 365 | * @vid: VLAN ID to add/remove from table |
| 366 | * @add: Indicates if this is an add or remove operation |
| 367 | * @flags: flags field to indicate add and secure |
| 368 | * |
| 369 | * This function is used to add or remove unicast addresses for |
| 370 | * the PF. |
| 371 | **/ |
| 372 | static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort, |
| 373 | const u8 *mac, u16 vid, bool add, u8 flags) |
| 374 | { |
| 375 | /* verify MAC address is valid */ |
| 376 | if (!is_valid_ether_addr(mac)) |
| 377 | return FM10K_ERR_PARAM; |
| 378 | |
| 379 | return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags); |
| 380 | } |
| 381 | |
| 382 | /** |
| 383 | * fm10k_update_mc_addr_pf - Update device multicast addresses |
| 384 | * @hw: pointer to the HW structure |
| 385 | * @glort: base resource tag for this request |
| 386 | * @mac: MAC address to add/remove from table |
| 387 | * @vid: VLAN ID to add/remove from table |
| 388 | * @add: Indicates if this is an add or remove operation |
| 389 | * |
| 390 | * This function is used to add or remove multicast MAC addresses for |
| 391 | * the PF. |
| 392 | **/ |
| 393 | static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort, |
| 394 | const u8 *mac, u16 vid, bool add) |
| 395 | { |
| 396 | /* verify multicast address is valid */ |
| 397 | if (!is_multicast_ether_addr(mac)) |
| 398 | return FM10K_ERR_PARAM; |
| 399 | |
| 400 | return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0); |
| 401 | } |
| 402 | |
| 403 | /** |
| 404 | * fm10k_update_xcast_mode_pf - Request update of multicast mode |
| 405 | * @hw: pointer to hardware structure |
| 406 | * @glort: base resource tag for this request |
| 407 | * @mode: integer value indicating mode being requested |
| 408 | * |
| 409 | * This function will attempt to request a higher mode for the port |
| 410 | * so that it can enable either multicast, multicast promiscuous, or |
| 411 | * promiscuous mode of operation. |
| 412 | **/ |
| 413 | static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode) |
| 414 | { |
| 415 | struct fm10k_mbx_info *mbx = &hw->mbx; |
| 416 | u32 msg[3], xcast_mode; |
| 417 | |
| 418 | if (mode > FM10K_XCAST_MODE_NONE) |
| 419 | return FM10K_ERR_PARAM; |
Bruce Allan | a4fcad6 | 2015-10-28 17:19:40 -0700 | [diff] [blame] | 420 | |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 421 | /* if glort is not valid return error */ |
| 422 | if (!fm10k_glort_valid_pf(hw, glort)) |
| 423 | return FM10K_ERR_PARAM; |
| 424 | |
| 425 | /* write xcast mode as a single u32 value, |
| 426 | * lower 16 bits: glort |
| 427 | * upper 16 bits: mode |
| 428 | */ |
| 429 | xcast_mode = ((u32)mode << 16) | glort; |
| 430 | |
| 431 | /* generate message requesting to change xcast mode */ |
| 432 | fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES); |
| 433 | fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode); |
| 434 | |
| 435 | /* load onto outgoing mailbox */ |
| 436 | return mbx->ops.enqueue_tx(hw, mbx, msg); |
| 437 | } |
| 438 | |
| 439 | /** |
| 440 | * fm10k_update_int_moderator_pf - Update interrupt moderator linked list |
| 441 | * @hw: pointer to hardware structure |
| 442 | * |
| 443 | * This function walks through the MSI-X vector table to determine the |
| 444 | * number of active interrupts and based on that information updates the |
| 445 | * interrupt moderator linked list. |
| 446 | **/ |
| 447 | static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw) |
| 448 | { |
| 449 | u32 i; |
| 450 | |
| 451 | /* Disable interrupt moderator */ |
| 452 | fm10k_write_reg(hw, FM10K_INT_CTRL, 0); |
| 453 | |
| 454 | /* loop through PF from last to first looking enabled vectors */ |
| 455 | for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) { |
| 456 | if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) |
| 457 | break; |
| 458 | } |
| 459 | |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 460 | /* always reset VFITR2[0] to point to last enabled PF vector */ |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 461 | fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i); |
| 462 | |
| 463 | /* reset ITR2[0] to point to last enabled PF vector */ |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 464 | if (!hw->iov.num_vfs) |
| 465 | fm10k_write_reg(hw, FM10K_ITR2(0), i); |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 466 | |
| 467 | /* Enable interrupt moderator */ |
| 468 | fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); |
| 469 | } |
| 470 | |
| 471 | /** |
| 472 | * fm10k_update_lport_state_pf - Notify the switch of a change in port state |
| 473 | * @hw: pointer to the HW structure |
| 474 | * @glort: base resource tag for this request |
| 475 | * @count: number of logical ports being updated |
| 476 | * @enable: boolean value indicating enable or disable |
| 477 | * |
| 478 | * This function is used to add/remove a logical port from the switch. |
| 479 | **/ |
| 480 | static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort, |
| 481 | u16 count, bool enable) |
| 482 | { |
| 483 | struct fm10k_mbx_info *mbx = &hw->mbx; |
| 484 | u32 msg[3], lport_msg; |
| 485 | |
| 486 | /* do nothing if we are being asked to create or destroy 0 ports */ |
| 487 | if (!count) |
| 488 | return 0; |
| 489 | |
| 490 | /* if glort is not valid return error */ |
| 491 | if (!fm10k_glort_valid_pf(hw, glort)) |
| 492 | return FM10K_ERR_PARAM; |
| 493 | |
Ngai-Mint Kwan | 11ec36a | 2016-04-01 16:17:39 -0700 | [diff] [blame] | 494 | /* reset multicast mode if deleting lport */ |
| 495 | if (!enable) |
| 496 | fm10k_update_xcast_mode_pf(hw, glort, FM10K_XCAST_MODE_NONE); |
| 497 | |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 498 | /* construct the lport message from the 2 pieces of data we have */ |
| 499 | lport_msg = ((u32)count << 16) | glort; |
| 500 | |
| 501 | /* generate lport create/delete message */ |
| 502 | fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE : |
| 503 | FM10K_PF_MSG_ID_LPORT_DELETE); |
| 504 | fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg); |
| 505 | |
| 506 | /* load onto outgoing mailbox */ |
| 507 | return mbx->ops.enqueue_tx(hw, mbx, msg); |
| 508 | } |
| 509 | |
| 510 | /** |
| 511 | * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues |
| 512 | * @hw: pointer to hardware structure |
| 513 | * @dglort: pointer to dglort configuration structure |
| 514 | * |
| 515 | * Reads the configuration structure contained in dglort_cfg and uses |
| 516 | * that information to then populate a DGLORTMAP/DEC entry and the queues |
| 517 | * to which it has been assigned. |
| 518 | **/ |
| 519 | static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw, |
| 520 | struct fm10k_dglort_cfg *dglort) |
| 521 | { |
| 522 | u16 glort, queue_count, vsi_count, pc_count; |
| 523 | u16 vsi, queue, pc, q_idx; |
| 524 | u32 txqctl, dglortdec, dglortmap; |
| 525 | |
| 526 | /* verify the dglort pointer */ |
| 527 | if (!dglort) |
| 528 | return FM10K_ERR_PARAM; |
| 529 | |
| 530 | /* verify the dglort values */ |
| 531 | if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) || |
| 532 | (dglort->vsi_l > 6) || (dglort->vsi_b > 64) || |
| 533 | (dglort->queue_l > 8) || (dglort->queue_b >= 256)) |
| 534 | return FM10K_ERR_PARAM; |
| 535 | |
| 536 | /* determine count of VSIs and queues */ |
Bruce Allan | fcdb0a9 | 2015-12-22 13:43:49 -0800 | [diff] [blame] | 537 | queue_count = BIT(dglort->rss_l + dglort->pc_l); |
| 538 | vsi_count = BIT(dglort->vsi_l + dglort->queue_l); |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 539 | glort = dglort->glort; |
| 540 | q_idx = dglort->queue_b; |
| 541 | |
| 542 | /* configure SGLORT for queues */ |
| 543 | for (vsi = 0; vsi < vsi_count; vsi++, glort++) { |
| 544 | for (queue = 0; queue < queue_count; queue++, q_idx++) { |
| 545 | if (q_idx >= FM10K_MAX_QUEUES) |
| 546 | break; |
| 547 | |
| 548 | fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort); |
| 549 | fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort); |
| 550 | } |
| 551 | } |
| 552 | |
| 553 | /* determine count of PCs and queues */ |
Bruce Allan | fcdb0a9 | 2015-12-22 13:43:49 -0800 | [diff] [blame] | 554 | queue_count = BIT(dglort->queue_l + dglort->rss_l + dglort->vsi_l); |
| 555 | pc_count = BIT(dglort->pc_l); |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 556 | |
| 557 | /* configure PC for Tx queues */ |
| 558 | for (pc = 0; pc < pc_count; pc++) { |
| 559 | q_idx = pc + dglort->queue_b; |
| 560 | for (queue = 0; queue < queue_count; queue++) { |
| 561 | if (q_idx >= FM10K_MAX_QUEUES) |
| 562 | break; |
| 563 | |
| 564 | txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx)); |
| 565 | txqctl &= ~FM10K_TXQCTL_PC_MASK; |
| 566 | txqctl |= pc << FM10K_TXQCTL_PC_SHIFT; |
| 567 | fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl); |
| 568 | |
| 569 | q_idx += pc_count; |
| 570 | } |
| 571 | } |
| 572 | |
| 573 | /* configure DGLORTDEC */ |
| 574 | dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | |
| 575 | ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) | |
| 576 | ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) | |
| 577 | ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) | |
| 578 | ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) | |
| 579 | ((u32)(dglort->queue_l)); |
| 580 | if (dglort->inner_rss) |
| 581 | dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE; |
| 582 | |
| 583 | /* configure DGLORTMAP */ |
| 584 | dglortmap = (dglort->idx == fm10k_dglort_default) ? |
| 585 | FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO; |
| 586 | dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l; |
| 587 | dglortmap |= dglort->glort; |
| 588 | |
| 589 | /* write values to hardware */ |
| 590 | fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec); |
| 591 | fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap); |
| 592 | |
| 593 | return 0; |
| 594 | } |
| 595 | |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 596 | u16 fm10k_queues_per_pool(struct fm10k_hw *hw) |
| 597 | { |
| 598 | u16 num_pools = hw->iov.num_pools; |
| 599 | |
| 600 | return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ? |
| 601 | 8 : FM10K_MAX_QUEUES_POOL; |
| 602 | } |
| 603 | |
| 604 | u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx) |
| 605 | { |
| 606 | u16 num_vfs = hw->iov.num_vfs; |
| 607 | u16 vf_q_idx = FM10K_MAX_QUEUES; |
| 608 | |
| 609 | vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx); |
| 610 | |
| 611 | return vf_q_idx; |
| 612 | } |
| 613 | |
| 614 | static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw) |
| 615 | { |
| 616 | u16 num_pools = hw->iov.num_pools; |
| 617 | |
| 618 | return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 : |
| 619 | FM10K_MAX_VECTORS_POOL; |
| 620 | } |
| 621 | |
| 622 | static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx) |
| 623 | { |
| 624 | u16 vf_v_idx = FM10K_MAX_VECTORS_PF; |
| 625 | |
| 626 | vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx; |
| 627 | |
| 628 | return vf_v_idx; |
| 629 | } |
| 630 | |
| 631 | /** |
| 632 | * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization |
| 633 | * @hw: pointer to the HW structure |
| 634 | * @num_vfs: number of VFs to be allocated |
| 635 | * @num_pools: number of virtualization pools to be allocated |
| 636 | * |
| 637 | * Allocates queues and traffic classes to virtualization entities to prepare |
| 638 | * the PF for SR-IOV and VMDq |
| 639 | **/ |
| 640 | static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs, |
| 641 | u16 num_pools) |
| 642 | { |
| 643 | u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx; |
| 644 | u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT; |
| 645 | int i, j; |
| 646 | |
| 647 | /* hardware only supports up to 64 pools */ |
| 648 | if (num_pools > 64) |
| 649 | return FM10K_ERR_PARAM; |
| 650 | |
| 651 | /* the number of VFs cannot exceed the number of pools */ |
| 652 | if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs)) |
| 653 | return FM10K_ERR_PARAM; |
| 654 | |
| 655 | /* record number of virtualization entities */ |
| 656 | hw->iov.num_vfs = num_vfs; |
| 657 | hw->iov.num_pools = num_pools; |
| 658 | |
| 659 | /* determine qmap offsets and counts */ |
| 660 | qmap_stride = (num_vfs > 8) ? 32 : 256; |
| 661 | qpp = fm10k_queues_per_pool(hw); |
| 662 | vpp = fm10k_vectors_per_pool(hw); |
| 663 | |
| 664 | /* calculate starting index for queues */ |
| 665 | vf_q_idx = fm10k_vf_queue_index(hw, 0); |
| 666 | qmap_idx = 0; |
| 667 | |
| 668 | /* establish TCs with -1 credits and no quanta to prevent transmit */ |
| 669 | for (i = 0; i < num_vfs; i++) { |
| 670 | fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0); |
| 671 | fm10k_write_reg(hw, FM10K_TC_RATE(i), 0); |
| 672 | fm10k_write_reg(hw, FM10K_TC_CREDIT(i), |
| 673 | FM10K_TC_CREDIT_CREDIT_MASK); |
| 674 | } |
| 675 | |
| 676 | /* zero out all mbmem registers */ |
| 677 | for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;) |
| 678 | fm10k_write_reg(hw, FM10K_MBMEM(i), 0); |
| 679 | |
| 680 | /* clear event notification of VF FLR */ |
| 681 | fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0); |
| 682 | fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0); |
| 683 | |
| 684 | /* loop through unallocated rings assigning them back to PF */ |
| 685 | for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) { |
| 686 | fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); |
Jeff Kirsher | ded8b20 | 2015-04-03 13:27:04 -0700 | [diff] [blame] | 687 | fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | |
| 688 | FM10K_TXQCTL_UNLIMITED_BW | vid); |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 689 | fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF); |
| 690 | } |
| 691 | |
| 692 | /* PF should have already updated VFITR2[0] */ |
| 693 | |
| 694 | /* update all ITR registers to flow to VFITR2[0] */ |
| 695 | for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) { |
| 696 | if (!(i & (vpp - 1))) |
| 697 | fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp); |
| 698 | else |
| 699 | fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); |
| 700 | } |
| 701 | |
| 702 | /* update PF ITR2[0] to reference the last vector */ |
| 703 | fm10k_write_reg(hw, FM10K_ITR2(0), |
| 704 | fm10k_vf_vector_index(hw, num_vfs - 1)); |
| 705 | |
| 706 | /* loop through rings populating rings and TCs */ |
| 707 | for (i = 0; i < num_vfs; i++) { |
| 708 | /* record index for VF queue 0 for use in end of loop */ |
| 709 | vf_q_idx0 = vf_q_idx; |
| 710 | |
| 711 | for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) { |
| 712 | /* assign VF and locked TC to queues */ |
| 713 | fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); |
| 714 | fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx), |
| 715 | (i << FM10K_TXQCTL_TC_SHIFT) | i | |
| 716 | FM10K_TXQCTL_VF | vid); |
| 717 | fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx), |
| 718 | FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | |
| 719 | FM10K_RXDCTL_DROP_ON_EMPTY); |
| 720 | fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx), |
Bruce Allan | 1aab144 | 2015-12-22 13:43:44 -0800 | [diff] [blame] | 721 | (i << FM10K_RXQCTL_VF_SHIFT) | |
| 722 | FM10K_RXQCTL_VF); |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 723 | |
| 724 | /* map queue pair to VF */ |
| 725 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); |
| 726 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx); |
| 727 | } |
| 728 | |
| 729 | /* repeat the first ring for all of the remaining VF rings */ |
| 730 | for (; j < qmap_stride; j++, qmap_idx++) { |
| 731 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0); |
| 732 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0); |
| 733 | } |
| 734 | } |
| 735 | |
| 736 | /* loop through remaining indexes assigning all to queue 0 */ |
| 737 | while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) { |
| 738 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); |
| 739 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0); |
| 740 | qmap_idx++; |
| 741 | } |
| 742 | |
| 743 | return 0; |
| 744 | } |
| 745 | |
| 746 | /** |
| 747 | * fm10k_iov_configure_tc_pf - Configure the shaping group for VF |
| 748 | * @hw: pointer to the HW structure |
| 749 | * @vf_idx: index of VF receiving GLORT |
| 750 | * @rate: Rate indicated in Mb/s |
| 751 | * |
| 752 | * Configured the TC for a given VF to allow only up to a given number |
| 753 | * of Mb/s of outgoing Tx throughput. |
| 754 | **/ |
| 755 | static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate) |
| 756 | { |
| 757 | /* configure defaults */ |
| 758 | u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3; |
| 759 | u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK; |
| 760 | |
| 761 | /* verify vf is in range */ |
| 762 | if (vf_idx >= hw->iov.num_vfs) |
| 763 | return FM10K_ERR_PARAM; |
| 764 | |
| 765 | /* set interval to align with 4.096 usec in all modes */ |
| 766 | switch (hw->bus.speed) { |
| 767 | case fm10k_bus_speed_2500: |
| 768 | interval = FM10K_TC_RATE_INTERVAL_4US_GEN1; |
| 769 | break; |
| 770 | case fm10k_bus_speed_5000: |
| 771 | interval = FM10K_TC_RATE_INTERVAL_4US_GEN2; |
| 772 | break; |
| 773 | default: |
| 774 | break; |
| 775 | } |
| 776 | |
| 777 | if (rate) { |
| 778 | if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN) |
| 779 | return FM10K_ERR_PARAM; |
| 780 | |
| 781 | /* The quanta is measured in Bytes per 4.096 or 8.192 usec |
| 782 | * The rate is provided in Mbits per second |
| 783 | * To tralslate from rate to quanta we need to multiply the |
| 784 | * rate by 8.192 usec and divide by 8 bits/byte. To avoid |
| 785 | * dealing with floating point we can round the values up |
| 786 | * to the nearest whole number ratio which gives us 128 / 125. |
| 787 | */ |
| 788 | tc_rate = (rate * 128) / 125; |
| 789 | |
| 790 | /* try to keep the rate limiting accurate by increasing |
| 791 | * the number of credits and interval for rates less than 4Gb/s |
| 792 | */ |
| 793 | if (rate < 4000) |
| 794 | interval <<= 1; |
| 795 | else |
| 796 | tc_rate >>= 1; |
| 797 | } |
| 798 | |
| 799 | /* update rate limiter with new values */ |
| 800 | fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval); |
| 801 | fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); |
| 802 | fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); |
| 803 | |
| 804 | return 0; |
| 805 | } |
| 806 | |
| 807 | /** |
| 808 | * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list |
| 809 | * @hw: pointer to the HW structure |
| 810 | * @vf_idx: index of VF receiving GLORT |
| 811 | * |
| 812 | * Update the interrupt moderator linked list to include any MSI-X |
| 813 | * interrupts which the VF has enabled in the MSI-X vector table. |
| 814 | **/ |
| 815 | static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx) |
| 816 | { |
| 817 | u16 vf_v_idx, vf_v_limit, i; |
| 818 | |
| 819 | /* verify vf is in range */ |
| 820 | if (vf_idx >= hw->iov.num_vfs) |
| 821 | return FM10K_ERR_PARAM; |
| 822 | |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 823 | /* determine vector offset and count */ |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 824 | vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); |
| 825 | vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); |
| 826 | |
| 827 | /* search for first vector that is not masked */ |
| 828 | for (i = vf_v_limit - 1; i > vf_v_idx; i--) { |
| 829 | if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) |
| 830 | break; |
| 831 | } |
| 832 | |
| 833 | /* reset linked list so it now includes our active vectors */ |
| 834 | if (vf_idx == (hw->iov.num_vfs - 1)) |
| 835 | fm10k_write_reg(hw, FM10K_ITR2(0), i); |
| 836 | else |
| 837 | fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i); |
| 838 | |
| 839 | return 0; |
| 840 | } |
| 841 | |
| 842 | /** |
| 843 | * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF |
| 844 | * @hw: pointer to the HW structure |
| 845 | * @vf_info: pointer to VF information structure |
| 846 | * |
| 847 | * Assign a MAC address and default VLAN to a VF and notify it of the update |
| 848 | **/ |
| 849 | static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw, |
| 850 | struct fm10k_vf_info *vf_info) |
| 851 | { |
| 852 | u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i; |
| 853 | u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0; |
| 854 | s32 err = 0; |
| 855 | u16 vf_idx, vf_vid; |
| 856 | |
| 857 | /* verify vf is in range */ |
| 858 | if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs) |
| 859 | return FM10K_ERR_PARAM; |
| 860 | |
| 861 | /* determine qmap offsets and counts */ |
| 862 | qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; |
| 863 | queues_per_pool = fm10k_queues_per_pool(hw); |
| 864 | |
| 865 | /* calculate starting index for queues */ |
| 866 | vf_idx = vf_info->vf_idx; |
| 867 | vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); |
| 868 | qmap_idx = qmap_stride * vf_idx; |
| 869 | |
| 870 | /* MAP Tx queue back to 0 temporarily, and disable it */ |
| 871 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); |
| 872 | fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); |
| 873 | |
Jacob Keller | 5c69df8 | 2016-04-01 16:17:37 -0700 | [diff] [blame] | 874 | /* Determine correct default VLAN ID. The FM10K_VLAN_OVERRIDE bit is |
| 875 | * used here to indicate to the VF that it will not have privilege to |
| 876 | * write VLAN_TABLE. All policy is enforced on the PF but this allows |
| 877 | * the VF to correctly report errors to userspace rqeuests. |
| 878 | */ |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 879 | if (vf_info->pf_vid) |
Jacob Keller | 5c69df8 | 2016-04-01 16:17:37 -0700 | [diff] [blame] | 880 | vf_vid = vf_info->pf_vid | FM10K_VLAN_OVERRIDE; |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 881 | else |
| 882 | vf_vid = vf_info->sw_vid; |
| 883 | |
| 884 | /* generate MAC_ADDR request */ |
| 885 | fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN); |
| 886 | fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC, |
| 887 | vf_info->mac, vf_vid); |
| 888 | |
| 889 | /* load onto outgoing mailbox, ignore any errors on enqueue */ |
| 890 | if (vf_info->mbx.ops.enqueue_tx) |
| 891 | vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); |
| 892 | |
| 893 | /* verify ring has disabled before modifying base address registers */ |
| 894 | txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); |
| 895 | for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) { |
| 896 | /* limit ourselves to a 1ms timeout */ |
| 897 | if (timeout == 10) { |
| 898 | err = FM10K_ERR_DMA_PENDING; |
| 899 | goto err_out; |
| 900 | } |
| 901 | |
| 902 | usleep_range(100, 200); |
| 903 | txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); |
| 904 | } |
| 905 | |
| 906 | /* Update base address registers to contain MAC address */ |
| 907 | if (is_valid_ether_addr(vf_info->mac)) { |
| 908 | tdbal = (((u32)vf_info->mac[3]) << 24) | |
| 909 | (((u32)vf_info->mac[4]) << 16) | |
| 910 | (((u32)vf_info->mac[5]) << 8); |
| 911 | |
| 912 | tdbah = (((u32)0xFF) << 24) | |
| 913 | (((u32)vf_info->mac[0]) << 16) | |
| 914 | (((u32)vf_info->mac[1]) << 8) | |
| 915 | ((u32)vf_info->mac[2]); |
| 916 | } |
| 917 | |
| 918 | /* Record the base address into queue 0 */ |
| 919 | fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal); |
| 920 | fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah); |
| 921 | |
Jacob Keller | 20076fa | 2015-10-16 10:57:05 -0700 | [diff] [blame] | 922 | /* Provide the VF the ITR scale, using software-defined fields in TDLEN |
| 923 | * to pass the information during VF initialization. See definition of |
| 924 | * FM10K_TDLEN_ITR_SCALE_SHIFT for more details. |
| 925 | */ |
| 926 | fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale << |
| 927 | FM10K_TDLEN_ITR_SCALE_SHIFT); |
| 928 | |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 929 | err_out: |
| 930 | /* configure Queue control register */ |
| 931 | txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) & |
| 932 | FM10K_TXQCTL_VID_MASK; |
| 933 | txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) | |
| 934 | FM10K_TXQCTL_VF | vf_idx; |
| 935 | |
Jacob Keller | aa502b4 | 2015-11-02 12:10:22 -0800 | [diff] [blame] | 936 | /* assign VLAN ID */ |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 937 | for (i = 0; i < queues_per_pool; i++) |
| 938 | fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl); |
| 939 | |
| 940 | /* restore the queue back to VF ownership */ |
| 941 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); |
| 942 | return err; |
| 943 | } |
| 944 | |
| 945 | /** |
| 946 | * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF |
| 947 | * @hw: pointer to the HW structure |
| 948 | * @vf_info: pointer to VF information structure |
| 949 | * |
| 950 | * Reassign the interrupts and queues to a VF following an FLR |
| 951 | **/ |
| 952 | static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw, |
| 953 | struct fm10k_vf_info *vf_info) |
| 954 | { |
| 955 | u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx; |
| 956 | u32 tdbal = 0, tdbah = 0, txqctl, rxqctl; |
| 957 | u16 vf_v_idx, vf_v_limit, vf_vid; |
| 958 | u8 vf_idx = vf_info->vf_idx; |
| 959 | int i; |
| 960 | |
| 961 | /* verify vf is in range */ |
| 962 | if (vf_idx >= hw->iov.num_vfs) |
| 963 | return FM10K_ERR_PARAM; |
| 964 | |
| 965 | /* clear event notification of VF FLR */ |
Bruce Allan | fcdb0a9 | 2015-12-22 13:43:49 -0800 | [diff] [blame] | 966 | fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), BIT(vf_idx % 32)); |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 967 | |
| 968 | /* force timeout and then disconnect the mailbox */ |
| 969 | vf_info->mbx.timeout = 0; |
| 970 | if (vf_info->mbx.ops.disconnect) |
| 971 | vf_info->mbx.ops.disconnect(hw, &vf_info->mbx); |
| 972 | |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 973 | /* determine vector offset and count */ |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 974 | vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); |
| 975 | vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); |
| 976 | |
| 977 | /* determine qmap offsets and counts */ |
| 978 | qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; |
| 979 | queues_per_pool = fm10k_queues_per_pool(hw); |
| 980 | qmap_idx = qmap_stride * vf_idx; |
| 981 | |
| 982 | /* make all the queues inaccessible to the VF */ |
| 983 | for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) { |
| 984 | fm10k_write_reg(hw, FM10K_TQMAP(i), 0); |
| 985 | fm10k_write_reg(hw, FM10K_RQMAP(i), 0); |
| 986 | } |
| 987 | |
| 988 | /* calculate starting index for queues */ |
| 989 | vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); |
| 990 | |
| 991 | /* determine correct default VLAN ID */ |
| 992 | if (vf_info->pf_vid) |
| 993 | vf_vid = vf_info->pf_vid; |
| 994 | else |
| 995 | vf_vid = vf_info->sw_vid; |
| 996 | |
| 997 | /* configure Queue control register */ |
| 998 | txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) | |
| 999 | (vf_idx << FM10K_TXQCTL_TC_SHIFT) | |
| 1000 | FM10K_TXQCTL_VF | vf_idx; |
Bruce Allan | 1aab144 | 2015-12-22 13:43:44 -0800 | [diff] [blame] | 1001 | rxqctl = (vf_idx << FM10K_RXQCTL_VF_SHIFT) | FM10K_RXQCTL_VF; |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1002 | |
| 1003 | /* stop further DMA and reset queue ownership back to VF */ |
| 1004 | for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) { |
| 1005 | fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); |
| 1006 | fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); |
| 1007 | fm10k_write_reg(hw, FM10K_RXDCTL(i), |
| 1008 | FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | |
| 1009 | FM10K_RXDCTL_DROP_ON_EMPTY); |
| 1010 | fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl); |
| 1011 | } |
| 1012 | |
| 1013 | /* reset TC with -1 credits and no quanta to prevent transmit */ |
| 1014 | fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0); |
| 1015 | fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0); |
| 1016 | fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), |
| 1017 | FM10K_TC_CREDIT_CREDIT_MASK); |
| 1018 | |
| 1019 | /* update our first entry in the table based on previous VF */ |
| 1020 | if (!vf_idx) |
| 1021 | hw->mac.ops.update_int_moderator(hw); |
| 1022 | else |
| 1023 | hw->iov.ops.assign_int_moderator(hw, vf_idx - 1); |
| 1024 | |
| 1025 | /* reset linked list so it now includes our active vectors */ |
| 1026 | if (vf_idx == (hw->iov.num_vfs - 1)) |
| 1027 | fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx); |
| 1028 | else |
| 1029 | fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx); |
| 1030 | |
| 1031 | /* link remaining vectors so that next points to previous */ |
| 1032 | for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++) |
| 1033 | fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1); |
| 1034 | |
| 1035 | /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */ |
| 1036 | for (i = FM10K_VFMBMEM_LEN; i--;) |
| 1037 | fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0); |
| 1038 | for (i = FM10K_VLAN_TABLE_SIZE; i--;) |
| 1039 | fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0); |
| 1040 | for (i = FM10K_RETA_SIZE; i--;) |
| 1041 | fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0); |
| 1042 | for (i = FM10K_RSSRK_SIZE; i--;) |
| 1043 | fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0); |
| 1044 | fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0); |
| 1045 | |
| 1046 | /* Update base address registers to contain MAC address */ |
| 1047 | if (is_valid_ether_addr(vf_info->mac)) { |
| 1048 | tdbal = (((u32)vf_info->mac[3]) << 24) | |
| 1049 | (((u32)vf_info->mac[4]) << 16) | |
| 1050 | (((u32)vf_info->mac[5]) << 8); |
| 1051 | tdbah = (((u32)0xFF) << 24) | |
| 1052 | (((u32)vf_info->mac[0]) << 16) | |
| 1053 | (((u32)vf_info->mac[1]) << 8) | |
| 1054 | ((u32)vf_info->mac[2]); |
| 1055 | } |
| 1056 | |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 1057 | /* map queue pairs back to VF from last to first */ |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1058 | for (i = queues_per_pool; i--;) { |
| 1059 | fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal); |
| 1060 | fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah); |
Jacob Keller | 20076fa | 2015-10-16 10:57:05 -0700 | [diff] [blame] | 1061 | /* See definition of FM10K_TDLEN_ITR_SCALE_SHIFT for an |
| 1062 | * explanation of how TDLEN is used. |
| 1063 | */ |
| 1064 | fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx + i), |
| 1065 | hw->mac.itr_scale << |
| 1066 | FM10K_TDLEN_ITR_SCALE_SHIFT); |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1067 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i); |
| 1068 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i); |
| 1069 | } |
| 1070 | |
Jacob Keller | fba341d | 2015-06-03 16:31:08 -0700 | [diff] [blame] | 1071 | /* repeat the first ring for all the remaining VF rings */ |
| 1072 | for (i = queues_per_pool; i < qmap_stride; i++) { |
| 1073 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx); |
| 1074 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx); |
| 1075 | } |
| 1076 | |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1077 | return 0; |
| 1078 | } |
| 1079 | |
| 1080 | /** |
| 1081 | * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF |
| 1082 | * @hw: pointer to hardware structure |
| 1083 | * @vf_info: pointer to VF information structure |
| 1084 | * @lport_idx: Logical port offset from the hardware glort |
| 1085 | * @flags: Set of capability flags to extend port beyond basic functionality |
| 1086 | * |
| 1087 | * This function allows enabling a VF port by assigning it a GLORT and |
| 1088 | * setting the flags so that it can enable an Rx mode. |
| 1089 | **/ |
| 1090 | static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw, |
| 1091 | struct fm10k_vf_info *vf_info, |
| 1092 | u16 lport_idx, u8 flags) |
| 1093 | { |
| 1094 | u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE; |
| 1095 | |
| 1096 | /* if glort is not valid return error */ |
| 1097 | if (!fm10k_glort_valid_pf(hw, glort)) |
| 1098 | return FM10K_ERR_PARAM; |
| 1099 | |
| 1100 | vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE; |
| 1101 | vf_info->glort = glort; |
| 1102 | |
| 1103 | return 0; |
| 1104 | } |
| 1105 | |
| 1106 | /** |
| 1107 | * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF |
| 1108 | * @hw: pointer to hardware structure |
| 1109 | * @vf_info: pointer to VF information structure |
| 1110 | * |
| 1111 | * This function disables a VF port by stripping it of a GLORT and |
| 1112 | * setting the flags so that it cannot enable any Rx mode. |
| 1113 | **/ |
| 1114 | static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw, |
| 1115 | struct fm10k_vf_info *vf_info) |
| 1116 | { |
| 1117 | u32 msg[1]; |
| 1118 | |
| 1119 | /* need to disable the port if it is already enabled */ |
| 1120 | if (FM10K_VF_FLAG_ENABLED(vf_info)) { |
| 1121 | /* notify switch that this port has been disabled */ |
| 1122 | fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false); |
| 1123 | |
| 1124 | /* generate port state response to notify VF it is not ready */ |
| 1125 | fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); |
| 1126 | vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); |
| 1127 | } |
| 1128 | |
| 1129 | /* clear flags and glort if it exists */ |
| 1130 | vf_info->vf_flags = 0; |
| 1131 | vf_info->glort = 0; |
| 1132 | } |
| 1133 | |
| 1134 | /** |
| 1135 | * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs |
| 1136 | * @hw: pointer to hardware structure |
| 1137 | * @q: stats for all queues of a VF |
| 1138 | * @vf_idx: index of VF |
| 1139 | * |
| 1140 | * This function collects queue stats for VFs. |
| 1141 | **/ |
| 1142 | static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw, |
| 1143 | struct fm10k_hw_stats_q *q, |
| 1144 | u16 vf_idx) |
| 1145 | { |
| 1146 | u32 idx, qpp; |
| 1147 | |
| 1148 | /* get stats for all of the queues */ |
| 1149 | qpp = fm10k_queues_per_pool(hw); |
| 1150 | idx = fm10k_vf_queue_index(hw, vf_idx); |
| 1151 | fm10k_update_hw_stats_q(hw, q, idx, qpp); |
| 1152 | } |
| 1153 | |
| 1154 | /** |
| 1155 | * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF |
| 1156 | * @hw: Pointer to hardware structure |
| 1157 | * @results: Pointer array to message, results[0] is pointer to message |
| 1158 | * @mbx: Pointer to mailbox information structure |
| 1159 | * |
| 1160 | * This function is a default handler for MSI-X requests from the VF. The |
| 1161 | * assumption is that in this case it is acceptable to just directly |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 1162 | * hand off the message from the VF to the underlying shared code. |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1163 | **/ |
| 1164 | s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results, |
| 1165 | struct fm10k_mbx_info *mbx) |
| 1166 | { |
| 1167 | struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; |
| 1168 | u8 vf_idx = vf_info->vf_idx; |
| 1169 | |
| 1170 | return hw->iov.ops.assign_int_moderator(hw, vf_idx); |
| 1171 | } |
| 1172 | |
| 1173 | /** |
Jacob Keller | aa502b4 | 2015-11-02 12:10:22 -0800 | [diff] [blame] | 1174 | * fm10k_iov_select_vid - Select correct default VLAN ID |
Jacob Keller | 9adbac5 | 2015-06-24 13:34:50 -0700 | [diff] [blame] | 1175 | * @hw: Pointer to hardware structure |
Jacob Keller | aa502b4 | 2015-11-02 12:10:22 -0800 | [diff] [blame] | 1176 | * @vid: VLAN ID to correct |
Jacob Keller | 9adbac5 | 2015-06-24 13:34:50 -0700 | [diff] [blame] | 1177 | * |
Jacob Keller | aa502b4 | 2015-11-02 12:10:22 -0800 | [diff] [blame] | 1178 | * Will report an error if the VLAN ID is out of range. For VID = 0, it will |
| 1179 | * return either the pf_vid or sw_vid depending on which one is set. |
Jacob Keller | 9adbac5 | 2015-06-24 13:34:50 -0700 | [diff] [blame] | 1180 | */ |
Bruce Allan | e214d85 | 2015-10-28 16:04:40 -0700 | [diff] [blame] | 1181 | static s32 fm10k_iov_select_vid(struct fm10k_vf_info *vf_info, u16 vid) |
Jacob Keller | 9adbac5 | 2015-06-24 13:34:50 -0700 | [diff] [blame] | 1182 | { |
| 1183 | if (!vid) |
| 1184 | return vf_info->pf_vid ? vf_info->pf_vid : vf_info->sw_vid; |
| 1185 | else if (vf_info->pf_vid && vid != vf_info->pf_vid) |
| 1186 | return FM10K_ERR_PARAM; |
| 1187 | else |
| 1188 | return vid; |
| 1189 | } |
| 1190 | |
| 1191 | /** |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1192 | * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF |
| 1193 | * @hw: Pointer to hardware structure |
| 1194 | * @results: Pointer array to message, results[0] is pointer to message |
| 1195 | * @mbx: Pointer to mailbox information structure |
| 1196 | * |
| 1197 | * This function is a default handler for MAC/VLAN requests from the VF. |
| 1198 | * The assumption is that in this case it is acceptable to just directly |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 1199 | * hand off the message from the VF to the underlying shared code. |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1200 | **/ |
| 1201 | s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results, |
| 1202 | struct fm10k_mbx_info *mbx) |
| 1203 | { |
| 1204 | struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1205 | u8 mac[ETH_ALEN]; |
| 1206 | u32 *result; |
Jacob Keller | 9adbac5 | 2015-06-24 13:34:50 -0700 | [diff] [blame] | 1207 | int err = 0; |
| 1208 | bool set; |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1209 | u16 vlan; |
| 1210 | u32 vid; |
| 1211 | |
| 1212 | /* we shouldn't be updating rules on a disabled interface */ |
| 1213 | if (!FM10K_VF_FLAG_ENABLED(vf_info)) |
| 1214 | err = FM10K_ERR_PARAM; |
| 1215 | |
| 1216 | if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) { |
| 1217 | result = results[FM10K_MAC_VLAN_MSG_VLAN]; |
| 1218 | |
| 1219 | /* record VLAN id requested */ |
| 1220 | err = fm10k_tlv_attr_get_u32(result, &vid); |
| 1221 | if (err) |
| 1222 | return err; |
| 1223 | |
Jacob Keller | 9adbac5 | 2015-06-24 13:34:50 -0700 | [diff] [blame] | 1224 | set = !(vid & FM10K_VLAN_CLEAR); |
| 1225 | vid &= ~FM10K_VLAN_CLEAR; |
| 1226 | |
Jacob Keller | f808c5d | 2016-03-31 09:52:30 -0700 | [diff] [blame] | 1227 | /* if the length field has been set, this is a multi-bit |
| 1228 | * update request. For multi-bit requests, simply disallow |
| 1229 | * them when the pf_vid has been set. In this case, the PF |
| 1230 | * should have already cleared the VLAN_TABLE, and if we |
| 1231 | * allowed them, it could allow a rogue VF to receive traffic |
| 1232 | * on a VLAN it was not assigned. In the single-bit case, we |
| 1233 | * need to modify requests for VLAN 0 to use the default PF or |
| 1234 | * SW vid when assigned. |
| 1235 | */ |
Jacob Keller | 4ab0f79 | 2015-10-26 16:32:05 -0700 | [diff] [blame] | 1236 | |
Jacob Keller | f808c5d | 2016-03-31 09:52:30 -0700 | [diff] [blame] | 1237 | if (vid >> 16) { |
| 1238 | /* prevent multi-bit requests when PF has |
| 1239 | * administratively set the VLAN for this VF |
| 1240 | */ |
| 1241 | if (vf_info->pf_vid) |
| 1242 | return FM10K_ERR_PARAM; |
| 1243 | } else { |
| 1244 | err = fm10k_iov_select_vid(vf_info, (u16)vid); |
| 1245 | if (err < 0) |
| 1246 | return err; |
| 1247 | |
| 1248 | vid = err; |
| 1249 | } |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1250 | |
| 1251 | /* update VSI info for VF in regards to VLAN table */ |
Jacob Keller | 9adbac5 | 2015-06-24 13:34:50 -0700 | [diff] [blame] | 1252 | err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, set); |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1253 | } |
| 1254 | |
| 1255 | if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) { |
| 1256 | result = results[FM10K_MAC_VLAN_MSG_MAC]; |
| 1257 | |
| 1258 | /* record unicast MAC address requested */ |
| 1259 | err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); |
| 1260 | if (err) |
| 1261 | return err; |
| 1262 | |
| 1263 | /* block attempts to set MAC for a locked device */ |
| 1264 | if (is_valid_ether_addr(vf_info->mac) && |
Jacob Keller | 6186ddf | 2015-11-16 15:33:34 -0800 | [diff] [blame] | 1265 | !ether_addr_equal(mac, vf_info->mac)) |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1266 | return FM10K_ERR_PARAM; |
| 1267 | |
Jacob Keller | 9adbac5 | 2015-06-24 13:34:50 -0700 | [diff] [blame] | 1268 | set = !(vlan & FM10K_VLAN_CLEAR); |
| 1269 | vlan &= ~FM10K_VLAN_CLEAR; |
| 1270 | |
| 1271 | err = fm10k_iov_select_vid(vf_info, vlan); |
| 1272 | if (err < 0) |
| 1273 | return err; |
Jacob Keller | 4ab0f79 | 2015-10-26 16:32:05 -0700 | [diff] [blame] | 1274 | |
| 1275 | vlan = (u16)err; |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1276 | |
| 1277 | /* notify switch of request for new unicast address */ |
Jacob Keller | 9adbac5 | 2015-06-24 13:34:50 -0700 | [diff] [blame] | 1278 | err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, |
| 1279 | mac, vlan, set, 0); |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1280 | } |
| 1281 | |
| 1282 | if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) { |
| 1283 | result = results[FM10K_MAC_VLAN_MSG_MULTICAST]; |
| 1284 | |
| 1285 | /* record multicast MAC address requested */ |
| 1286 | err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); |
| 1287 | if (err) |
| 1288 | return err; |
| 1289 | |
| 1290 | /* verify that the VF is allowed to request multicast */ |
| 1291 | if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED)) |
| 1292 | return FM10K_ERR_PARAM; |
| 1293 | |
Jacob Keller | 9adbac5 | 2015-06-24 13:34:50 -0700 | [diff] [blame] | 1294 | set = !(vlan & FM10K_VLAN_CLEAR); |
| 1295 | vlan &= ~FM10K_VLAN_CLEAR; |
| 1296 | |
| 1297 | err = fm10k_iov_select_vid(vf_info, vlan); |
| 1298 | if (err < 0) |
| 1299 | return err; |
Jacob Keller | 4ab0f79 | 2015-10-26 16:32:05 -0700 | [diff] [blame] | 1300 | |
| 1301 | vlan = (u16)err; |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1302 | |
| 1303 | /* notify switch of request for new multicast address */ |
Jacob Keller | 9adbac5 | 2015-06-24 13:34:50 -0700 | [diff] [blame] | 1304 | err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, |
| 1305 | mac, vlan, set); |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1306 | } |
| 1307 | |
| 1308 | return err; |
| 1309 | } |
| 1310 | |
| 1311 | /** |
| 1312 | * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode |
| 1313 | * @vf_info: VF info structure containing capability flags |
| 1314 | * @mode: Requested xcast mode |
| 1315 | * |
| 1316 | * This function outputs the mode that most closely matches the requested |
| 1317 | * mode. If not modes match it will request we disable the port |
| 1318 | **/ |
| 1319 | static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info, |
| 1320 | u8 mode) |
| 1321 | { |
| 1322 | u8 vf_flags = vf_info->vf_flags; |
| 1323 | |
| 1324 | /* match up mode to capabilities as best as possible */ |
| 1325 | switch (mode) { |
| 1326 | case FM10K_XCAST_MODE_PROMISC: |
| 1327 | if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE) |
| 1328 | return FM10K_XCAST_MODE_PROMISC; |
| 1329 | /* fallthough */ |
| 1330 | case FM10K_XCAST_MODE_ALLMULTI: |
| 1331 | if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE) |
| 1332 | return FM10K_XCAST_MODE_ALLMULTI; |
| 1333 | /* fallthough */ |
| 1334 | case FM10K_XCAST_MODE_MULTI: |
| 1335 | if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE) |
| 1336 | return FM10K_XCAST_MODE_MULTI; |
| 1337 | /* fallthough */ |
| 1338 | case FM10K_XCAST_MODE_NONE: |
| 1339 | if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE) |
| 1340 | return FM10K_XCAST_MODE_NONE; |
| 1341 | /* fallthough */ |
| 1342 | default: |
| 1343 | break; |
| 1344 | } |
| 1345 | |
| 1346 | /* disable interface as it should not be able to request any */ |
| 1347 | return FM10K_XCAST_MODE_DISABLE; |
| 1348 | } |
| 1349 | |
| 1350 | /** |
| 1351 | * fm10k_iov_msg_lport_state_pf - Message handler for port state requests |
| 1352 | * @hw: Pointer to hardware structure |
| 1353 | * @results: Pointer array to message, results[0] is pointer to message |
| 1354 | * @mbx: Pointer to mailbox information structure |
| 1355 | * |
| 1356 | * This function is a default handler for port state requests. The port |
| 1357 | * state requests for now are basic and consist of enabling or disabling |
| 1358 | * the port. |
| 1359 | **/ |
| 1360 | s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results, |
| 1361 | struct fm10k_mbx_info *mbx) |
| 1362 | { |
| 1363 | struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; |
| 1364 | u32 *result; |
| 1365 | s32 err = 0; |
| 1366 | u32 msg[2]; |
| 1367 | u8 mode = 0; |
| 1368 | |
| 1369 | /* verify VF is allowed to enable even minimal mode */ |
| 1370 | if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)) |
| 1371 | return FM10K_ERR_PARAM; |
| 1372 | |
| 1373 | if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) { |
| 1374 | result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE]; |
| 1375 | |
| 1376 | /* XCAST mode update requested */ |
| 1377 | err = fm10k_tlv_attr_get_u8(result, &mode); |
| 1378 | if (err) |
| 1379 | return FM10K_ERR_PARAM; |
| 1380 | |
| 1381 | /* prep for possible demotion depending on capabilities */ |
| 1382 | mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode); |
| 1383 | |
| 1384 | /* if mode is not currently enabled, enable it */ |
Bruce Allan | fcdb0a9 | 2015-12-22 13:43:49 -0800 | [diff] [blame] | 1385 | if (!(FM10K_VF_FLAG_ENABLED(vf_info) & BIT(mode))) |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1386 | fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode); |
| 1387 | |
| 1388 | /* swap mode back to a bit flag */ |
| 1389 | mode = FM10K_VF_FLAG_SET_MODE(mode); |
| 1390 | } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) { |
| 1391 | /* need to disable the port if it is already enabled */ |
| 1392 | if (FM10K_VF_FLAG_ENABLED(vf_info)) |
| 1393 | err = fm10k_update_lport_state_pf(hw, vf_info->glort, |
| 1394 | 1, false); |
| 1395 | |
Jacob Keller | ee4373e7 | 2015-06-03 16:31:12 -0700 | [diff] [blame] | 1396 | /* we need to clear VF_FLAG_ENABLED flags in order to ensure |
| 1397 | * that we actually re-enable the LPORT state below. Note that |
| 1398 | * this has no impact if the VF is already disabled, as the |
| 1399 | * flags are already cleared. |
| 1400 | */ |
| 1401 | if (!err) |
| 1402 | vf_info->vf_flags = FM10K_VF_FLAG_CAPABLE(vf_info); |
| 1403 | |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1404 | /* when enabling the port we should reset the rate limiters */ |
| 1405 | hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate); |
| 1406 | |
| 1407 | /* set mode for minimal functionality */ |
| 1408 | mode = FM10K_VF_FLAG_SET_MODE_NONE; |
| 1409 | |
| 1410 | /* generate port state response to notify VF it is ready */ |
| 1411 | fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); |
| 1412 | fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY); |
| 1413 | mbx->ops.enqueue_tx(hw, mbx, msg); |
| 1414 | } |
| 1415 | |
| 1416 | /* if enable state toggled note the update */ |
| 1417 | if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode)) |
| 1418 | err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1, |
| 1419 | !!mode); |
| 1420 | |
| 1421 | /* if state change succeeded, then update our stored state */ |
| 1422 | mode |= FM10K_VF_FLAG_CAPABLE(vf_info); |
| 1423 | if (!err) |
| 1424 | vf_info->vf_flags = mode; |
| 1425 | |
| 1426 | return err; |
| 1427 | } |
| 1428 | |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1429 | /** |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1430 | * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF |
| 1431 | * @hw: pointer to hardware structure |
| 1432 | * @stats: pointer to the stats structure to update |
| 1433 | * |
| 1434 | * This function collects and aggregates global and per queue hardware |
| 1435 | * statistics. |
| 1436 | **/ |
| 1437 | static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw, |
| 1438 | struct fm10k_hw_stats *stats) |
| 1439 | { |
| 1440 | u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop; |
| 1441 | u32 id, id_prev; |
| 1442 | |
| 1443 | /* Use Tx queue 0 as a canary to detect a reset */ |
| 1444 | id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); |
| 1445 | |
| 1446 | /* Read Global Statistics */ |
| 1447 | do { |
| 1448 | timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT, |
| 1449 | &stats->timeout); |
| 1450 | ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur); |
| 1451 | ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca); |
| 1452 | um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um); |
| 1453 | xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec); |
| 1454 | vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP, |
| 1455 | &stats->vlan_drop); |
Bruce Allan | 3d02b3d | 2015-10-28 17:19:56 -0700 | [diff] [blame] | 1456 | loopback_drop = |
| 1457 | fm10k_read_hw_stats_32b(hw, |
| 1458 | FM10K_STATS_LOOPBACK_DROP, |
| 1459 | &stats->loopback_drop); |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1460 | nodesc_drop = fm10k_read_hw_stats_32b(hw, |
| 1461 | FM10K_STATS_NODESC_DROP, |
| 1462 | &stats->nodesc_drop); |
| 1463 | |
| 1464 | /* if value has not changed then we have consistent data */ |
| 1465 | id_prev = id; |
| 1466 | id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); |
| 1467 | } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK); |
| 1468 | |
| 1469 | /* drop non-ID bits and set VALID ID bit */ |
| 1470 | id &= FM10K_TXQCTL_ID_MASK; |
| 1471 | id |= FM10K_STAT_VALID; |
| 1472 | |
| 1473 | /* Update Global Statistics */ |
| 1474 | if (stats->stats_idx == id) { |
| 1475 | stats->timeout.count += timeout; |
| 1476 | stats->ur.count += ur; |
| 1477 | stats->ca.count += ca; |
| 1478 | stats->um.count += um; |
| 1479 | stats->xec.count += xec; |
| 1480 | stats->vlan_drop.count += vlan_drop; |
| 1481 | stats->loopback_drop.count += loopback_drop; |
| 1482 | stats->nodesc_drop.count += nodesc_drop; |
| 1483 | } |
| 1484 | |
| 1485 | /* Update bases and record current PF id */ |
| 1486 | fm10k_update_hw_base_32b(&stats->timeout, timeout); |
| 1487 | fm10k_update_hw_base_32b(&stats->ur, ur); |
| 1488 | fm10k_update_hw_base_32b(&stats->ca, ca); |
| 1489 | fm10k_update_hw_base_32b(&stats->um, um); |
| 1490 | fm10k_update_hw_base_32b(&stats->xec, xec); |
| 1491 | fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop); |
| 1492 | fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop); |
| 1493 | fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop); |
| 1494 | stats->stats_idx = id; |
| 1495 | |
| 1496 | /* Update Queue Statistics */ |
| 1497 | fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues); |
| 1498 | } |
| 1499 | |
| 1500 | /** |
| 1501 | * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF |
| 1502 | * @hw: pointer to hardware structure |
| 1503 | * @stats: pointer to the stats structure to update |
| 1504 | * |
| 1505 | * This function resets the base for global and per queue hardware |
| 1506 | * statistics. |
| 1507 | **/ |
| 1508 | static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw, |
| 1509 | struct fm10k_hw_stats *stats) |
| 1510 | { |
| 1511 | /* Unbind Global Statistics */ |
| 1512 | fm10k_unbind_hw_stats_32b(&stats->timeout); |
| 1513 | fm10k_unbind_hw_stats_32b(&stats->ur); |
| 1514 | fm10k_unbind_hw_stats_32b(&stats->ca); |
| 1515 | fm10k_unbind_hw_stats_32b(&stats->um); |
| 1516 | fm10k_unbind_hw_stats_32b(&stats->xec); |
| 1517 | fm10k_unbind_hw_stats_32b(&stats->vlan_drop); |
| 1518 | fm10k_unbind_hw_stats_32b(&stats->loopback_drop); |
| 1519 | fm10k_unbind_hw_stats_32b(&stats->nodesc_drop); |
| 1520 | |
| 1521 | /* Unbind Queue Statistics */ |
| 1522 | fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues); |
| 1523 | |
| 1524 | /* Reinitialize bases for all stats */ |
| 1525 | fm10k_update_hw_stats_pf(hw, stats); |
| 1526 | } |
| 1527 | |
| 1528 | /** |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1529 | * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system |
| 1530 | * @hw: pointer to hardware structure |
| 1531 | * @dma_mask: 64 bit DMA mask required for platform |
| 1532 | * |
| 1533 | * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order |
| 1534 | * to limit the access to memory beyond what is physically in the system. |
| 1535 | **/ |
| 1536 | static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask) |
| 1537 | { |
| 1538 | /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */ |
| 1539 | u32 phyaddr = (u32)(dma_mask >> 32); |
| 1540 | |
| 1541 | fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr); |
| 1542 | } |
| 1543 | |
| 1544 | /** |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1545 | * fm10k_get_fault_pf - Record a fault in one of the interface units |
| 1546 | * @hw: pointer to hardware structure |
| 1547 | * @type: pointer to fault type register offset |
| 1548 | * @fault: pointer to memory location to record the fault |
| 1549 | * |
| 1550 | * Record the fault register contents to the fault data structure and |
| 1551 | * clear the entry from the register. |
| 1552 | * |
| 1553 | * Returns ERR_PARAM if invalid register is specified or no error is present. |
| 1554 | **/ |
| 1555 | static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type, |
| 1556 | struct fm10k_fault *fault) |
| 1557 | { |
| 1558 | u32 func; |
| 1559 | |
| 1560 | /* verify the fault register is in range and is aligned */ |
| 1561 | switch (type) { |
| 1562 | case FM10K_PCA_FAULT: |
| 1563 | case FM10K_THI_FAULT: |
| 1564 | case FM10K_FUM_FAULT: |
| 1565 | break; |
| 1566 | default: |
| 1567 | return FM10K_ERR_PARAM; |
| 1568 | } |
| 1569 | |
| 1570 | /* only service faults that are valid */ |
| 1571 | func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC); |
| 1572 | if (!(func & FM10K_FAULT_FUNC_VALID)) |
| 1573 | return FM10K_ERR_PARAM; |
| 1574 | |
| 1575 | /* read remaining fields */ |
| 1576 | fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI); |
| 1577 | fault->address <<= 32; |
| 1578 | fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO); |
| 1579 | fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO); |
| 1580 | |
| 1581 | /* clear valid bit to allow for next error */ |
| 1582 | fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID); |
| 1583 | |
| 1584 | /* Record which function triggered the error */ |
| 1585 | if (func & FM10K_FAULT_FUNC_PF) |
| 1586 | fault->func = 0; |
| 1587 | else |
| 1588 | fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >> |
| 1589 | FM10K_FAULT_FUNC_VF_SHIFT); |
| 1590 | |
| 1591 | /* record fault type */ |
| 1592 | fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK; |
| 1593 | |
| 1594 | return 0; |
| 1595 | } |
| 1596 | |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1597 | /** |
| 1598 | * fm10k_request_lport_map_pf - Request LPORT map from the switch API |
| 1599 | * @hw: pointer to hardware structure |
| 1600 | * |
| 1601 | **/ |
| 1602 | static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw) |
| 1603 | { |
| 1604 | struct fm10k_mbx_info *mbx = &hw->mbx; |
| 1605 | u32 msg[1]; |
| 1606 | |
| 1607 | /* issue request asking for LPORT map */ |
| 1608 | fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP); |
| 1609 | |
| 1610 | /* load onto outgoing mailbox */ |
| 1611 | return mbx->ops.enqueue_tx(hw, mbx, msg); |
| 1612 | } |
| 1613 | |
| 1614 | /** |
| 1615 | * fm10k_get_host_state_pf - Returns the state of the switch and mailbox |
| 1616 | * @hw: pointer to hardware structure |
| 1617 | * @switch_ready: pointer to boolean value that will record switch state |
| 1618 | * |
Jacob Keller | d8ec92f | 2016-02-10 14:45:51 -0800 | [diff] [blame] | 1619 | * This function will check the DMA_CTRL2 register and mailbox in order |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1620 | * to determine if the switch is ready for the PF to begin requesting |
| 1621 | * addresses and mapping traffic to the local interface. |
| 1622 | **/ |
| 1623 | static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready) |
| 1624 | { |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1625 | u32 dma_ctrl2; |
| 1626 | |
Matthew Vick | eca3204 | 2015-01-31 02:23:05 +0000 | [diff] [blame] | 1627 | /* verify the switch is ready for interaction */ |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1628 | dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2); |
| 1629 | if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY)) |
Jacob Keller | 0afd20e | 2016-06-07 16:08:59 -0700 | [diff] [blame] | 1630 | return 0; |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1631 | |
| 1632 | /* retrieve generic host state info */ |
Jacob Keller | 0afd20e | 2016-06-07 16:08:59 -0700 | [diff] [blame] | 1633 | return fm10k_get_host_state_generic(hw, switch_ready); |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1634 | } |
| 1635 | |
| 1636 | /* This structure defines the attibutes to be parsed below */ |
| 1637 | const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = { |
Jacob Keller | a7a7783 | 2016-04-01 16:17:33 -0700 | [diff] [blame] | 1638 | FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR, |
| 1639 | sizeof(struct fm10k_swapi_error)), |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1640 | FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP), |
| 1641 | FM10K_TLV_ATTR_LAST |
| 1642 | }; |
| 1643 | |
| 1644 | /** |
| 1645 | * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM |
| 1646 | * @hw: Pointer to hardware structure |
| 1647 | * @results: pointer array containing parsed data |
| 1648 | * @mbx: Pointer to mailbox information structure |
| 1649 | * |
| 1650 | * This handler configures the lport mapping based on the reply from the |
| 1651 | * switch API. |
| 1652 | **/ |
| 1653 | s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results, |
| 1654 | struct fm10k_mbx_info *mbx) |
| 1655 | { |
| 1656 | u16 glort, mask; |
| 1657 | u32 dglort_map; |
| 1658 | s32 err; |
| 1659 | |
| 1660 | err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP], |
| 1661 | &dglort_map); |
| 1662 | if (err) |
| 1663 | return err; |
| 1664 | |
| 1665 | /* extract values out of the header */ |
| 1666 | glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT); |
| 1667 | mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK); |
| 1668 | |
| 1669 | /* verify mask is set and none of the masked bits in glort are set */ |
| 1670 | if (!mask || (glort & ~mask)) |
| 1671 | return FM10K_ERR_PARAM; |
| 1672 | |
| 1673 | /* verify the mask is contiguous, and that it is 1's followed by 0's */ |
| 1674 | if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE) |
| 1675 | return FM10K_ERR_PARAM; |
| 1676 | |
| 1677 | /* record the glort, mask, and port count */ |
| 1678 | hw->mac.dglort_map = dglort_map; |
| 1679 | |
| 1680 | return 0; |
| 1681 | } |
| 1682 | |
| 1683 | const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = { |
| 1684 | FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID), |
| 1685 | FM10K_TLV_ATTR_LAST |
| 1686 | }; |
| 1687 | |
| 1688 | /** |
| 1689 | * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM |
| 1690 | * @hw: Pointer to hardware structure |
| 1691 | * @results: pointer array containing parsed data |
| 1692 | * @mbx: Pointer to mailbox information structure |
| 1693 | * |
| 1694 | * This handler configures the default VLAN for the PF |
| 1695 | **/ |
Bruce Allan | bb269e8 | 2015-10-28 17:19:51 -0700 | [diff] [blame] | 1696 | static s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results, |
| 1697 | struct fm10k_mbx_info *mbx) |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1698 | { |
| 1699 | u16 glort, pvid; |
| 1700 | u32 pvid_update; |
| 1701 | s32 err; |
| 1702 | |
| 1703 | err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID], |
| 1704 | &pvid_update); |
| 1705 | if (err) |
| 1706 | return err; |
| 1707 | |
| 1708 | /* extract values from the pvid update */ |
| 1709 | glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT); |
| 1710 | pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID); |
| 1711 | |
| 1712 | /* if glort is not valid return error */ |
| 1713 | if (!fm10k_glort_valid_pf(hw, glort)) |
| 1714 | return FM10K_ERR_PARAM; |
| 1715 | |
Jacob Keller | aa502b4 | 2015-11-02 12:10:22 -0800 | [diff] [blame] | 1716 | /* verify VLAN ID is valid */ |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1717 | if (pvid >= FM10K_VLAN_TABLE_VID_MAX) |
| 1718 | return FM10K_ERR_PARAM; |
| 1719 | |
| 1720 | /* record the port VLAN ID value */ |
| 1721 | hw->mac.default_vid = pvid; |
| 1722 | |
| 1723 | return 0; |
| 1724 | } |
| 1725 | |
| 1726 | /** |
| 1727 | * fm10k_record_global_table_data - Move global table data to swapi table info |
| 1728 | * @from: pointer to source table data structure |
| 1729 | * @to: pointer to destination table info structure |
| 1730 | * |
| 1731 | * This function is will copy table_data to the table_info contained in |
| 1732 | * the hw struct. |
| 1733 | **/ |
| 1734 | static void fm10k_record_global_table_data(struct fm10k_global_table_data *from, |
| 1735 | struct fm10k_swapi_table_info *to) |
| 1736 | { |
| 1737 | /* convert from le32 struct to CPU byte ordered values */ |
| 1738 | to->used = le32_to_cpu(from->used); |
| 1739 | to->avail = le32_to_cpu(from->avail); |
| 1740 | } |
| 1741 | |
| 1742 | const struct fm10k_tlv_attr fm10k_err_msg_attr[] = { |
| 1743 | FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR, |
| 1744 | sizeof(struct fm10k_swapi_error)), |
| 1745 | FM10K_TLV_ATTR_LAST |
| 1746 | }; |
| 1747 | |
| 1748 | /** |
| 1749 | * fm10k_msg_err_pf - Message handler for error reply |
| 1750 | * @hw: Pointer to hardware structure |
| 1751 | * @results: pointer array containing parsed data |
| 1752 | * @mbx: Pointer to mailbox information structure |
| 1753 | * |
| 1754 | * This handler will capture the data for any error replies to previous |
| 1755 | * messages that the PF has sent. |
| 1756 | **/ |
| 1757 | s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results, |
| 1758 | struct fm10k_mbx_info *mbx) |
| 1759 | { |
| 1760 | struct fm10k_swapi_error err_msg; |
| 1761 | s32 err; |
| 1762 | |
| 1763 | /* extract structure from message */ |
| 1764 | err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR], |
| 1765 | &err_msg, sizeof(err_msg)); |
| 1766 | if (err) |
| 1767 | return err; |
| 1768 | |
| 1769 | /* record table status */ |
| 1770 | fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac); |
| 1771 | fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop); |
| 1772 | fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu); |
| 1773 | |
| 1774 | /* record SW API status value */ |
| 1775 | hw->swapi.status = le32_to_cpu(err_msg.status); |
| 1776 | |
| 1777 | return 0; |
| 1778 | } |
| 1779 | |
| 1780 | static const struct fm10k_msg_data fm10k_msg_data_pf[] = { |
| 1781 | FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf), |
| 1782 | FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf), |
| 1783 | FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf), |
| 1784 | FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf), |
| 1785 | FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf), |
| 1786 | FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf), |
| 1787 | FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error), |
| 1788 | }; |
| 1789 | |
Bruce Allan | f329ad7 | 2015-12-08 15:50:39 -0800 | [diff] [blame] | 1790 | static const struct fm10k_mac_ops mac_ops_pf = { |
Bruce Allan | 4e458cf | 2015-12-08 15:50:34 -0800 | [diff] [blame] | 1791 | .get_bus_info = fm10k_get_bus_info_generic, |
| 1792 | .reset_hw = fm10k_reset_hw_pf, |
| 1793 | .init_hw = fm10k_init_hw_pf, |
| 1794 | .start_hw = fm10k_start_hw_generic, |
| 1795 | .stop_hw = fm10k_stop_hw_generic, |
| 1796 | .update_vlan = fm10k_update_vlan_pf, |
| 1797 | .read_mac_addr = fm10k_read_mac_addr_pf, |
| 1798 | .update_uc_addr = fm10k_update_uc_addr_pf, |
| 1799 | .update_mc_addr = fm10k_update_mc_addr_pf, |
| 1800 | .update_xcast_mode = fm10k_update_xcast_mode_pf, |
| 1801 | .update_int_moderator = fm10k_update_int_moderator_pf, |
| 1802 | .update_lport_state = fm10k_update_lport_state_pf, |
| 1803 | .update_hw_stats = fm10k_update_hw_stats_pf, |
| 1804 | .rebind_hw_stats = fm10k_rebind_hw_stats_pf, |
| 1805 | .configure_dglort_map = fm10k_configure_dglort_map_pf, |
| 1806 | .set_dma_mask = fm10k_set_dma_mask_pf, |
| 1807 | .get_fault = fm10k_get_fault_pf, |
| 1808 | .get_host_state = fm10k_get_host_state_pf, |
Jacob Keller | 0afd20e | 2016-06-07 16:08:59 -0700 | [diff] [blame] | 1809 | .request_lport_map = fm10k_request_lport_map_pf, |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1810 | }; |
| 1811 | |
Bruce Allan | f329ad7 | 2015-12-08 15:50:39 -0800 | [diff] [blame] | 1812 | static const struct fm10k_iov_ops iov_ops_pf = { |
Bruce Allan | 4e458cf | 2015-12-08 15:50:34 -0800 | [diff] [blame] | 1813 | .assign_resources = fm10k_iov_assign_resources_pf, |
| 1814 | .configure_tc = fm10k_iov_configure_tc_pf, |
| 1815 | .assign_int_moderator = fm10k_iov_assign_int_moderator_pf, |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1816 | .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf, |
Bruce Allan | 4e458cf | 2015-12-08 15:50:34 -0800 | [diff] [blame] | 1817 | .reset_resources = fm10k_iov_reset_resources_pf, |
| 1818 | .set_lport = fm10k_iov_set_lport_pf, |
| 1819 | .reset_lport = fm10k_iov_reset_lport_pf, |
| 1820 | .update_stats = fm10k_iov_update_stats_pf, |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1821 | }; |
| 1822 | |
Alexander Duyck | 401b538 | 2014-09-20 19:47:58 -0400 | [diff] [blame] | 1823 | static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw) |
| 1824 | { |
| 1825 | fm10k_get_invariants_generic(hw); |
| 1826 | |
| 1827 | return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf); |
| 1828 | } |
| 1829 | |
Bruce Allan | f329ad7 | 2015-12-08 15:50:39 -0800 | [diff] [blame] | 1830 | const struct fm10k_info fm10k_pf_info = { |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1831 | .mac = fm10k_mac_pf, |
Bruce Allan | 4e458cf | 2015-12-08 15:50:34 -0800 | [diff] [blame] | 1832 | .get_invariants = fm10k_get_invariants_pf, |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1833 | .mac_ops = &mac_ops_pf, |
Alexander Duyck | c265386 | 2014-09-20 19:51:57 -0400 | [diff] [blame] | 1834 | .iov_ops = &iov_ops_pf, |
Alexander Duyck | b6fec18 | 2014-09-20 19:47:46 -0400 | [diff] [blame] | 1835 | }; |