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Jiri Pirko93c1edb2015-07-29 23:33:46 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/core.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_CORE_H
38#define _MLXSW_CORE_H
39
40#include <linux/module.h>
41#include <linux/device.h>
42#include <linux/slab.h>
43#include <linux/gfp.h>
44#include <linux/types.h>
45#include <linux/skbuff.h>
Jiri Pirkodd9bdb02016-04-14 18:19:28 +020046#include <linux/workqueue.h>
Jiri Pirko932762b2016-04-08 19:11:21 +020047#include <net/devlink.h>
Jiri Pirko93c1edb2015-07-29 23:33:46 +020048
Ido Schimmel4ec14b72015-07-29 23:33:48 +020049#include "trap.h"
50#include "reg.h"
51
Jiri Pirko93c1edb2015-07-29 23:33:46 +020052#include "cmd.h"
53
54#define MLXSW_MODULE_ALIAS_PREFIX "mlxsw-driver-"
55#define MODULE_MLXSW_DRIVER_ALIAS(kind) \
56 MODULE_ALIAS(MLXSW_MODULE_ALIAS_PREFIX kind)
57
Jiri Pirko31557f02015-07-29 23:33:49 +020058#define MLXSW_DEVICE_KIND_SWITCHX2 "switchx2"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020059#define MLXSW_DEVICE_KIND_SPECTRUM "spectrum"
Jiri Pirko31557f02015-07-29 23:33:49 +020060
Jiri Pirko93c1edb2015-07-29 23:33:46 +020061struct mlxsw_core;
62struct mlxsw_driver;
63struct mlxsw_bus;
64struct mlxsw_bus_info;
65
Jiri Pirkob2f10572016-04-08 19:11:23 +020066void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core);
67
Jiri Pirko93c1edb2015-07-29 23:33:46 +020068int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver);
69void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver);
70
71int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info,
72 const struct mlxsw_bus *mlxsw_bus,
73 void *bus_priv);
74void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core);
75
76struct mlxsw_tx_info {
77 u8 local_port;
78 bool is_emad;
79};
80
Jiri Pirko307c2432016-04-08 19:11:22 +020081bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core,
Ido Schimmeld0034622015-08-06 16:41:56 +020082 const struct mlxsw_tx_info *tx_info);
Jiri Pirko307c2432016-04-08 19:11:22 +020083int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb,
Jiri Pirko93c1edb2015-07-29 23:33:46 +020084 const struct mlxsw_tx_info *tx_info);
85
86struct mlxsw_rx_listener {
87 void (*func)(struct sk_buff *skb, u8 local_port, void *priv);
88 u8 local_port;
89 u16 trap_id;
90};
91
Ido Schimmel4ec14b72015-07-29 23:33:48 +020092struct mlxsw_event_listener {
93 void (*func)(const struct mlxsw_reg_info *reg,
94 char *payload, void *priv);
95 enum mlxsw_event_trap_id trap_id;
96};
97
Jiri Pirko93c1edb2015-07-29 23:33:46 +020098int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core,
99 const struct mlxsw_rx_listener *rxl,
100 void *priv);
101void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core,
102 const struct mlxsw_rx_listener *rxl,
103 void *priv);
104
Ido Schimmel4ec14b72015-07-29 23:33:48 +0200105int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core,
106 const struct mlxsw_event_listener *el,
107 void *priv);
108void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core,
109 const struct mlxsw_event_listener *el,
110 void *priv);
111
Jiri Pirkocaf7297e2016-04-14 18:19:29 +0200112typedef void mlxsw_reg_trans_cb_t(struct mlxsw_core *mlxsw_core, char *payload,
113 size_t payload_len, unsigned long cb_priv);
114
115int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core,
116 const struct mlxsw_reg_info *reg, char *payload,
117 struct list_head *bulk_list,
118 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv);
119int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core,
120 const struct mlxsw_reg_info *reg, char *payload,
121 struct list_head *bulk_list,
122 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv);
123int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list);
124
Ido Schimmel4ec14b72015-07-29 23:33:48 +0200125int mlxsw_reg_query(struct mlxsw_core *mlxsw_core,
126 const struct mlxsw_reg_info *reg, char *payload);
127int mlxsw_reg_write(struct mlxsw_core *mlxsw_core,
128 const struct mlxsw_reg_info *reg, char *payload);
129
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200130struct mlxsw_rx_info {
Jiri Pirko80606462015-12-03 12:12:23 +0100131 bool is_lag;
132 union {
133 u16 sys_port;
134 u16 lag_id;
135 } u;
136 u8 lag_port_index;
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200137 int trap_id;
138};
139
140void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb,
141 struct mlxsw_rx_info *rx_info);
142
Jiri Pirko80606462015-12-03 12:12:23 +0100143void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core,
144 u16 lag_id, u8 port_index, u8 local_port);
145u8 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core,
146 u16 lag_id, u8 port_index);
147void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core,
148 u16 lag_id, u8 local_port);
149
Jiri Pirko932762b2016-04-08 19:11:21 +0200150struct mlxsw_core_port {
151 struct devlink_port devlink_port;
152};
153
Jiri Pirko325f2f12016-04-14 18:19:23 +0200154static inline void *
155mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port)
156{
157 /* mlxsw_core_port is ensured to always be the first field in driver
158 * port structure.
159 */
160 return mlxsw_core_port;
161}
162
Jiri Pirko932762b2016-04-08 19:11:21 +0200163int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core,
164 struct mlxsw_core_port *mlxsw_core_port, u8 local_port,
165 struct net_device *dev, bool split, u32 split_group);
166void mlxsw_core_port_fini(struct mlxsw_core_port *mlxsw_core_port);
167
Jiri Pirkodd9bdb02016-04-14 18:19:28 +0200168int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay);
169
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200170#define MLXSW_CONFIG_PROFILE_SWID_COUNT 8
171
172struct mlxsw_swid_config {
173 u8 used_type:1,
174 used_properties:1;
175 u8 type;
176 u8 properties;
177};
178
179struct mlxsw_config_profile {
180 u16 used_max_vepa_channels:1,
181 used_max_lag:1,
182 used_max_port_per_lag:1,
183 used_max_mid:1,
184 used_max_pgt:1,
185 used_max_system_port:1,
186 used_max_vlan_groups:1,
187 used_max_regions:1,
188 used_flood_tables:1,
189 used_flood_mode:1,
190 used_max_ib_mc:1,
191 used_max_pkey:1,
192 used_ar_sec:1,
Jiri Pirko489107b2016-07-05 11:27:45 +0200193 used_adaptive_routing_group_cap:1,
194 used_kvd_sizes:1;
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200195 u8 max_vepa_channels;
196 u16 max_lag;
197 u16 max_port_per_lag;
198 u16 max_mid;
199 u16 max_pgt;
200 u16 max_system_port;
201 u16 max_vlan_groups;
202 u16 max_regions;
203 u8 max_flood_tables;
204 u8 max_vid_flood_tables;
205 u8 flood_mode;
Ido Schimmel12fd35a2015-10-16 14:01:25 +0200206 u8 max_fid_offset_flood_tables;
207 u16 fid_offset_flood_table_size;
Ido Schimmel453b6a82015-10-16 14:01:24 +0200208 u8 max_fid_flood_tables;
209 u16 fid_flood_table_size;
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200210 u16 max_ib_mc;
211 u16 max_pkey;
212 u8 ar_sec;
213 u16 adaptive_routing_group_cap;
214 u8 arn;
Jiri Pirko489107b2016-07-05 11:27:45 +0200215 u32 kvd_linear_size;
216 u32 kvd_hash_single_size;
217 u32 kvd_hash_double_size;
Nogah Frankel57d316b2016-07-21 12:03:09 +0200218 u8 resource_query_enable;
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200219 struct mlxsw_swid_config swid_config[MLXSW_CONFIG_PROFILE_SWID_COUNT];
220};
221
222struct mlxsw_driver {
223 struct list_head list;
224 const char *kind;
225 struct module *owner;
226 size_t priv_size;
Jiri Pirkob2f10572016-04-08 19:11:23 +0200227 int (*init)(struct mlxsw_core *mlxsw_core,
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200228 const struct mlxsw_bus_info *mlxsw_bus_info);
Jiri Pirkob2f10572016-04-08 19:11:23 +0200229 void (*fini)(struct mlxsw_core *mlxsw_core);
230 int (*port_split)(struct mlxsw_core *mlxsw_core, u8 local_port,
231 unsigned int count);
232 int (*port_unsplit)(struct mlxsw_core *mlxsw_core, u8 local_port);
Jiri Pirkoa6179bf2016-04-14 18:19:15 +0200233 int (*sb_pool_get)(struct mlxsw_core *mlxsw_core,
234 unsigned int sb_index, u16 pool_index,
235 struct devlink_sb_pool_info *pool_info);
236 int (*sb_pool_set)(struct mlxsw_core *mlxsw_core,
237 unsigned int sb_index, u16 pool_index, u32 size,
238 enum devlink_sb_threshold_type threshold_type);
239 int (*sb_port_pool_get)(struct mlxsw_core_port *mlxsw_core_port,
240 unsigned int sb_index, u16 pool_index,
241 u32 *p_threshold);
242 int (*sb_port_pool_set)(struct mlxsw_core_port *mlxsw_core_port,
243 unsigned int sb_index, u16 pool_index,
244 u32 threshold);
245 int (*sb_tc_pool_bind_get)(struct mlxsw_core_port *mlxsw_core_port,
246 unsigned int sb_index, u16 tc_index,
247 enum devlink_sb_pool_type pool_type,
248 u16 *p_pool_index, u32 *p_threshold);
249 int (*sb_tc_pool_bind_set)(struct mlxsw_core_port *mlxsw_core_port,
250 unsigned int sb_index, u16 tc_index,
251 enum devlink_sb_pool_type pool_type,
252 u16 pool_index, u32 threshold);
Jiri Pirko1ceecc82016-04-14 18:19:25 +0200253 int (*sb_occ_snapshot)(struct mlxsw_core *mlxsw_core,
254 unsigned int sb_index);
255 int (*sb_occ_max_clear)(struct mlxsw_core *mlxsw_core,
256 unsigned int sb_index);
257 int (*sb_occ_port_pool_get)(struct mlxsw_core_port *mlxsw_core_port,
258 unsigned int sb_index, u16 pool_index,
259 u32 *p_cur, u32 *p_max);
260 int (*sb_occ_tc_port_bind_get)(struct mlxsw_core_port *mlxsw_core_port,
261 unsigned int sb_index, u16 tc_index,
262 enum devlink_sb_pool_type pool_type,
263 u32 *p_cur, u32 *p_max);
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200264 void (*txhdr_construct)(struct sk_buff *skb,
265 const struct mlxsw_tx_info *tx_info);
266 u8 txhdr_len;
267 const struct mlxsw_config_profile *profile;
268};
269
Nogah Frankel57d316b2016-07-21 12:03:09 +0200270struct mlxsw_resources {
Nogah Frankelded821c2016-07-21 12:03:10 +0200271 u8 max_span_valid:1;
272 u8 max_span;
Nogah Frankel57d316b2016-07-21 12:03:09 +0200273};
274
275struct mlxsw_resources *mlxsw_core_resources_get(struct mlxsw_core *mlxsw_core);
276
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200277struct mlxsw_bus {
278 const char *kind;
279 int (*init)(void *bus_priv, struct mlxsw_core *mlxsw_core,
Nogah Frankel57d316b2016-07-21 12:03:09 +0200280 const struct mlxsw_config_profile *profile,
281 struct mlxsw_resources *resources);
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200282 void (*fini)(void *bus_priv);
Ido Schimmeld0034622015-08-06 16:41:56 +0200283 bool (*skb_transmit_busy)(void *bus_priv,
284 const struct mlxsw_tx_info *tx_info);
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200285 int (*skb_transmit)(void *bus_priv, struct sk_buff *skb,
286 const struct mlxsw_tx_info *tx_info);
287 int (*cmd_exec)(void *bus_priv, u16 opcode, u8 opcode_mod,
288 u32 in_mod, bool out_mbox_direct,
289 char *in_mbox, size_t in_mbox_size,
290 char *out_mbox, size_t out_mbox_size,
291 u8 *p_status);
292};
293
294struct mlxsw_bus_info {
295 const char *device_kind;
296 const char *device_name;
297 struct device *dev;
298 struct {
299 u16 major;
300 u16 minor;
301 u16 subminor;
302 } fw_rev;
303 u8 vsd[MLXSW_CMD_BOARDINFO_VSD_LEN];
304 u8 psid[MLXSW_CMD_BOARDINFO_PSID_LEN];
305};
306
Jiri Pirko89309da2015-11-27 13:45:57 +0100307struct mlxsw_hwmon;
308
309#ifdef CONFIG_MLXSW_CORE_HWMON
310
311int mlxsw_hwmon_init(struct mlxsw_core *mlxsw_core,
312 const struct mlxsw_bus_info *mlxsw_bus_info,
313 struct mlxsw_hwmon **p_hwmon);
314void mlxsw_hwmon_fini(struct mlxsw_hwmon *mlxsw_hwmon);
315
316#else
317
318static inline int mlxsw_hwmon_init(struct mlxsw_core *mlxsw_core,
319 const struct mlxsw_bus_info *mlxsw_bus_info,
320 struct mlxsw_hwmon **p_hwmon)
321{
322 return 0;
323}
324
Jiri Pirko89309da2015-11-27 13:45:57 +0100325#endif
326
Jiri Pirko93c1edb2015-07-29 23:33:46 +0200327#endif