Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. |
| 3 | * DWC Ether MAC version 4.00 has been used for developing this code. |
| 4 | * |
| 5 | * This only implements the mac core functions for this chip. |
| 6 | * |
| 7 | * Copyright (C) 2015 STMicroelectronics Ltd |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms and conditions of the GNU General Public License, |
| 11 | * version 2, as published by the Free Software Foundation. |
| 12 | * |
| 13 | * Author: Alexandre Torgue <alexandre.torgue@st.com> |
| 14 | */ |
| 15 | |
| 16 | #include <linux/crc32.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/ethtool.h> |
| 19 | #include <linux/io.h> |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 20 | #include "stmmac_pcs.h" |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 21 | #include "dwmac4.h" |
| 22 | |
| 23 | static void dwmac4_core_init(struct mac_device_info *hw, int mtu) |
| 24 | { |
| 25 | void __iomem *ioaddr = hw->pcsr; |
| 26 | u32 value = readl(ioaddr + GMAC_CONFIG); |
| 27 | |
| 28 | value |= GMAC_CORE_INIT; |
| 29 | |
| 30 | if (mtu > 1500) |
| 31 | value |= GMAC_CONFIG_2K; |
| 32 | if (mtu > 2000) |
| 33 | value |= GMAC_CONFIG_JE; |
| 34 | |
Giuseppe CAVALLARO | 02e57b9 | 2016-06-24 15:16:26 +0200 | [diff] [blame] | 35 | if (hw->ps) { |
| 36 | value |= GMAC_CONFIG_TE; |
| 37 | |
| 38 | if (hw->ps == SPEED_1000) { |
| 39 | value &= ~GMAC_CONFIG_PS; |
| 40 | } else { |
| 41 | value |= GMAC_CONFIG_PS; |
| 42 | |
| 43 | if (hw->ps == SPEED_10) |
| 44 | value &= ~GMAC_CONFIG_FES; |
| 45 | else |
| 46 | value |= GMAC_CONFIG_FES; |
| 47 | } |
| 48 | } |
| 49 | |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 50 | writel(value, ioaddr + GMAC_CONFIG); |
| 51 | |
| 52 | /* Mask GMAC interrupts */ |
Giuseppe CAVALLARO | 3fe5cad | 2016-06-24 15:16:25 +0200 | [diff] [blame] | 53 | value = GMAC_INT_DEFAULT_MASK; |
| 54 | if (hw->pmt) |
| 55 | value |= GMAC_INT_PMT_EN; |
| 56 | if (hw->pcs) |
| 57 | value |= GMAC_PCS_IRQ_DEFAULT; |
| 58 | |
| 59 | writel(value, ioaddr + GMAC_INT_EN); |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 60 | } |
| 61 | |
| 62 | static void dwmac4_dump_regs(struct mac_device_info *hw) |
| 63 | { |
| 64 | void __iomem *ioaddr = hw->pcsr; |
| 65 | int i; |
| 66 | |
| 67 | pr_debug("\tDWMAC4 regs (base addr = 0x%p)\n", ioaddr); |
| 68 | |
| 69 | for (i = 0; i < GMAC_REG_NUM; i++) { |
| 70 | int offset = i * 4; |
| 71 | |
| 72 | pr_debug("\tReg No. %d (offset 0x%x): 0x%08x\n", i, |
| 73 | offset, readl(ioaddr + offset)); |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | static int dwmac4_rx_ipc_enable(struct mac_device_info *hw) |
| 78 | { |
| 79 | void __iomem *ioaddr = hw->pcsr; |
| 80 | u32 value = readl(ioaddr + GMAC_CONFIG); |
| 81 | |
| 82 | if (hw->rx_csum) |
| 83 | value |= GMAC_CONFIG_IPC; |
| 84 | else |
| 85 | value &= ~GMAC_CONFIG_IPC; |
| 86 | |
| 87 | writel(value, ioaddr + GMAC_CONFIG); |
| 88 | |
| 89 | value = readl(ioaddr + GMAC_CONFIG); |
| 90 | |
| 91 | return !!(value & GMAC_CONFIG_IPC); |
| 92 | } |
| 93 | |
| 94 | static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode) |
| 95 | { |
| 96 | void __iomem *ioaddr = hw->pcsr; |
| 97 | unsigned int pmt = 0; |
| 98 | |
| 99 | if (mode & WAKE_MAGIC) { |
| 100 | pr_debug("GMAC: WOL Magic frame\n"); |
| 101 | pmt |= power_down | magic_pkt_en; |
| 102 | } |
| 103 | if (mode & WAKE_UCAST) { |
| 104 | pr_debug("GMAC: WOL on global unicast\n"); |
| 105 | pmt |= global_unicast; |
| 106 | } |
| 107 | |
| 108 | writel(pmt, ioaddr + GMAC_PMT); |
| 109 | } |
| 110 | |
| 111 | static void dwmac4_set_umac_addr(struct mac_device_info *hw, |
| 112 | unsigned char *addr, unsigned int reg_n) |
| 113 | { |
| 114 | void __iomem *ioaddr = hw->pcsr; |
| 115 | |
| 116 | stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), |
| 117 | GMAC_ADDR_LOW(reg_n)); |
| 118 | } |
| 119 | |
| 120 | static void dwmac4_get_umac_addr(struct mac_device_info *hw, |
| 121 | unsigned char *addr, unsigned int reg_n) |
| 122 | { |
| 123 | void __iomem *ioaddr = hw->pcsr; |
| 124 | |
| 125 | stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), |
| 126 | GMAC_ADDR_LOW(reg_n)); |
| 127 | } |
| 128 | |
| 129 | static void dwmac4_set_filter(struct mac_device_info *hw, |
| 130 | struct net_device *dev) |
| 131 | { |
| 132 | void __iomem *ioaddr = (void __iomem *)dev->base_addr; |
| 133 | unsigned int value = 0; |
| 134 | |
| 135 | if (dev->flags & IFF_PROMISC) { |
| 136 | value = GMAC_PACKET_FILTER_PR; |
| 137 | } else if ((dev->flags & IFF_ALLMULTI) || |
| 138 | (netdev_mc_count(dev) > HASH_TABLE_SIZE)) { |
| 139 | /* Pass all multi */ |
| 140 | value = GMAC_PACKET_FILTER_PM; |
| 141 | /* Set the 64 bits of the HASH tab. To be updated if taller |
| 142 | * hash table is used |
| 143 | */ |
| 144 | writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31); |
| 145 | writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63); |
| 146 | } else if (!netdev_mc_empty(dev)) { |
| 147 | u32 mc_filter[2]; |
| 148 | struct netdev_hw_addr *ha; |
| 149 | |
| 150 | /* Hash filter for multicast */ |
| 151 | value = GMAC_PACKET_FILTER_HMC; |
| 152 | |
| 153 | memset(mc_filter, 0, sizeof(mc_filter)); |
| 154 | netdev_for_each_mc_addr(ha, dev) { |
| 155 | /* The upper 6 bits of the calculated CRC are used to |
| 156 | * index the content of the Hash Table Reg 0 and 1. |
| 157 | */ |
| 158 | int bit_nr = |
| 159 | (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26); |
| 160 | /* The most significant bit determines the register |
| 161 | * to use while the other 5 bits determines the bit |
| 162 | * within the selected register |
| 163 | */ |
| 164 | mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F)); |
| 165 | } |
| 166 | writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31); |
| 167 | writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63); |
| 168 | } |
| 169 | |
| 170 | /* Handle multiple unicast addresses */ |
| 171 | if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) { |
| 172 | /* Switch to promiscuous mode if more than 128 addrs |
| 173 | * are required |
| 174 | */ |
| 175 | value |= GMAC_PACKET_FILTER_PR; |
| 176 | } else if (!netdev_uc_empty(dev)) { |
| 177 | int reg = 1; |
| 178 | struct netdev_hw_addr *ha; |
| 179 | |
| 180 | netdev_for_each_uc_addr(ha, dev) { |
Ben Dooks | ca8bdaf | 2016-06-08 19:21:17 +0100 | [diff] [blame] | 181 | dwmac4_set_umac_addr(hw, ha->addr, reg); |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 182 | reg++; |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | writel(value, ioaddr + GMAC_PACKET_FILTER); |
| 187 | } |
| 188 | |
| 189 | static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex, |
| 190 | unsigned int fc, unsigned int pause_time) |
| 191 | { |
| 192 | void __iomem *ioaddr = hw->pcsr; |
| 193 | u32 channel = STMMAC_CHAN0; /* FIXME */ |
| 194 | unsigned int flow = 0; |
| 195 | |
| 196 | pr_debug("GMAC Flow-Control:\n"); |
| 197 | if (fc & FLOW_RX) { |
| 198 | pr_debug("\tReceive Flow-Control ON\n"); |
| 199 | flow |= GMAC_RX_FLOW_CTRL_RFE; |
| 200 | writel(flow, ioaddr + GMAC_RX_FLOW_CTRL); |
| 201 | } |
| 202 | if (fc & FLOW_TX) { |
| 203 | pr_debug("\tTransmit Flow-Control ON\n"); |
| 204 | flow |= GMAC_TX_FLOW_CTRL_TFE; |
| 205 | writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel)); |
| 206 | |
| 207 | if (duplex) { |
| 208 | pr_debug("\tduplex mode: PAUSE %d\n", pause_time); |
| 209 | flow |= (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT); |
| 210 | writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(channel)); |
| 211 | } |
| 212 | } |
| 213 | } |
| 214 | |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 215 | static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral, |
| 216 | bool loopback) |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 217 | { |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 218 | dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback); |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 219 | } |
| 220 | |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 221 | static void dwmac4_rane(void __iomem *ioaddr, bool restart) |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 222 | { |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 223 | dwmac_rane(ioaddr, GMAC_PCS_BASE, restart); |
| 224 | } |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 225 | |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 226 | static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv) |
| 227 | { |
| 228 | dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv); |
| 229 | } |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 230 | |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 231 | /* RGMII or SMII interface */ |
| 232 | static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x) |
| 233 | { |
| 234 | u32 status; |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 235 | |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 236 | status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS); |
| 237 | x->irq_rgmii_n++; |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 238 | |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 239 | /* Check the link status */ |
| 240 | if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) { |
| 241 | int speed_value; |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 242 | |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 243 | x->pcs_link = 1; |
| 244 | |
| 245 | speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >> |
| 246 | GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT); |
| 247 | if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125) |
| 248 | x->pcs_speed = SPEED_1000; |
| 249 | else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25) |
| 250 | x->pcs_speed = SPEED_100; |
| 251 | else |
| 252 | x->pcs_speed = SPEED_10; |
| 253 | |
| 254 | x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK); |
| 255 | |
| 256 | pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed, |
| 257 | x->pcs_duplex ? "Full" : "Half"); |
| 258 | } else { |
| 259 | x->pcs_link = 0; |
| 260 | pr_info("Link is Down\n"); |
| 261 | } |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | static int dwmac4_irq_status(struct mac_device_info *hw, |
| 265 | struct stmmac_extra_stats *x) |
| 266 | { |
| 267 | void __iomem *ioaddr = hw->pcsr; |
| 268 | u32 mtl_int_qx_status; |
| 269 | u32 intr_status; |
| 270 | int ret = 0; |
| 271 | |
| 272 | intr_status = readl(ioaddr + GMAC_INT_STATUS); |
| 273 | |
| 274 | /* Not used events (e.g. MMC interrupts) are not handled. */ |
| 275 | if ((intr_status & mmc_tx_irq)) |
| 276 | x->mmc_tx_irq_n++; |
| 277 | if (unlikely(intr_status & mmc_rx_irq)) |
| 278 | x->mmc_rx_irq_n++; |
| 279 | if (unlikely(intr_status & mmc_rx_csum_offload_irq)) |
| 280 | x->mmc_rx_csum_offload_irq_n++; |
| 281 | /* Clear the PMT bits 5 and 6 by reading the PMT status reg */ |
| 282 | if (unlikely(intr_status & pmt_irq)) { |
| 283 | readl(ioaddr + GMAC_PMT); |
| 284 | x->irq_receive_pmt_irq_n++; |
| 285 | } |
| 286 | |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 287 | mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS); |
| 288 | /* Check MTL Interrupt: Currently only one queue is used: Q0. */ |
| 289 | if (mtl_int_qx_status & MTL_INT_Q0) { |
| 290 | /* read Queue 0 Interrupt status */ |
| 291 | u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0)); |
| 292 | |
| 293 | if (status & MTL_RX_OVERFLOW_INT) { |
| 294 | /* clear Interrupt */ |
| 295 | writel(status | MTL_RX_OVERFLOW_INT, |
| 296 | ioaddr + MTL_CHAN_INT_CTRL(STMMAC_CHAN0)); |
| 297 | ret = CORE_IRQ_MTL_RX_OVERFLOW; |
| 298 | } |
| 299 | } |
| 300 | |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 301 | dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x); |
| 302 | if (intr_status & PCS_RGSMIIIS_IRQ) |
| 303 | dwmac4_phystatus(ioaddr, x); |
| 304 | |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 305 | return ret; |
| 306 | } |
| 307 | |
| 308 | static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x) |
| 309 | { |
| 310 | u32 value; |
| 311 | |
| 312 | /* Currently only channel 0 is supported */ |
| 313 | value = readl(ioaddr + MTL_CHAN_TX_DEBUG(STMMAC_CHAN0)); |
| 314 | |
| 315 | if (value & MTL_DEBUG_TXSTSFSTS) |
| 316 | x->mtl_tx_status_fifo_full++; |
| 317 | if (value & MTL_DEBUG_TXFSTS) |
| 318 | x->mtl_tx_fifo_not_empty++; |
| 319 | if (value & MTL_DEBUG_TWCSTS) |
| 320 | x->mmtl_fifo_ctrl++; |
| 321 | if (value & MTL_DEBUG_TRCSTS_MASK) { |
| 322 | u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK) |
| 323 | >> MTL_DEBUG_TRCSTS_SHIFT; |
| 324 | if (trcsts == MTL_DEBUG_TRCSTS_WRITE) |
| 325 | x->mtl_tx_fifo_read_ctrl_write++; |
| 326 | else if (trcsts == MTL_DEBUG_TRCSTS_TXW) |
| 327 | x->mtl_tx_fifo_read_ctrl_wait++; |
| 328 | else if (trcsts == MTL_DEBUG_TRCSTS_READ) |
| 329 | x->mtl_tx_fifo_read_ctrl_read++; |
| 330 | else |
| 331 | x->mtl_tx_fifo_read_ctrl_idle++; |
| 332 | } |
| 333 | if (value & MTL_DEBUG_TXPAUSED) |
| 334 | x->mac_tx_in_pause++; |
| 335 | |
| 336 | value = readl(ioaddr + MTL_CHAN_RX_DEBUG(STMMAC_CHAN0)); |
| 337 | |
| 338 | if (value & MTL_DEBUG_RXFSTS_MASK) { |
| 339 | u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK) |
| 340 | >> MTL_DEBUG_RRCSTS_SHIFT; |
| 341 | |
| 342 | if (rxfsts == MTL_DEBUG_RXFSTS_FULL) |
| 343 | x->mtl_rx_fifo_fill_level_full++; |
| 344 | else if (rxfsts == MTL_DEBUG_RXFSTS_AT) |
| 345 | x->mtl_rx_fifo_fill_above_thresh++; |
| 346 | else if (rxfsts == MTL_DEBUG_RXFSTS_BT) |
| 347 | x->mtl_rx_fifo_fill_below_thresh++; |
| 348 | else |
| 349 | x->mtl_rx_fifo_fill_level_empty++; |
| 350 | } |
| 351 | if (value & MTL_DEBUG_RRCSTS_MASK) { |
| 352 | u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >> |
| 353 | MTL_DEBUG_RRCSTS_SHIFT; |
| 354 | |
| 355 | if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH) |
| 356 | x->mtl_rx_fifo_read_ctrl_flush++; |
| 357 | else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT) |
| 358 | x->mtl_rx_fifo_read_ctrl_read_data++; |
| 359 | else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA) |
| 360 | x->mtl_rx_fifo_read_ctrl_status++; |
| 361 | else |
| 362 | x->mtl_rx_fifo_read_ctrl_idle++; |
| 363 | } |
| 364 | if (value & MTL_DEBUG_RWCSTS) |
| 365 | x->mtl_rx_fifo_ctrl_active++; |
| 366 | |
| 367 | /* GMAC debug */ |
| 368 | value = readl(ioaddr + GMAC_DEBUG); |
| 369 | |
| 370 | if (value & GMAC_DEBUG_TFCSTS_MASK) { |
| 371 | u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK) |
| 372 | >> GMAC_DEBUG_TFCSTS_SHIFT; |
| 373 | |
| 374 | if (tfcsts == GMAC_DEBUG_TFCSTS_XFER) |
| 375 | x->mac_tx_frame_ctrl_xfer++; |
| 376 | else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE) |
| 377 | x->mac_tx_frame_ctrl_pause++; |
| 378 | else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT) |
| 379 | x->mac_tx_frame_ctrl_wait++; |
| 380 | else |
| 381 | x->mac_tx_frame_ctrl_idle++; |
| 382 | } |
| 383 | if (value & GMAC_DEBUG_TPESTS) |
| 384 | x->mac_gmii_tx_proto_engine++; |
| 385 | if (value & GMAC_DEBUG_RFCFCSTS_MASK) |
| 386 | x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK) |
| 387 | >> GMAC_DEBUG_RFCFCSTS_SHIFT; |
| 388 | if (value & GMAC_DEBUG_RPESTS) |
| 389 | x->mac_gmii_rx_proto_engine++; |
| 390 | } |
| 391 | |
| 392 | static const struct stmmac_ops dwmac4_ops = { |
| 393 | .core_init = dwmac4_core_init, |
| 394 | .rx_ipc = dwmac4_rx_ipc_enable, |
| 395 | .dump_regs = dwmac4_dump_regs, |
| 396 | .host_irq_status = dwmac4_irq_status, |
| 397 | .flow_ctrl = dwmac4_flow_ctrl, |
| 398 | .pmt = dwmac4_pmt, |
| 399 | .set_umac_addr = dwmac4_set_umac_addr, |
| 400 | .get_umac_addr = dwmac4_get_umac_addr, |
Giuseppe CAVALLARO | 70523e63 | 2016-06-24 15:16:24 +0200 | [diff] [blame] | 401 | .pcs_ctrl_ane = dwmac4_ctrl_ane, |
| 402 | .pcs_rane = dwmac4_rane, |
| 403 | .pcs_get_adv_lp = dwmac4_get_adv_lp, |
Alexandre TORGUE | 477286b | 2016-04-01 11:37:31 +0200 | [diff] [blame] | 404 | .debug = dwmac4_debug, |
| 405 | .set_filter = dwmac4_set_filter, |
| 406 | }; |
| 407 | |
| 408 | struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins, |
| 409 | int perfect_uc_entries, int *synopsys_id) |
| 410 | { |
| 411 | struct mac_device_info *mac; |
| 412 | u32 hwid = readl(ioaddr + GMAC_VERSION); |
| 413 | |
| 414 | mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL); |
| 415 | if (!mac) |
| 416 | return NULL; |
| 417 | |
| 418 | mac->pcsr = ioaddr; |
| 419 | mac->multicast_filter_bins = mcbins; |
| 420 | mac->unicast_filter_entries = perfect_uc_entries; |
| 421 | mac->mcast_bits_log2 = 0; |
| 422 | |
| 423 | if (mac->multicast_filter_bins) |
| 424 | mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins); |
| 425 | |
| 426 | mac->mac = &dwmac4_ops; |
| 427 | |
| 428 | mac->link.port = GMAC_CONFIG_PS; |
| 429 | mac->link.duplex = GMAC_CONFIG_DM; |
| 430 | mac->link.speed = GMAC_CONFIG_FES; |
| 431 | mac->mii.addr = GMAC_MDIO_ADDR; |
| 432 | mac->mii.data = GMAC_MDIO_DATA; |
| 433 | |
| 434 | /* Get and dump the chip ID */ |
| 435 | *synopsys_id = stmmac_get_synopsys_id(hwid); |
| 436 | |
| 437 | if (*synopsys_id > DWMAC_CORE_4_00) |
| 438 | mac->dma = &dwmac410_dma_ops; |
| 439 | else |
| 440 | mac->dma = &dwmac4_dma_ops; |
| 441 | |
| 442 | return mac; |
| 443 | } |