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gerrit-public.fairphone.software / kernel / msm-4.9 / fc1e2c8ea85e109acf09e74789e9b852f6eed251 / . / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c
blob: 5bd2cbaf582de4a93f59fc4e13ed10216c582b53 [file] [log] [blame]
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]1/*
Sujith Manoharan5b681382011-05-17 13:36:18 +0530[diff] [blame]2 * Copyright (c) 2010-2011 Atheros Communications Inc.
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]17#include <asm/unaligned.h>
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]18#include "hw.h"
19#include "ar9003_phy.h"
20#include "ar9003_eeprom.h"
Rajkumar Manoharane82cb032012-10-12 14:07:25 +0530[diff] [blame]21#include "ar9003_mci.h"
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]22
23#define COMP_HDR_LEN 4
24#define COMP_CKSUM_LEN 2
25
Joe Perches1b5c8d62014-03-12 10:22:38 -0700[diff] [blame]26#define LE16(x) cpu_to_le16(x)
27#define LE32(x) cpu_to_le32(x)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]28
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]29/* Local defines to distinguish between extension and control CTL's */
30#define EXT_ADDITIVE (0x8000)
31#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
32#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
33#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]34
35#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
36#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
37
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]38#define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
39
Vasanthakumar Thiagarajand0ce2d12010-12-21 01:42:43 -0800[diff] [blame]40#define EEPROM_DATA_LEN_9485 1088
41
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]42static int ar9003_hw_power_interpolate(int32_t x,
43 int32_t *px, int32_t *py, u_int16_t np);
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]44
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]45static const struct ar9300_eeprom ar9300_default = {
46 .eepromVersion = 2,
47 .templateVersion = 2,
Senthil Balasubramanianb503c7a2011-08-19 18:43:06 +0530[diff] [blame]48 .macAddr = {0, 2, 3, 4, 5, 6},
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]49 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
50 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
51 .baseEepHeader = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]52 .regDmn = { LE16(0), LE16(0x1f) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]53 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
54 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]55 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]56 .eepMisc = 0,
57 },
58 .rfSilent = 0,
59 .blueToothOptions = 0,
60 .deviceCap = 0,
61 .deviceType = 5, /* takes lower byte in eeprom location */
62 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
63 .params_for_tuning_caps = {0, 0},
64 .featureEnable = 0x0c,
65 /*
66 * bit0 - enable tx temp comp - disabled
67 * bit1 - enable tx volt comp - disabled
68 * bit2 - enable fastClock - enabled
69 * bit3 - enable doubling - enabled
70 * bit4 - enable internal regulator - disabled
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]71 * bit5 - enable pa predistortion - disabled
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]72 */
73 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
74 .eepromWriteEnableGpio = 3,
75 .wlanDisableGpio = 0,
76 .wlanLedGpio = 8,
77 .rxBandSelectGpio = 0xff,
78 .txrxgain = 0,
79 .swreg = 0,
80 },
81 .modalHeader2G = {
82 /* ar9300_modal_eep_header 2g */
83 /* 4 idle,t1,t2,b(4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]84 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]85 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]86 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]87
88 /*
89 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
90 * rx1, rx12, b (2 bits each)
91 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]92 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]93
94 /*
95 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
96 * for ar9280 (0xa20c/b20c 5:0)
97 */
98 .xatten1DB = {0, 0, 0},
99
100 /*
101 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
102 * for ar9280 (0xa20c/b20c 16:12
103 */
104 .xatten1Margin = {0, 0, 0},
105 .tempSlope = 36,
106 .voltSlope = 0,
107
108 /*
109 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
110 * channels in usual fbin coding format
111 */
112 .spurChans = {0, 0, 0, 0, 0},
113
114 /*
115 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
116 * if the register is per chain
117 */
118 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]119 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
120 .quick_drop = 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]121 .xpaBiasLvl = 0,
122 .txFrameToDataStart = 0x0e,
123 .txFrameToPaOn = 0x0e,
124 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
125 .antennaGain = 0,
126 .switchSettling = 0x2c,
127 .adcDesiredSize = -30,
128 .txEndToXpaOff = 0,
129 .txEndToRxOn = 0x2,
130 .txFrameToXpaOn = 0xe,
131 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]132 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
133 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Sujith Manoharan66a80a32013-12-18 09:53:21 +0530[diff] [blame]134 .switchcomspdt = 0,
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]135 .xlna_bias_strength = 0,
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]136 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]137 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]138 },
139 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]140 .base_ext1 = {
141 .ant_div_control = 0,
Sujith Manoharanee65b382013-12-18 09:53:22 +0530[diff] [blame]142 .future = {0, 0},
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]143 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]144 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]145 .calFreqPier2G = {
146 FREQ2FBIN(2412, 1),
147 FREQ2FBIN(2437, 1),
148 FREQ2FBIN(2472, 1),
149 },
150 /* ar9300_cal_data_per_freq_op_loop 2g */
151 .calPierData2G = {
152 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
153 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
154 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
155 },
156 .calTarget_freqbin_Cck = {
157 FREQ2FBIN(2412, 1),
158 FREQ2FBIN(2484, 1),
159 },
160 .calTarget_freqbin_2G = {
161 FREQ2FBIN(2412, 1),
162 FREQ2FBIN(2437, 1),
163 FREQ2FBIN(2472, 1)
164 },
165 .calTarget_freqbin_2GHT20 = {
166 FREQ2FBIN(2412, 1),
167 FREQ2FBIN(2437, 1),
168 FREQ2FBIN(2472, 1)
169 },
170 .calTarget_freqbin_2GHT40 = {
171 FREQ2FBIN(2412, 1),
172 FREQ2FBIN(2437, 1),
173 FREQ2FBIN(2472, 1)
174 },
175 .calTargetPowerCck = {
176 /* 1L-5L,5S,11L,11S */
177 { {36, 36, 36, 36} },
178 { {36, 36, 36, 36} },
179 },
180 .calTargetPower2G = {
181 /* 6-24,36,48,54 */
182 { {32, 32, 28, 24} },
183 { {32, 32, 28, 24} },
184 { {32, 32, 28, 24} },
185 },
186 .calTargetPower2GHT20 = {
187 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
188 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
189 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
190 },
191 .calTargetPower2GHT40 = {
192 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
193 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
194 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
195 },
196 .ctlIndex_2G = {
197 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
198 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
199 },
200 .ctl_freqbin_2G = {
201 {
202 FREQ2FBIN(2412, 1),
203 FREQ2FBIN(2417, 1),
204 FREQ2FBIN(2457, 1),
205 FREQ2FBIN(2462, 1)
206 },
207 {
208 FREQ2FBIN(2412, 1),
209 FREQ2FBIN(2417, 1),
210 FREQ2FBIN(2462, 1),
211 0xFF,
212 },
213
214 {
215 FREQ2FBIN(2412, 1),
216 FREQ2FBIN(2417, 1),
217 FREQ2FBIN(2462, 1),
218 0xFF,
219 },
220 {
221 FREQ2FBIN(2422, 1),
222 FREQ2FBIN(2427, 1),
223 FREQ2FBIN(2447, 1),
224 FREQ2FBIN(2452, 1)
225 },
226
227 {
228 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
229 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
230 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
231 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
232 },
233
234 {
235 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
236 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
237 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
238 0,
239 },
240
241 {
242 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
243 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
244 FREQ2FBIN(2472, 1),
245 0,
246 },
247
248 {
249 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
250 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
251 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
252 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
253 },
254
255 {
256 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
257 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
258 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
259 },
260
261 {
262 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
263 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
264 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
265 0
266 },
267
268 {
269 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
270 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
271 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
272 0
273 },
274
275 {
276 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
277 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
278 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]279 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]280 }
281 },
282 .ctlPowerData_2G = {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]283 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
284 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
285 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]286
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]287 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]288 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
289 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]290
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]291 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
292 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
293 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]294
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]295 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
296 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
297 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]298 },
299 .modalHeader5G = {
300 /* 4 idle,t1,t2,b (4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]301 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]302 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]303 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]304 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
305 .antCtrlChain = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]306 LE16(0x000), LE16(0x000), LE16(0x000),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]307 },
308 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
309 .xatten1DB = {0, 0, 0},
310
311 /*
312 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
313 * for merlin (0xa20c/b20c 16:12
314 */
315 .xatten1Margin = {0, 0, 0},
316 .tempSlope = 68,
317 .voltSlope = 0,
318 /* spurChans spur channels in usual fbin coding format */
319 .spurChans = {0, 0, 0, 0, 0},
320 /* noiseFloorThreshCh Check if the register is per chain */
321 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]322 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
323 .quick_drop = 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]324 .xpaBiasLvl = 0,
325 .txFrameToDataStart = 0x0e,
326 .txFrameToPaOn = 0x0e,
327 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
328 .antennaGain = 0,
329 .switchSettling = 0x2d,
330 .adcDesiredSize = -30,
331 .txEndToXpaOff = 0,
332 .txEndToRxOn = 0x2,
333 .txFrameToXpaOn = 0xe,
334 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]335 .papdRateMaskHt20 = LE32(0x0c80c080),
336 .papdRateMaskHt40 = LE32(0x0080c080),
Sujith Manoharan66a80a32013-12-18 09:53:21 +0530[diff] [blame]337 .switchcomspdt = 0,
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]338 .xlna_bias_strength = 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]339 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]340 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]341 },
342 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]343 .base_ext2 = {
344 .tempSlopeLow = 0,
345 .tempSlopeHigh = 0,
346 .xatten1DBLow = {0, 0, 0},
347 .xatten1MarginLow = {0, 0, 0},
348 .xatten1DBHigh = {0, 0, 0},
349 .xatten1MarginHigh = {0, 0, 0}
350 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]351 .calFreqPier5G = {
352 FREQ2FBIN(5180, 0),
353 FREQ2FBIN(5220, 0),
354 FREQ2FBIN(5320, 0),
355 FREQ2FBIN(5400, 0),
356 FREQ2FBIN(5500, 0),
357 FREQ2FBIN(5600, 0),
358 FREQ2FBIN(5725, 0),
359 FREQ2FBIN(5825, 0)
360 },
361 .calPierData5G = {
362 {
363 {0, 0, 0, 0, 0},
364 {0, 0, 0, 0, 0},
365 {0, 0, 0, 0, 0},
366 {0, 0, 0, 0, 0},
367 {0, 0, 0, 0, 0},
368 {0, 0, 0, 0, 0},
369 {0, 0, 0, 0, 0},
370 {0, 0, 0, 0, 0},
371 },
372 {
373 {0, 0, 0, 0, 0},
374 {0, 0, 0, 0, 0},
375 {0, 0, 0, 0, 0},
376 {0, 0, 0, 0, 0},
377 {0, 0, 0, 0, 0},
378 {0, 0, 0, 0, 0},
379 {0, 0, 0, 0, 0},
380 {0, 0, 0, 0, 0},
381 },
382 {
383 {0, 0, 0, 0, 0},
384 {0, 0, 0, 0, 0},
385 {0, 0, 0, 0, 0},
386 {0, 0, 0, 0, 0},
387 {0, 0, 0, 0, 0},
388 {0, 0, 0, 0, 0},
389 {0, 0, 0, 0, 0},
390 {0, 0, 0, 0, 0},
391 },
392
393 },
394 .calTarget_freqbin_5G = {
395 FREQ2FBIN(5180, 0),
396 FREQ2FBIN(5220, 0),
397 FREQ2FBIN(5320, 0),
398 FREQ2FBIN(5400, 0),
399 FREQ2FBIN(5500, 0),
400 FREQ2FBIN(5600, 0),
401 FREQ2FBIN(5725, 0),
402 FREQ2FBIN(5825, 0)
403 },
404 .calTarget_freqbin_5GHT20 = {
405 FREQ2FBIN(5180, 0),
406 FREQ2FBIN(5240, 0),
407 FREQ2FBIN(5320, 0),
408 FREQ2FBIN(5500, 0),
409 FREQ2FBIN(5700, 0),
410 FREQ2FBIN(5745, 0),
411 FREQ2FBIN(5725, 0),
412 FREQ2FBIN(5825, 0)
413 },
414 .calTarget_freqbin_5GHT40 = {
415 FREQ2FBIN(5180, 0),
416 FREQ2FBIN(5240, 0),
417 FREQ2FBIN(5320, 0),
418 FREQ2FBIN(5500, 0),
419 FREQ2FBIN(5700, 0),
420 FREQ2FBIN(5745, 0),
421 FREQ2FBIN(5725, 0),
422 FREQ2FBIN(5825, 0)
423 },
424 .calTargetPower5G = {
425 /* 6-24,36,48,54 */
426 { {20, 20, 20, 10} },
427 { {20, 20, 20, 10} },
428 { {20, 20, 20, 10} },
429 { {20, 20, 20, 10} },
430 { {20, 20, 20, 10} },
431 { {20, 20, 20, 10} },
432 { {20, 20, 20, 10} },
433 { {20, 20, 20, 10} },
434 },
435 .calTargetPower5GHT20 = {
436 /*
437 * 0_8_16,1-3_9-11_17-19,
438 * 4,5,6,7,12,13,14,15,20,21,22,23
439 */
440 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
441 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
442 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
443 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
444 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
445 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
446 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
447 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
448 },
449 .calTargetPower5GHT40 = {
450 /*
451 * 0_8_16,1-3_9-11_17-19,
452 * 4,5,6,7,12,13,14,15,20,21,22,23
453 */
454 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
455 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
457 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
458 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
460 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
461 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
462 },
463 .ctlIndex_5G = {
464 0x10, 0x16, 0x18, 0x40, 0x46,
465 0x48, 0x30, 0x36, 0x38
466 },
467 .ctl_freqbin_5G = {
468 {
469 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
470 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
471 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
472 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
473 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
474 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
475 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
476 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
477 },
478 {
479 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
480 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
481 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
482 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
483 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
484 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
485 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
486 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
487 },
488
489 {
490 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
491 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
492 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
493 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
494 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
495 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
496 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
497 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
498 },
499
500 {
501 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
502 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
503 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
504 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
505 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
506 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
507 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
508 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
509 },
510
511 {
512 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
513 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
514 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
515 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
516 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
517 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
518 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
519 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
520 },
521
522 {
523 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
524 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
525 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
526 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
527 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
528 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
529 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
530 /* Data[5].ctlEdges[7].bChannel */ 0xFF
531 },
532
533 {
534 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
535 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
536 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
537 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
538 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
539 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
540 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
541 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
542 },
543
544 {
545 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
546 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
547 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
548 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
549 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
550 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
551 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
552 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
553 },
554
555 {
556 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
557 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
558 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
559 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
560 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
561 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
562 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
563 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
564 }
565 },
566 .ctlPowerData_5G = {
567 {
568 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]569 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
570 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]571 }
572 },
573 {
574 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]575 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
576 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]577 }
578 },
579 {
580 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]581 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
582 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]583 }
584 },
585 {
586 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]587 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
588 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]589 }
590 },
591 {
592 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]593 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
594 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]595 }
596 },
597 {
598 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]599 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
600 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]601 }
602 },
603 {
604 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]605 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
606 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]607 }
608 },
609 {
610 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]611 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
612 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]613 }
614 },
615 {
616 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]617 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
618 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]619 }
620 },
621 }
622};
623
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]624static const struct ar9300_eeprom ar9300_x113 = {
625 .eepromVersion = 2,
626 .templateVersion = 6,
627 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
628 .custData = {"x113-023-f0000"},
629 .baseEepHeader = {
630 .regDmn = { LE16(0), LE16(0x1f) },
631 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
632 .opCapFlags = {
Luis R. Rodriguez9ba7f4f2011-05-11 14:57:26 -0700[diff] [blame]633 .opFlags = AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]634 .eepMisc = 0,
635 },
636 .rfSilent = 0,
637 .blueToothOptions = 0,
638 .deviceCap = 0,
639 .deviceType = 5, /* takes lower byte in eeprom location */
640 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
641 .params_for_tuning_caps = {0, 0},
642 .featureEnable = 0x0d,
643 /*
644 * bit0 - enable tx temp comp - disabled
645 * bit1 - enable tx volt comp - disabled
646 * bit2 - enable fastClock - enabled
647 * bit3 - enable doubling - enabled
648 * bit4 - enable internal regulator - disabled
649 * bit5 - enable pa predistortion - disabled
650 */
651 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
652 .eepromWriteEnableGpio = 6,
653 .wlanDisableGpio = 0,
654 .wlanLedGpio = 8,
655 .rxBandSelectGpio = 0xff,
656 .txrxgain = 0x21,
657 .swreg = 0,
658 },
659 .modalHeader2G = {
660 /* ar9300_modal_eep_header 2g */
661 /* 4 idle,t1,t2,b(4 bits per setting) */
662 .antCtrlCommon = LE32(0x110),
663 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
664 .antCtrlCommon2 = LE32(0x44444),
665
666 /*
667 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
668 * rx1, rx12, b (2 bits each)
669 */
670 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
671
672 /*
673 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
674 * for ar9280 (0xa20c/b20c 5:0)
675 */
676 .xatten1DB = {0, 0, 0},
677
678 /*
679 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
680 * for ar9280 (0xa20c/b20c 16:12
681 */
682 .xatten1Margin = {0, 0, 0},
683 .tempSlope = 25,
684 .voltSlope = 0,
685
686 /*
687 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
688 * channels in usual fbin coding format
689 */
690 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
691
692 /*
693 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
694 * if the register is per chain
695 */
696 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]697 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
698 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]699 .xpaBiasLvl = 0,
700 .txFrameToDataStart = 0x0e,
701 .txFrameToPaOn = 0x0e,
702 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
703 .antennaGain = 0,
704 .switchSettling = 0x2c,
705 .adcDesiredSize = -30,
706 .txEndToXpaOff = 0,
707 .txEndToRxOn = 0x2,
708 .txFrameToXpaOn = 0xe,
709 .thresh62 = 28,
710 .papdRateMaskHt20 = LE32(0x0c80c080),
711 .papdRateMaskHt40 = LE32(0x0080c080),
Sujith Manoharan66a80a32013-12-18 09:53:21 +0530[diff] [blame]712 .switchcomspdt = 0,
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]713 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]714 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]715 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]716 },
717 },
718 .base_ext1 = {
719 .ant_div_control = 0,
Sujith Manoharanee65b382013-12-18 09:53:22 +0530[diff] [blame]720 .future = {0, 0},
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]721 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]722 },
723 .calFreqPier2G = {
724 FREQ2FBIN(2412, 1),
725 FREQ2FBIN(2437, 1),
726 FREQ2FBIN(2472, 1),
727 },
728 /* ar9300_cal_data_per_freq_op_loop 2g */
729 .calPierData2G = {
730 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
731 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
732 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
733 },
734 .calTarget_freqbin_Cck = {
735 FREQ2FBIN(2412, 1),
736 FREQ2FBIN(2472, 1),
737 },
738 .calTarget_freqbin_2G = {
739 FREQ2FBIN(2412, 1),
740 FREQ2FBIN(2437, 1),
741 FREQ2FBIN(2472, 1)
742 },
743 .calTarget_freqbin_2GHT20 = {
744 FREQ2FBIN(2412, 1),
745 FREQ2FBIN(2437, 1),
746 FREQ2FBIN(2472, 1)
747 },
748 .calTarget_freqbin_2GHT40 = {
749 FREQ2FBIN(2412, 1),
750 FREQ2FBIN(2437, 1),
751 FREQ2FBIN(2472, 1)
752 },
753 .calTargetPowerCck = {
754 /* 1L-5L,5S,11L,11S */
755 { {34, 34, 34, 34} },
756 { {34, 34, 34, 34} },
757 },
758 .calTargetPower2G = {
759 /* 6-24,36,48,54 */
760 { {34, 34, 32, 32} },
761 { {34, 34, 32, 32} },
762 { {34, 34, 32, 32} },
763 },
764 .calTargetPower2GHT20 = {
765 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
766 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
767 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
768 },
769 .calTargetPower2GHT40 = {
770 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
771 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
772 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
773 },
774 .ctlIndex_2G = {
775 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
776 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
777 },
778 .ctl_freqbin_2G = {
779 {
780 FREQ2FBIN(2412, 1),
781 FREQ2FBIN(2417, 1),
782 FREQ2FBIN(2457, 1),
783 FREQ2FBIN(2462, 1)
784 },
785 {
786 FREQ2FBIN(2412, 1),
787 FREQ2FBIN(2417, 1),
788 FREQ2FBIN(2462, 1),
789 0xFF,
790 },
791
792 {
793 FREQ2FBIN(2412, 1),
794 FREQ2FBIN(2417, 1),
795 FREQ2FBIN(2462, 1),
796 0xFF,
797 },
798 {
799 FREQ2FBIN(2422, 1),
800 FREQ2FBIN(2427, 1),
801 FREQ2FBIN(2447, 1),
802 FREQ2FBIN(2452, 1)
803 },
804
805 {
806 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
807 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
808 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
809 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
810 },
811
812 {
813 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
814 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
815 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
816 0,
817 },
818
819 {
820 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
821 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
822 FREQ2FBIN(2472, 1),
823 0,
824 },
825
826 {
827 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
828 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
829 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
830 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
831 },
832
833 {
834 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
835 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
836 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
837 },
838
839 {
840 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
841 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
842 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
843 0
844 },
845
846 {
847 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
848 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
849 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
850 0
851 },
852
853 {
854 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
855 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
856 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
857 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
858 }
859 },
860 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]861 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
862 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
863 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]864
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]865 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]866 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
867 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]868
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]869 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
870 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
871 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]872
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]873 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
874 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
875 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]876 },
877 .modalHeader5G = {
878 /* 4 idle,t1,t2,b (4 bits per setting) */
879 .antCtrlCommon = LE32(0x220),
880 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
881 .antCtrlCommon2 = LE32(0x11111),
882 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
883 .antCtrlChain = {
884 LE16(0x150), LE16(0x150), LE16(0x150),
885 },
886 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
887 .xatten1DB = {0, 0, 0},
888
889 /*
890 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
891 * for merlin (0xa20c/b20c 16:12
892 */
893 .xatten1Margin = {0, 0, 0},
894 .tempSlope = 68,
895 .voltSlope = 0,
896 /* spurChans spur channels in usual fbin coding format */
897 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
898 /* noiseFloorThreshCh Check if the register is per chain */
899 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]900 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
901 .quick_drop = 0,
Senthil Balasubramanianbe0e6aa2011-05-12 16:24:28 +0530[diff] [blame]902 .xpaBiasLvl = 0xf,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]903 .txFrameToDataStart = 0x0e,
904 .txFrameToPaOn = 0x0e,
905 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
906 .antennaGain = 0,
907 .switchSettling = 0x2d,
908 .adcDesiredSize = -30,
909 .txEndToXpaOff = 0,
910 .txEndToRxOn = 0x2,
911 .txFrameToXpaOn = 0xe,
912 .thresh62 = 28,
913 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
914 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Sujith Manoharan66a80a32013-12-18 09:53:21 +0530[diff] [blame]915 .switchcomspdt = 0,
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]916 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]917 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]918 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]919 },
920 },
921 .base_ext2 = {
922 .tempSlopeLow = 72,
923 .tempSlopeHigh = 105,
924 .xatten1DBLow = {0, 0, 0},
925 .xatten1MarginLow = {0, 0, 0},
926 .xatten1DBHigh = {0, 0, 0},
927 .xatten1MarginHigh = {0, 0, 0}
928 },
929 .calFreqPier5G = {
930 FREQ2FBIN(5180, 0),
931 FREQ2FBIN(5240, 0),
932 FREQ2FBIN(5320, 0),
933 FREQ2FBIN(5400, 0),
934 FREQ2FBIN(5500, 0),
935 FREQ2FBIN(5600, 0),
936 FREQ2FBIN(5745, 0),
937 FREQ2FBIN(5785, 0)
938 },
939 .calPierData5G = {
940 {
941 {0, 0, 0, 0, 0},
942 {0, 0, 0, 0, 0},
943 {0, 0, 0, 0, 0},
944 {0, 0, 0, 0, 0},
945 {0, 0, 0, 0, 0},
946 {0, 0, 0, 0, 0},
947 {0, 0, 0, 0, 0},
948 {0, 0, 0, 0, 0},
949 },
950 {
951 {0, 0, 0, 0, 0},
952 {0, 0, 0, 0, 0},
953 {0, 0, 0, 0, 0},
954 {0, 0, 0, 0, 0},
955 {0, 0, 0, 0, 0},
956 {0, 0, 0, 0, 0},
957 {0, 0, 0, 0, 0},
958 {0, 0, 0, 0, 0},
959 },
960 {
961 {0, 0, 0, 0, 0},
962 {0, 0, 0, 0, 0},
963 {0, 0, 0, 0, 0},
964 {0, 0, 0, 0, 0},
965 {0, 0, 0, 0, 0},
966 {0, 0, 0, 0, 0},
967 {0, 0, 0, 0, 0},
968 {0, 0, 0, 0, 0},
969 },
970
971 },
972 .calTarget_freqbin_5G = {
973 FREQ2FBIN(5180, 0),
974 FREQ2FBIN(5220, 0),
975 FREQ2FBIN(5320, 0),
976 FREQ2FBIN(5400, 0),
977 FREQ2FBIN(5500, 0),
978 FREQ2FBIN(5600, 0),
979 FREQ2FBIN(5745, 0),
980 FREQ2FBIN(5785, 0)
981 },
982 .calTarget_freqbin_5GHT20 = {
983 FREQ2FBIN(5180, 0),
984 FREQ2FBIN(5240, 0),
985 FREQ2FBIN(5320, 0),
986 FREQ2FBIN(5400, 0),
987 FREQ2FBIN(5500, 0),
988 FREQ2FBIN(5700, 0),
989 FREQ2FBIN(5745, 0),
990 FREQ2FBIN(5825, 0)
991 },
992 .calTarget_freqbin_5GHT40 = {
993 FREQ2FBIN(5190, 0),
994 FREQ2FBIN(5230, 0),
995 FREQ2FBIN(5320, 0),
996 FREQ2FBIN(5410, 0),
997 FREQ2FBIN(5510, 0),
998 FREQ2FBIN(5670, 0),
999 FREQ2FBIN(5755, 0),
1000 FREQ2FBIN(5825, 0)
1001 },
1002 .calTargetPower5G = {
1003 /* 6-24,36,48,54 */
1004 { {42, 40, 40, 34} },
1005 { {42, 40, 40, 34} },
1006 { {42, 40, 40, 34} },
1007 { {42, 40, 40, 34} },
1008 { {42, 40, 40, 34} },
1009 { {42, 40, 40, 34} },
1010 { {42, 40, 40, 34} },
1011 { {42, 40, 40, 34} },
1012 },
1013 .calTargetPower5GHT20 = {
1014 /*
1015 * 0_8_16,1-3_9-11_17-19,
1016 * 4,5,6,7,12,13,14,15,20,21,22,23
1017 */
1018 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1019 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1020 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1021 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1022 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1023 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1024 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1025 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1026 },
1027 .calTargetPower5GHT40 = {
1028 /*
1029 * 0_8_16,1-3_9-11_17-19,
1030 * 4,5,6,7,12,13,14,15,20,21,22,23
1031 */
1032 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1033 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1034 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1035 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1036 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1037 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1038 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1039 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1040 },
1041 .ctlIndex_5G = {
1042 0x10, 0x16, 0x18, 0x40, 0x46,
1043 0x48, 0x30, 0x36, 0x38
1044 },
1045 .ctl_freqbin_5G = {
1046 {
1047 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1048 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1049 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1050 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1051 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1052 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1053 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1054 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1055 },
1056 {
1057 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1058 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1059 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1060 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1061 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1062 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1063 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1064 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1065 },
1066
1067 {
1068 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1069 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1070 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1071 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1072 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1073 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1074 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1075 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1076 },
1077
1078 {
1079 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1080 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1081 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1082 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1083 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1084 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1085 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1086 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1087 },
1088
1089 {
1090 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1091 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1092 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1093 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1094 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1095 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1096 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1097 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1098 },
1099
1100 {
1101 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1102 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1103 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1104 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1105 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1106 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1107 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1108 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1109 },
1110
1111 {
1112 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1113 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1114 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1115 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1116 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1117 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1118 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1119 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1120 },
1121
1122 {
1123 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1124 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1125 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1126 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1127 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1128 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1129 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1130 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1131 },
1132
1133 {
1134 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1135 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1136 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1137 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1138 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1139 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1140 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1141 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1142 }
1143 },
1144 .ctlPowerData_5G = {
1145 {
1146 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1147 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1148 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1149 }
1150 },
1151 {
1152 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1153 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1154 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1155 }
1156 },
1157 {
1158 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1159 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1160 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1161 }
1162 },
1163 {
1164 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1165 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1166 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1167 }
1168 },
1169 {
1170 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1171 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1172 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1173 }
1174 },
1175 {
1176 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1177 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1178 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1179 }
1180 },
1181 {
1182 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1183 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1184 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1185 }
1186 },
1187 {
1188 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1189 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1190 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1191 }
1192 },
1193 {
1194 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1195 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1196 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1197 }
1198 },
1199 }
1200};
1201
1202
1203static const struct ar9300_eeprom ar9300_h112 = {
1204 .eepromVersion = 2,
1205 .templateVersion = 3,
1206 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1207 .custData = {"h112-241-f0000"},
1208 .baseEepHeader = {
1209 .regDmn = { LE16(0), LE16(0x1f) },
1210 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1211 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]1212 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1213 .eepMisc = 0,
1214 },
1215 .rfSilent = 0,
1216 .blueToothOptions = 0,
1217 .deviceCap = 0,
1218 .deviceType = 5, /* takes lower byte in eeprom location */
1219 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1220 .params_for_tuning_caps = {0, 0},
1221 .featureEnable = 0x0d,
1222 /*
1223 * bit0 - enable tx temp comp - disabled
1224 * bit1 - enable tx volt comp - disabled
1225 * bit2 - enable fastClock - enabled
1226 * bit3 - enable doubling - enabled
1227 * bit4 - enable internal regulator - disabled
1228 * bit5 - enable pa predistortion - disabled
1229 */
1230 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1231 .eepromWriteEnableGpio = 6,
1232 .wlanDisableGpio = 0,
1233 .wlanLedGpio = 8,
1234 .rxBandSelectGpio = 0xff,
1235 .txrxgain = 0x10,
1236 .swreg = 0,
1237 },
1238 .modalHeader2G = {
1239 /* ar9300_modal_eep_header 2g */
1240 /* 4 idle,t1,t2,b(4 bits per setting) */
1241 .antCtrlCommon = LE32(0x110),
1242 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1243 .antCtrlCommon2 = LE32(0x44444),
1244
1245 /*
1246 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1247 * rx1, rx12, b (2 bits each)
1248 */
1249 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1250
1251 /*
1252 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1253 * for ar9280 (0xa20c/b20c 5:0)
1254 */
1255 .xatten1DB = {0, 0, 0},
1256
1257 /*
1258 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1259 * for ar9280 (0xa20c/b20c 16:12
1260 */
1261 .xatten1Margin = {0, 0, 0},
1262 .tempSlope = 25,
1263 .voltSlope = 0,
1264
1265 /*
1266 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1267 * channels in usual fbin coding format
1268 */
1269 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1270
1271 /*
1272 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1273 * if the register is per chain
1274 */
1275 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]1276 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1277 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1278 .xpaBiasLvl = 0,
1279 .txFrameToDataStart = 0x0e,
1280 .txFrameToPaOn = 0x0e,
1281 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1282 .antennaGain = 0,
1283 .switchSettling = 0x2c,
1284 .adcDesiredSize = -30,
1285 .txEndToXpaOff = 0,
1286 .txEndToRxOn = 0x2,
1287 .txFrameToXpaOn = 0xe,
1288 .thresh62 = 28,
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1289 .papdRateMaskHt20 = LE32(0x0c80c080),
1290 .papdRateMaskHt40 = LE32(0x0080c080),
Sujith Manoharan66a80a32013-12-18 09:53:21 +0530[diff] [blame]1291 .switchcomspdt = 0,
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1292 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1293 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1294 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1295 },
1296 },
1297 .base_ext1 = {
1298 .ant_div_control = 0,
Sujith Manoharanee65b382013-12-18 09:53:22 +0530[diff] [blame]1299 .future = {0, 0},
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]1300 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1301 },
1302 .calFreqPier2G = {
1303 FREQ2FBIN(2412, 1),
1304 FREQ2FBIN(2437, 1),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1305 FREQ2FBIN(2462, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1306 },
1307 /* ar9300_cal_data_per_freq_op_loop 2g */
1308 .calPierData2G = {
1309 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1310 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1311 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1312 },
1313 .calTarget_freqbin_Cck = {
1314 FREQ2FBIN(2412, 1),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1315 FREQ2FBIN(2472, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1316 },
1317 .calTarget_freqbin_2G = {
1318 FREQ2FBIN(2412, 1),
1319 FREQ2FBIN(2437, 1),
1320 FREQ2FBIN(2472, 1)
1321 },
1322 .calTarget_freqbin_2GHT20 = {
1323 FREQ2FBIN(2412, 1),
1324 FREQ2FBIN(2437, 1),
1325 FREQ2FBIN(2472, 1)
1326 },
1327 .calTarget_freqbin_2GHT40 = {
1328 FREQ2FBIN(2412, 1),
1329 FREQ2FBIN(2437, 1),
1330 FREQ2FBIN(2472, 1)
1331 },
1332 .calTargetPowerCck = {
1333 /* 1L-5L,5S,11L,11S */
1334 { {34, 34, 34, 34} },
1335 { {34, 34, 34, 34} },
1336 },
1337 .calTargetPower2G = {
1338 /* 6-24,36,48,54 */
1339 { {34, 34, 32, 32} },
1340 { {34, 34, 32, 32} },
1341 { {34, 34, 32, 32} },
1342 },
1343 .calTargetPower2GHT20 = {
1344 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1345 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1346 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1347 },
1348 .calTargetPower2GHT40 = {
1349 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1350 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1351 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1352 },
1353 .ctlIndex_2G = {
1354 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1355 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1356 },
1357 .ctl_freqbin_2G = {
1358 {
1359 FREQ2FBIN(2412, 1),
1360 FREQ2FBIN(2417, 1),
1361 FREQ2FBIN(2457, 1),
1362 FREQ2FBIN(2462, 1)
1363 },
1364 {
1365 FREQ2FBIN(2412, 1),
1366 FREQ2FBIN(2417, 1),
1367 FREQ2FBIN(2462, 1),
1368 0xFF,
1369 },
1370
1371 {
1372 FREQ2FBIN(2412, 1),
1373 FREQ2FBIN(2417, 1),
1374 FREQ2FBIN(2462, 1),
1375 0xFF,
1376 },
1377 {
1378 FREQ2FBIN(2422, 1),
1379 FREQ2FBIN(2427, 1),
1380 FREQ2FBIN(2447, 1),
1381 FREQ2FBIN(2452, 1)
1382 },
1383
1384 {
1385 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1386 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1387 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1388 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1389 },
1390
1391 {
1392 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1393 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1394 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1395 0,
1396 },
1397
1398 {
1399 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1400 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1401 FREQ2FBIN(2472, 1),
1402 0,
1403 },
1404
1405 {
1406 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1407 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1408 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1409 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1410 },
1411
1412 {
1413 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1416 },
1417
1418 {
1419 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1420 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1421 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1422 0
1423 },
1424
1425 {
1426 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1427 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1428 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1429 0
1430 },
1431
1432 {
1433 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1434 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1435 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1436 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1437 }
1438 },
1439 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1440 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1441 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1442 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1443
Mohammed Shafi Shajakhan81dc6762011-06-17 11:07:32 +0530[diff] [blame]1444 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1445 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1446 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1447
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1448 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1449 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1450 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1451
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1452 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1453 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1454 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1455 },
1456 .modalHeader5G = {
1457 /* 4 idle,t1,t2,b (4 bits per setting) */
1458 .antCtrlCommon = LE32(0x220),
1459 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1460 .antCtrlCommon2 = LE32(0x44444),
1461 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1462 .antCtrlChain = {
1463 LE16(0x150), LE16(0x150), LE16(0x150),
1464 },
1465 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1466 .xatten1DB = {0, 0, 0},
1467
1468 /*
1469 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1470 * for merlin (0xa20c/b20c 16:12
1471 */
1472 .xatten1Margin = {0, 0, 0},
1473 .tempSlope = 45,
1474 .voltSlope = 0,
1475 /* spurChans spur channels in usual fbin coding format */
1476 .spurChans = {0, 0, 0, 0, 0},
1477 /* noiseFloorThreshCh Check if the register is per chain */
1478 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]1479 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1480 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1481 .xpaBiasLvl = 0,
1482 .txFrameToDataStart = 0x0e,
1483 .txFrameToPaOn = 0x0e,
1484 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1485 .antennaGain = 0,
1486 .switchSettling = 0x2d,
1487 .adcDesiredSize = -30,
1488 .txEndToXpaOff = 0,
1489 .txEndToRxOn = 0x2,
1490 .txFrameToXpaOn = 0xe,
1491 .thresh62 = 28,
1492 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1493 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Sujith Manoharan66a80a32013-12-18 09:53:21 +0530[diff] [blame]1494 .switchcomspdt = 0,
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1495 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1496 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1497 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1498 },
1499 },
1500 .base_ext2 = {
1501 .tempSlopeLow = 40,
1502 .tempSlopeHigh = 50,
1503 .xatten1DBLow = {0, 0, 0},
1504 .xatten1MarginLow = {0, 0, 0},
1505 .xatten1DBHigh = {0, 0, 0},
1506 .xatten1MarginHigh = {0, 0, 0}
1507 },
1508 .calFreqPier5G = {
1509 FREQ2FBIN(5180, 0),
1510 FREQ2FBIN(5220, 0),
1511 FREQ2FBIN(5320, 0),
1512 FREQ2FBIN(5400, 0),
1513 FREQ2FBIN(5500, 0),
1514 FREQ2FBIN(5600, 0),
1515 FREQ2FBIN(5700, 0),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1516 FREQ2FBIN(5785, 0)
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1517 },
1518 .calPierData5G = {
1519 {
1520 {0, 0, 0, 0, 0},
1521 {0, 0, 0, 0, 0},
1522 {0, 0, 0, 0, 0},
1523 {0, 0, 0, 0, 0},
1524 {0, 0, 0, 0, 0},
1525 {0, 0, 0, 0, 0},
1526 {0, 0, 0, 0, 0},
1527 {0, 0, 0, 0, 0},
1528 },
1529 {
1530 {0, 0, 0, 0, 0},
1531 {0, 0, 0, 0, 0},
1532 {0, 0, 0, 0, 0},
1533 {0, 0, 0, 0, 0},
1534 {0, 0, 0, 0, 0},
1535 {0, 0, 0, 0, 0},
1536 {0, 0, 0, 0, 0},
1537 {0, 0, 0, 0, 0},
1538 },
1539 {
1540 {0, 0, 0, 0, 0},
1541 {0, 0, 0, 0, 0},
1542 {0, 0, 0, 0, 0},
1543 {0, 0, 0, 0, 0},
1544 {0, 0, 0, 0, 0},
1545 {0, 0, 0, 0, 0},
1546 {0, 0, 0, 0, 0},
1547 {0, 0, 0, 0, 0},
1548 },
1549
1550 },
1551 .calTarget_freqbin_5G = {
1552 FREQ2FBIN(5180, 0),
1553 FREQ2FBIN(5240, 0),
1554 FREQ2FBIN(5320, 0),
1555 FREQ2FBIN(5400, 0),
1556 FREQ2FBIN(5500, 0),
1557 FREQ2FBIN(5600, 0),
1558 FREQ2FBIN(5700, 0),
1559 FREQ2FBIN(5825, 0)
1560 },
1561 .calTarget_freqbin_5GHT20 = {
1562 FREQ2FBIN(5180, 0),
1563 FREQ2FBIN(5240, 0),
1564 FREQ2FBIN(5320, 0),
1565 FREQ2FBIN(5400, 0),
1566 FREQ2FBIN(5500, 0),
1567 FREQ2FBIN(5700, 0),
1568 FREQ2FBIN(5745, 0),
1569 FREQ2FBIN(5825, 0)
1570 },
1571 .calTarget_freqbin_5GHT40 = {
1572 FREQ2FBIN(5180, 0),
1573 FREQ2FBIN(5240, 0),
1574 FREQ2FBIN(5320, 0),
1575 FREQ2FBIN(5400, 0),
1576 FREQ2FBIN(5500, 0),
1577 FREQ2FBIN(5700, 0),
1578 FREQ2FBIN(5745, 0),
1579 FREQ2FBIN(5825, 0)
1580 },
1581 .calTargetPower5G = {
1582 /* 6-24,36,48,54 */
1583 { {30, 30, 28, 24} },
1584 { {30, 30, 28, 24} },
1585 { {30, 30, 28, 24} },
1586 { {30, 30, 28, 24} },
1587 { {30, 30, 28, 24} },
1588 { {30, 30, 28, 24} },
1589 { {30, 30, 28, 24} },
1590 { {30, 30, 28, 24} },
1591 },
1592 .calTargetPower5GHT20 = {
1593 /*
1594 * 0_8_16,1-3_9-11_17-19,
1595 * 4,5,6,7,12,13,14,15,20,21,22,23
1596 */
1597 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1598 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1599 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1600 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1601 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1602 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1603 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1604 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1605 },
1606 .calTargetPower5GHT40 = {
1607 /*
1608 * 0_8_16,1-3_9-11_17-19,
1609 * 4,5,6,7,12,13,14,15,20,21,22,23
1610 */
1611 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1612 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1613 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1614 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1615 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1616 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1617 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1618 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1619 },
1620 .ctlIndex_5G = {
1621 0x10, 0x16, 0x18, 0x40, 0x46,
1622 0x48, 0x30, 0x36, 0x38
1623 },
1624 .ctl_freqbin_5G = {
1625 {
1626 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1627 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1628 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1629 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1630 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1631 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1632 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1633 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1634 },
1635 {
1636 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1637 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1638 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1639 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1640 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1641 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1642 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1643 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1644 },
1645
1646 {
1647 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1648 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1649 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1650 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1651 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1652 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1653 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1654 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1655 },
1656
1657 {
1658 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1659 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1660 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1661 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1662 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1663 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1664 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1665 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1666 },
1667
1668 {
1669 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1670 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1671 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1672 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1673 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1674 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1675 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1676 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1677 },
1678
1679 {
1680 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1681 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1682 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1683 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1684 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1685 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1686 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1687 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1688 },
1689
1690 {
1691 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1692 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1693 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1694 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1695 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1696 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1697 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1698 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1699 },
1700
1701 {
1702 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1703 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1704 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1705 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1706 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1707 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1708 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1709 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1710 },
1711
1712 {
1713 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1714 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1715 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1716 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1717 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1718 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1719 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1720 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1721 }
1722 },
1723 .ctlPowerData_5G = {
1724 {
1725 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1726 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1727 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1728 }
1729 },
1730 {
1731 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1732 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1733 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1734 }
1735 },
1736 {
1737 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1738 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1739 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1740 }
1741 },
1742 {
1743 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1744 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1745 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1746 }
1747 },
1748 {
1749 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1750 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1751 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1752 }
1753 },
1754 {
1755 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1756 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1757 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1758 }
1759 },
1760 {
1761 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1762 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1763 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1764 }
1765 },
1766 {
1767 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1768 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1769 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1770 }
1771 },
1772 {
1773 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1774 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1775 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1776 }
1777 },
1778 }
1779};
1780
1781
1782static const struct ar9300_eeprom ar9300_x112 = {
1783 .eepromVersion = 2,
1784 .templateVersion = 5,
1785 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1786 .custData = {"x112-041-f0000"},
1787 .baseEepHeader = {
1788 .regDmn = { LE16(0), LE16(0x1f) },
1789 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1790 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]1791 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1792 .eepMisc = 0,
1793 },
1794 .rfSilent = 0,
1795 .blueToothOptions = 0,
1796 .deviceCap = 0,
1797 .deviceType = 5, /* takes lower byte in eeprom location */
1798 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1799 .params_for_tuning_caps = {0, 0},
1800 .featureEnable = 0x0d,
1801 /*
1802 * bit0 - enable tx temp comp - disabled
1803 * bit1 - enable tx volt comp - disabled
1804 * bit2 - enable fastclock - enabled
1805 * bit3 - enable doubling - enabled
1806 * bit4 - enable internal regulator - disabled
1807 * bit5 - enable pa predistortion - disabled
1808 */
1809 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1810 .eepromWriteEnableGpio = 6,
1811 .wlanDisableGpio = 0,
1812 .wlanLedGpio = 8,
1813 .rxBandSelectGpio = 0xff,
1814 .txrxgain = 0x0,
1815 .swreg = 0,
1816 },
1817 .modalHeader2G = {
1818 /* ar9300_modal_eep_header 2g */
1819 /* 4 idle,t1,t2,b(4 bits per setting) */
1820 .antCtrlCommon = LE32(0x110),
1821 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1822 .antCtrlCommon2 = LE32(0x22222),
1823
1824 /*
1825 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1826 * rx1, rx12, b (2 bits each)
1827 */
1828 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1829
1830 /*
1831 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1832 * for ar9280 (0xa20c/b20c 5:0)
1833 */
1834 .xatten1DB = {0x1b, 0x1b, 0x1b},
1835
1836 /*
1837 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1838 * for ar9280 (0xa20c/b20c 16:12
1839 */
1840 .xatten1Margin = {0x15, 0x15, 0x15},
1841 .tempSlope = 50,
1842 .voltSlope = 0,
1843
1844 /*
1845 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1846 * channels in usual fbin coding format
1847 */
1848 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1849
1850 /*
1851 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1852 * if the register is per chain
1853 */
1854 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]1855 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1856 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1857 .xpaBiasLvl = 0,
1858 .txFrameToDataStart = 0x0e,
1859 .txFrameToPaOn = 0x0e,
1860 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1861 .antennaGain = 0,
1862 .switchSettling = 0x2c,
1863 .adcDesiredSize = -30,
1864 .txEndToXpaOff = 0,
1865 .txEndToRxOn = 0x2,
1866 .txFrameToXpaOn = 0xe,
1867 .thresh62 = 28,
1868 .papdRateMaskHt20 = LE32(0x0c80c080),
1869 .papdRateMaskHt40 = LE32(0x0080c080),
Sujith Manoharan66a80a32013-12-18 09:53:21 +0530[diff] [blame]1870 .switchcomspdt = 0,
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1871 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1872 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1873 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1874 },
1875 },
1876 .base_ext1 = {
1877 .ant_div_control = 0,
Sujith Manoharanee65b382013-12-18 09:53:22 +0530[diff] [blame]1878 .future = {0, 0},
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]1879 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1880 },
1881 .calFreqPier2G = {
1882 FREQ2FBIN(2412, 1),
1883 FREQ2FBIN(2437, 1),
1884 FREQ2FBIN(2472, 1),
1885 },
1886 /* ar9300_cal_data_per_freq_op_loop 2g */
1887 .calPierData2G = {
1888 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1889 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1890 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1891 },
1892 .calTarget_freqbin_Cck = {
1893 FREQ2FBIN(2412, 1),
1894 FREQ2FBIN(2472, 1),
1895 },
1896 .calTarget_freqbin_2G = {
1897 FREQ2FBIN(2412, 1),
1898 FREQ2FBIN(2437, 1),
1899 FREQ2FBIN(2472, 1)
1900 },
1901 .calTarget_freqbin_2GHT20 = {
1902 FREQ2FBIN(2412, 1),
1903 FREQ2FBIN(2437, 1),
1904 FREQ2FBIN(2472, 1)
1905 },
1906 .calTarget_freqbin_2GHT40 = {
1907 FREQ2FBIN(2412, 1),
1908 FREQ2FBIN(2437, 1),
1909 FREQ2FBIN(2472, 1)
1910 },
1911 .calTargetPowerCck = {
1912 /* 1L-5L,5S,11L,11s */
1913 { {38, 38, 38, 38} },
1914 { {38, 38, 38, 38} },
1915 },
1916 .calTargetPower2G = {
1917 /* 6-24,36,48,54 */
1918 { {38, 38, 36, 34} },
1919 { {38, 38, 36, 34} },
1920 { {38, 38, 34, 32} },
1921 },
1922 .calTargetPower2GHT20 = {
1923 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1924 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1925 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1926 },
1927 .calTargetPower2GHT40 = {
1928 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1929 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1930 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1931 },
1932 .ctlIndex_2G = {
1933 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1934 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1935 },
1936 .ctl_freqbin_2G = {
1937 {
1938 FREQ2FBIN(2412, 1),
1939 FREQ2FBIN(2417, 1),
1940 FREQ2FBIN(2457, 1),
1941 FREQ2FBIN(2462, 1)
1942 },
1943 {
1944 FREQ2FBIN(2412, 1),
1945 FREQ2FBIN(2417, 1),
1946 FREQ2FBIN(2462, 1),
1947 0xFF,
1948 },
1949
1950 {
1951 FREQ2FBIN(2412, 1),
1952 FREQ2FBIN(2417, 1),
1953 FREQ2FBIN(2462, 1),
1954 0xFF,
1955 },
1956 {
1957 FREQ2FBIN(2422, 1),
1958 FREQ2FBIN(2427, 1),
1959 FREQ2FBIN(2447, 1),
1960 FREQ2FBIN(2452, 1)
1961 },
1962
1963 {
1964 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1965 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1966 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1967 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1968 },
1969
1970 {
1971 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1972 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1973 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1974 0,
1975 },
1976
1977 {
1978 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1979 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1980 FREQ2FBIN(2472, 1),
1981 0,
1982 },
1983
1984 {
1985 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1986 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1987 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1988 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1989 },
1990
1991 {
1992 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1993 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1994 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1995 },
1996
1997 {
1998 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1999 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2000 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2001 0
2002 },
2003
2004 {
2005 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2006 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2007 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2008 0
2009 },
2010
2011 {
2012 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2013 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2014 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2015 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2016 }
2017 },
2018 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2019 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2020 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2021 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2022
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]2023 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2024 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2025 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2026
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2027 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2028 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2029 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2030
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2031 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2032 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2033 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2034 },
2035 .modalHeader5G = {
2036 /* 4 idle,t1,t2,b (4 bits per setting) */
2037 .antCtrlCommon = LE32(0x110),
2038 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2039 .antCtrlCommon2 = LE32(0x22222),
2040 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2041 .antCtrlChain = {
2042 LE16(0x0), LE16(0x0), LE16(0x0),
2043 },
2044 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2045 .xatten1DB = {0x13, 0x19, 0x17},
2046
2047 /*
2048 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2049 * for merlin (0xa20c/b20c 16:12
2050 */
2051 .xatten1Margin = {0x19, 0x19, 0x19},
2052 .tempSlope = 70,
2053 .voltSlope = 15,
2054 /* spurChans spur channels in usual fbin coding format */
2055 .spurChans = {0, 0, 0, 0, 0},
2056 /* noiseFloorThreshch check if the register is per chain */
2057 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]2058 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2059 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2060 .xpaBiasLvl = 0,
2061 .txFrameToDataStart = 0x0e,
2062 .txFrameToPaOn = 0x0e,
2063 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2064 .antennaGain = 0,
2065 .switchSettling = 0x2d,
2066 .adcDesiredSize = -30,
2067 .txEndToXpaOff = 0,
2068 .txEndToRxOn = 0x2,
2069 .txFrameToXpaOn = 0xe,
2070 .thresh62 = 28,
2071 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2072 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Sujith Manoharan66a80a32013-12-18 09:53:21 +0530[diff] [blame]2073 .switchcomspdt = 0,
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2074 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2075 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2076 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2077 },
2078 },
2079 .base_ext2 = {
2080 .tempSlopeLow = 72,
2081 .tempSlopeHigh = 105,
2082 .xatten1DBLow = {0x10, 0x14, 0x10},
2083 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2084 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2085 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2086 },
2087 .calFreqPier5G = {
2088 FREQ2FBIN(5180, 0),
2089 FREQ2FBIN(5220, 0),
2090 FREQ2FBIN(5320, 0),
2091 FREQ2FBIN(5400, 0),
2092 FREQ2FBIN(5500, 0),
2093 FREQ2FBIN(5600, 0),
2094 FREQ2FBIN(5700, 0),
2095 FREQ2FBIN(5785, 0)
2096 },
2097 .calPierData5G = {
2098 {
2099 {0, 0, 0, 0, 0},
2100 {0, 0, 0, 0, 0},
2101 {0, 0, 0, 0, 0},
2102 {0, 0, 0, 0, 0},
2103 {0, 0, 0, 0, 0},
2104 {0, 0, 0, 0, 0},
2105 {0, 0, 0, 0, 0},
2106 {0, 0, 0, 0, 0},
2107 },
2108 {
2109 {0, 0, 0, 0, 0},
2110 {0, 0, 0, 0, 0},
2111 {0, 0, 0, 0, 0},
2112 {0, 0, 0, 0, 0},
2113 {0, 0, 0, 0, 0},
2114 {0, 0, 0, 0, 0},
2115 {0, 0, 0, 0, 0},
2116 {0, 0, 0, 0, 0},
2117 },
2118 {
2119 {0, 0, 0, 0, 0},
2120 {0, 0, 0, 0, 0},
2121 {0, 0, 0, 0, 0},
2122 {0, 0, 0, 0, 0},
2123 {0, 0, 0, 0, 0},
2124 {0, 0, 0, 0, 0},
2125 {0, 0, 0, 0, 0},
2126 {0, 0, 0, 0, 0},
2127 },
2128
2129 },
2130 .calTarget_freqbin_5G = {
2131 FREQ2FBIN(5180, 0),
2132 FREQ2FBIN(5220, 0),
2133 FREQ2FBIN(5320, 0),
2134 FREQ2FBIN(5400, 0),
2135 FREQ2FBIN(5500, 0),
2136 FREQ2FBIN(5600, 0),
2137 FREQ2FBIN(5725, 0),
2138 FREQ2FBIN(5825, 0)
2139 },
2140 .calTarget_freqbin_5GHT20 = {
2141 FREQ2FBIN(5180, 0),
2142 FREQ2FBIN(5220, 0),
2143 FREQ2FBIN(5320, 0),
2144 FREQ2FBIN(5400, 0),
2145 FREQ2FBIN(5500, 0),
2146 FREQ2FBIN(5600, 0),
2147 FREQ2FBIN(5725, 0),
2148 FREQ2FBIN(5825, 0)
2149 },
2150 .calTarget_freqbin_5GHT40 = {
2151 FREQ2FBIN(5180, 0),
2152 FREQ2FBIN(5220, 0),
2153 FREQ2FBIN(5320, 0),
2154 FREQ2FBIN(5400, 0),
2155 FREQ2FBIN(5500, 0),
2156 FREQ2FBIN(5600, 0),
2157 FREQ2FBIN(5725, 0),
2158 FREQ2FBIN(5825, 0)
2159 },
2160 .calTargetPower5G = {
2161 /* 6-24,36,48,54 */
2162 { {32, 32, 28, 26} },
2163 { {32, 32, 28, 26} },
2164 { {32, 32, 28, 26} },
2165 { {32, 32, 26, 24} },
2166 { {32, 32, 26, 24} },
2167 { {32, 32, 24, 22} },
2168 { {30, 30, 24, 22} },
2169 { {30, 30, 24, 22} },
2170 },
2171 .calTargetPower5GHT20 = {
2172 /*
2173 * 0_8_16,1-3_9-11_17-19,
2174 * 4,5,6,7,12,13,14,15,20,21,22,23
2175 */
2176 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2177 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2178 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2179 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2180 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2181 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2182 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2183 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2184 },
2185 .calTargetPower5GHT40 = {
2186 /*
2187 * 0_8_16,1-3_9-11_17-19,
2188 * 4,5,6,7,12,13,14,15,20,21,22,23
2189 */
2190 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2191 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2192 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2193 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2194 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2195 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2196 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2197 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2198 },
2199 .ctlIndex_5G = {
2200 0x10, 0x16, 0x18, 0x40, 0x46,
2201 0x48, 0x30, 0x36, 0x38
2202 },
2203 .ctl_freqbin_5G = {
2204 {
2205 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2206 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2207 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2208 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2209 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2210 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2211 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2212 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2213 },
2214 {
2215 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2216 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2217 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2218 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2219 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2220 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2221 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2222 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2223 },
2224
2225 {
2226 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2227 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2228 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2229 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2230 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2231 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2232 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2233 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2234 },
2235
2236 {
2237 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2238 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2239 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2240 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2241 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2242 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2243 /* Data[3].ctledges[6].bchannel */ 0xFF,
2244 /* Data[3].ctledges[7].bchannel */ 0xFF,
2245 },
2246
2247 {
2248 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2249 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2250 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2251 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2252 /* Data[4].ctledges[4].bchannel */ 0xFF,
2253 /* Data[4].ctledges[5].bchannel */ 0xFF,
2254 /* Data[4].ctledges[6].bchannel */ 0xFF,
2255 /* Data[4].ctledges[7].bchannel */ 0xFF,
2256 },
2257
2258 {
2259 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2260 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2261 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2262 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2263 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2264 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2265 /* Data[5].ctledges[6].bchannel */ 0xFF,
2266 /* Data[5].ctledges[7].bchannel */ 0xFF
2267 },
2268
2269 {
2270 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2271 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2272 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2273 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2274 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2275 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2276 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2277 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2278 },
2279
2280 {
2281 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2282 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2283 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2284 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2285 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2286 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2287 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2288 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2289 },
2290
2291 {
2292 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2293 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2294 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2295 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2296 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2297 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2298 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2299 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2300 }
2301 },
2302 .ctlPowerData_5G = {
2303 {
2304 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2305 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2306 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2307 }
2308 },
2309 {
2310 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2311 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2312 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2313 }
2314 },
2315 {
2316 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2317 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2318 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2319 }
2320 },
2321 {
2322 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2323 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2324 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2325 }
2326 },
2327 {
2328 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2329 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2330 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2331 }
2332 },
2333 {
2334 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2335 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2336 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2337 }
2338 },
2339 {
2340 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2341 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2342 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2343 }
2344 },
2345 {
2346 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2347 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2348 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2349 }
2350 },
2351 {
2352 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2353 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2354 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2355 }
2356 },
2357 }
2358};
2359
2360static const struct ar9300_eeprom ar9300_h116 = {
2361 .eepromVersion = 2,
2362 .templateVersion = 4,
2363 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2364 .custData = {"h116-041-f0000"},
2365 .baseEepHeader = {
2366 .regDmn = { LE16(0), LE16(0x1f) },
2367 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2368 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]2369 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2370 .eepMisc = 0,
2371 },
2372 .rfSilent = 0,
2373 .blueToothOptions = 0,
2374 .deviceCap = 0,
2375 .deviceType = 5, /* takes lower byte in eeprom location */
2376 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2377 .params_for_tuning_caps = {0, 0},
2378 .featureEnable = 0x0d,
2379 /*
2380 * bit0 - enable tx temp comp - disabled
2381 * bit1 - enable tx volt comp - disabled
2382 * bit2 - enable fastClock - enabled
2383 * bit3 - enable doubling - enabled
2384 * bit4 - enable internal regulator - disabled
2385 * bit5 - enable pa predistortion - disabled
2386 */
2387 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2388 .eepromWriteEnableGpio = 6,
2389 .wlanDisableGpio = 0,
2390 .wlanLedGpio = 8,
2391 .rxBandSelectGpio = 0xff,
2392 .txrxgain = 0x10,
2393 .swreg = 0,
2394 },
2395 .modalHeader2G = {
2396 /* ar9300_modal_eep_header 2g */
2397 /* 4 idle,t1,t2,b(4 bits per setting) */
2398 .antCtrlCommon = LE32(0x110),
2399 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2400 .antCtrlCommon2 = LE32(0x44444),
2401
2402 /*
2403 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2404 * rx1, rx12, b (2 bits each)
2405 */
2406 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2407
2408 /*
2409 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2410 * for ar9280 (0xa20c/b20c 5:0)
2411 */
2412 .xatten1DB = {0x1f, 0x1f, 0x1f},
2413
2414 /*
2415 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2416 * for ar9280 (0xa20c/b20c 16:12
2417 */
2418 .xatten1Margin = {0x12, 0x12, 0x12},
2419 .tempSlope = 25,
2420 .voltSlope = 0,
2421
2422 /*
2423 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2424 * channels in usual fbin coding format
2425 */
2426 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2427
2428 /*
2429 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2430 * if the register is per chain
2431 */
2432 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]2433 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2434 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2435 .xpaBiasLvl = 0,
2436 .txFrameToDataStart = 0x0e,
2437 .txFrameToPaOn = 0x0e,
2438 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2439 .antennaGain = 0,
2440 .switchSettling = 0x2c,
2441 .adcDesiredSize = -30,
2442 .txEndToXpaOff = 0,
2443 .txEndToRxOn = 0x2,
2444 .txFrameToXpaOn = 0xe,
2445 .thresh62 = 28,
2446 .papdRateMaskHt20 = LE32(0x0c80C080),
2447 .papdRateMaskHt40 = LE32(0x0080C080),
Sujith Manoharan66a80a32013-12-18 09:53:21 +0530[diff] [blame]2448 .switchcomspdt = 0,
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2449 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2450 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2451 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2452 },
2453 },
2454 .base_ext1 = {
2455 .ant_div_control = 0,
Sujith Manoharanee65b382013-12-18 09:53:22 +0530[diff] [blame]2456 .future = {0, 0},
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]2457 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2458 },
2459 .calFreqPier2G = {
2460 FREQ2FBIN(2412, 1),
2461 FREQ2FBIN(2437, 1),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]2462 FREQ2FBIN(2462, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2463 },
2464 /* ar9300_cal_data_per_freq_op_loop 2g */
2465 .calPierData2G = {
2466 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2467 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2468 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2469 },
2470 .calTarget_freqbin_Cck = {
2471 FREQ2FBIN(2412, 1),
2472 FREQ2FBIN(2472, 1),
2473 },
2474 .calTarget_freqbin_2G = {
2475 FREQ2FBIN(2412, 1),
2476 FREQ2FBIN(2437, 1),
2477 FREQ2FBIN(2472, 1)
2478 },
2479 .calTarget_freqbin_2GHT20 = {
2480 FREQ2FBIN(2412, 1),
2481 FREQ2FBIN(2437, 1),
2482 FREQ2FBIN(2472, 1)
2483 },
2484 .calTarget_freqbin_2GHT40 = {
2485 FREQ2FBIN(2412, 1),
2486 FREQ2FBIN(2437, 1),
2487 FREQ2FBIN(2472, 1)
2488 },
2489 .calTargetPowerCck = {
2490 /* 1L-5L,5S,11L,11S */
2491 { {34, 34, 34, 34} },
2492 { {34, 34, 34, 34} },
2493 },
2494 .calTargetPower2G = {
2495 /* 6-24,36,48,54 */
2496 { {34, 34, 32, 32} },
2497 { {34, 34, 32, 32} },
2498 { {34, 34, 32, 32} },
2499 },
2500 .calTargetPower2GHT20 = {
2501 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2502 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2503 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2504 },
2505 .calTargetPower2GHT40 = {
2506 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2507 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2508 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2509 },
2510 .ctlIndex_2G = {
2511 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2512 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2513 },
2514 .ctl_freqbin_2G = {
2515 {
2516 FREQ2FBIN(2412, 1),
2517 FREQ2FBIN(2417, 1),
2518 FREQ2FBIN(2457, 1),
2519 FREQ2FBIN(2462, 1)
2520 },
2521 {
2522 FREQ2FBIN(2412, 1),
2523 FREQ2FBIN(2417, 1),
2524 FREQ2FBIN(2462, 1),
2525 0xFF,
2526 },
2527
2528 {
2529 FREQ2FBIN(2412, 1),
2530 FREQ2FBIN(2417, 1),
2531 FREQ2FBIN(2462, 1),
2532 0xFF,
2533 },
2534 {
2535 FREQ2FBIN(2422, 1),
2536 FREQ2FBIN(2427, 1),
2537 FREQ2FBIN(2447, 1),
2538 FREQ2FBIN(2452, 1)
2539 },
2540
2541 {
2542 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2543 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2544 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2545 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2546 },
2547
2548 {
2549 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2550 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2551 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2552 0,
2553 },
2554
2555 {
2556 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2557 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2558 FREQ2FBIN(2472, 1),
2559 0,
2560 },
2561
2562 {
2563 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2564 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2565 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2566 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2567 },
2568
2569 {
2570 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2571 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2572 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2573 },
2574
2575 {
2576 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2577 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2578 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2579 0
2580 },
2581
2582 {
2583 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2584 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2585 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2586 0
2587 },
2588
2589 {
2590 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2591 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2592 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2593 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2594 }
2595 },
2596 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2597 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2598 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2599 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2600
Mohammed Shafi Shajakhan81dc6762011-06-17 11:07:32 +0530[diff] [blame]2601 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2602 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2603 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2604
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2605 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2606 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2607 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2608
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2609 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2610 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2611 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2612 },
2613 .modalHeader5G = {
2614 /* 4 idle,t1,t2,b (4 bits per setting) */
2615 .antCtrlCommon = LE32(0x220),
2616 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2617 .antCtrlCommon2 = LE32(0x44444),
2618 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2619 .antCtrlChain = {
2620 LE16(0x150), LE16(0x150), LE16(0x150),
2621 },
2622 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2623 .xatten1DB = {0x19, 0x19, 0x19},
2624
2625 /*
2626 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2627 * for merlin (0xa20c/b20c 16:12
2628 */
2629 .xatten1Margin = {0x14, 0x14, 0x14},
2630 .tempSlope = 70,
2631 .voltSlope = 0,
2632 /* spurChans spur channels in usual fbin coding format */
2633 .spurChans = {0, 0, 0, 0, 0},
2634 /* noiseFloorThreshCh Check if the register is per chain */
2635 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]2636 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2637 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2638 .xpaBiasLvl = 0,
2639 .txFrameToDataStart = 0x0e,
2640 .txFrameToPaOn = 0x0e,
2641 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2642 .antennaGain = 0,
2643 .switchSettling = 0x2d,
2644 .adcDesiredSize = -30,
2645 .txEndToXpaOff = 0,
2646 .txEndToRxOn = 0x2,
2647 .txFrameToXpaOn = 0xe,
2648 .thresh62 = 28,
2649 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2650 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Sujith Manoharan66a80a32013-12-18 09:53:21 +0530[diff] [blame]2651 .switchcomspdt = 0,
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2652 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2653 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2654 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2655 },
2656 },
2657 .base_ext2 = {
2658 .tempSlopeLow = 35,
2659 .tempSlopeHigh = 50,
2660 .xatten1DBLow = {0, 0, 0},
2661 .xatten1MarginLow = {0, 0, 0},
2662 .xatten1DBHigh = {0, 0, 0},
2663 .xatten1MarginHigh = {0, 0, 0}
2664 },
2665 .calFreqPier5G = {
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]2666 FREQ2FBIN(5160, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2667 FREQ2FBIN(5220, 0),
2668 FREQ2FBIN(5320, 0),
2669 FREQ2FBIN(5400, 0),
2670 FREQ2FBIN(5500, 0),
2671 FREQ2FBIN(5600, 0),
2672 FREQ2FBIN(5700, 0),
2673 FREQ2FBIN(5785, 0)
2674 },
2675 .calPierData5G = {
2676 {
2677 {0, 0, 0, 0, 0},
2678 {0, 0, 0, 0, 0},
2679 {0, 0, 0, 0, 0},
2680 {0, 0, 0, 0, 0},
2681 {0, 0, 0, 0, 0},
2682 {0, 0, 0, 0, 0},
2683 {0, 0, 0, 0, 0},
2684 {0, 0, 0, 0, 0},
2685 },
2686 {
2687 {0, 0, 0, 0, 0},
2688 {0, 0, 0, 0, 0},
2689 {0, 0, 0, 0, 0},
2690 {0, 0, 0, 0, 0},
2691 {0, 0, 0, 0, 0},
2692 {0, 0, 0, 0, 0},
2693 {0, 0, 0, 0, 0},
2694 {0, 0, 0, 0, 0},
2695 },
2696 {
2697 {0, 0, 0, 0, 0},
2698 {0, 0, 0, 0, 0},
2699 {0, 0, 0, 0, 0},
2700 {0, 0, 0, 0, 0},
2701 {0, 0, 0, 0, 0},
2702 {0, 0, 0, 0, 0},
2703 {0, 0, 0, 0, 0},
2704 {0, 0, 0, 0, 0},
2705 },
2706
2707 },
2708 .calTarget_freqbin_5G = {
2709 FREQ2FBIN(5180, 0),
2710 FREQ2FBIN(5240, 0),
2711 FREQ2FBIN(5320, 0),
2712 FREQ2FBIN(5400, 0),
2713 FREQ2FBIN(5500, 0),
2714 FREQ2FBIN(5600, 0),
2715 FREQ2FBIN(5700, 0),
2716 FREQ2FBIN(5825, 0)
2717 },
2718 .calTarget_freqbin_5GHT20 = {
2719 FREQ2FBIN(5180, 0),
2720 FREQ2FBIN(5240, 0),
2721 FREQ2FBIN(5320, 0),
2722 FREQ2FBIN(5400, 0),
2723 FREQ2FBIN(5500, 0),
2724 FREQ2FBIN(5700, 0),
2725 FREQ2FBIN(5745, 0),
2726 FREQ2FBIN(5825, 0)
2727 },
2728 .calTarget_freqbin_5GHT40 = {
2729 FREQ2FBIN(5180, 0),
2730 FREQ2FBIN(5240, 0),
2731 FREQ2FBIN(5320, 0),
2732 FREQ2FBIN(5400, 0),
2733 FREQ2FBIN(5500, 0),
2734 FREQ2FBIN(5700, 0),
2735 FREQ2FBIN(5745, 0),
2736 FREQ2FBIN(5825, 0)
2737 },
2738 .calTargetPower5G = {
2739 /* 6-24,36,48,54 */
2740 { {30, 30, 28, 24} },
2741 { {30, 30, 28, 24} },
2742 { {30, 30, 28, 24} },
2743 { {30, 30, 28, 24} },
2744 { {30, 30, 28, 24} },
2745 { {30, 30, 28, 24} },
2746 { {30, 30, 28, 24} },
2747 { {30, 30, 28, 24} },
2748 },
2749 .calTargetPower5GHT20 = {
2750 /*
2751 * 0_8_16,1-3_9-11_17-19,
2752 * 4,5,6,7,12,13,14,15,20,21,22,23
2753 */
2754 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2755 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2756 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2757 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2758 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2759 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2760 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2761 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2762 },
2763 .calTargetPower5GHT40 = {
2764 /*
2765 * 0_8_16,1-3_9-11_17-19,
2766 * 4,5,6,7,12,13,14,15,20,21,22,23
2767 */
2768 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2769 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2770 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2771 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2772 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2773 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2774 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2775 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2776 },
2777 .ctlIndex_5G = {
2778 0x10, 0x16, 0x18, 0x40, 0x46,
2779 0x48, 0x30, 0x36, 0x38
2780 },
2781 .ctl_freqbin_5G = {
2782 {
2783 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2784 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2785 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2786 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2787 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2788 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2789 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2790 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2791 },
2792 {
2793 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2794 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2795 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2796 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2797 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2798 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2799 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2800 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2801 },
2802
2803 {
2804 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2805 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2806 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2807 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2808 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2809 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2810 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2811 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2812 },
2813
2814 {
2815 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2816 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2817 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2818 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2819 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2820 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2821 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2822 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2823 },
2824
2825 {
2826 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2827 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2828 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2829 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2830 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2831 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2832 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2833 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2834 },
2835
2836 {
2837 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2838 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2839 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2840 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2841 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2842 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2843 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2844 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2845 },
2846
2847 {
2848 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2849 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2850 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2851 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2852 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2853 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2854 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2855 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2856 },
2857
2858 {
2859 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2860 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2861 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2862 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2863 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2864 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2865 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2866 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2867 },
2868
2869 {
2870 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2871 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2872 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2873 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2874 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2875 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2876 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2877 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2878 }
2879 },
2880 .ctlPowerData_5G = {
2881 {
2882 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2883 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2884 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2885 }
2886 },
2887 {
2888 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2889 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2890 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2891 }
2892 },
2893 {
2894 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2895 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2896 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2897 }
2898 },
2899 {
2900 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2901 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2902 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2903 }
2904 },
2905 {
2906 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2907 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2908 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2909 }
2910 },
2911 {
2912 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2913 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2914 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2915 }
2916 },
2917 {
2918 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2919 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2920 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2921 }
2922 },
2923 {
2924 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2925 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2926 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2927 }
2928 },
2929 {
2930 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2931 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2932 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2933 }
2934 },
2935 }
2936};
2937
2938
2939static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2940 &ar9300_default,
2941 &ar9300_x112,
2942 &ar9300_h116,
2943 &ar9300_h112,
2944 &ar9300_x113,
2945};
2946
2947static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2948{
2949#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2950 int it;
2951
2952 for (it = 0; it < N_LOOP; it++)
2953 if (ar9300_eep_templates[it]->templateVersion == id)
2954 return ar9300_eep_templates[it];
2955 return NULL;
2956#undef N_LOOP
2957}
2958
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2959static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2960{
2961 return 0;
2962}
2963
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]2964static int interpolate(int x, int xa, int xb, int ya, int yb)
2965{
2966 int bf, factor, plus;
2967
2968 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2969 factor = bf / 2;
2970 plus = bf % 2;
2971 return ya + factor + plus;
2972}
2973
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2974static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2975 enum eeprom_param param)
2976{
2977 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2978 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2979
2980 switch (param) {
2981 case EEP_MAC_LSW:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2982 return get_unaligned_be16(eep->macAddr);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2983 case EEP_MAC_MID:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2984 return get_unaligned_be16(eep->macAddr + 2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2985 case EEP_MAC_MSW:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2986 return get_unaligned_be16(eep->macAddr + 4);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2987 case EEP_REG_0:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]2988 return le16_to_cpu(pBase->regDmn[0]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2989 case EEP_OP_CAP:
2990 return pBase->deviceCap;
2991 case EEP_OP_MODE:
2992 return pBase->opCapFlags.opFlags;
2993 case EEP_RF_SILENT:
2994 return pBase->rfSilent;
2995 case EEP_TX_MASK:
2996 return (pBase->txrxMask >> 4) & 0xf;
2997 case EEP_RX_MASK:
2998 return pBase->txrxMask & 0xf;
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]2999 case EEP_PAPRD:
3000 return !!(pBase->featureEnable & BIT(5));
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +0530[diff] [blame]3001 case EEP_CHAIN_MASK_REDUCE:
3002 return (pBase->miscConfiguration >> 0x3) & 0x1;
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3003 case EEP_ANT_DIV_CTL1:
Sujith Manoharan7e12d6a2013-09-02 13:59:00 +0530[diff] [blame]3004 if (AR_SREV_9565(ah))
3005 return AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE;
3006 else
3007 return eep->base_ext1.ant_div_control;
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame]3008 case EEP_ANTENNA_GAIN_5G:
3009 return eep->modalHeader5G.antennaGain;
3010 case EEP_ANTENNA_GAIN_2G:
3011 return eep->modalHeader2G.antennaGain;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3012 default:
3013 return 0;
3014 }
3015}
3016
Gabor Juhos0e4b9f22012-12-10 15:30:27 +0100[diff] [blame]3017static bool ar9300_eeprom_read_byte(struct ath_hw *ah, int address,
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3018 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3019{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3020 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3021
Gabor Juhos0e4b9f22012-12-10 15:30:27 +0100[diff] [blame]3022 if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val)))
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3023 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3024
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3025 *buffer = (val >> (8 * (address % 2))) & 0xff;
3026 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3027}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3028
Gabor Juhos0e4b9f22012-12-10 15:30:27 +0100[diff] [blame]3029static bool ar9300_eeprom_read_word(struct ath_hw *ah, int address,
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3030 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3031{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3032 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3033
Gabor Juhos0e4b9f22012-12-10 15:30:27 +0100[diff] [blame]3034 if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val)))
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3035 return false;
3036
3037 buffer[0] = val >> 8;
3038 buffer[1] = val & 0xff;
3039
3040 return true;
3041}
3042
3043static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3044 int count)
3045{
3046 struct ath_common *common = ath9k_hw_common(ah);
3047 int i;
3048
3049 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3050 ath_dbg(common, EEPROM, "eeprom address not in range\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3051 return false;
3052 }
3053
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3054 /*
3055 * Since we're reading the bytes in reverse order from a little-endian
3056 * word stream, an even address means we only use the lower half of
3057 * the 16-bit word at that address
3058 */
3059 if (address % 2 == 0) {
Gabor Juhos0e4b9f22012-12-10 15:30:27 +0100[diff] [blame]3060 if (!ar9300_eeprom_read_byte(ah, address--, buffer++))
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3061 goto error;
3062
3063 count--;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3064 }
3065
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3066 for (i = 0; i < count / 2; i++) {
Gabor Juhos0e4b9f22012-12-10 15:30:27 +0100[diff] [blame]3067 if (!ar9300_eeprom_read_word(ah, address, buffer))
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3068 goto error;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3069
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3070 address -= 2;
3071 buffer += 2;
3072 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3073
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3074 if (count % 2)
Gabor Juhos0e4b9f22012-12-10 15:30:27 +0100[diff] [blame]3075 if (!ar9300_eeprom_read_byte(ah, address, buffer))
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3076 goto error;
3077
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3078 return true;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3079
3080error:
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3081 ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3082 address);
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3083 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3084}
3085
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3086static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3087{
3088 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3089
3090 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3091 AR9300_OTP_STATUS_VALID, 1000))
3092 return false;
3093
3094 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3095 return true;
3096}
3097
3098static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3099 int count)
3100{
3101 u32 data;
3102 int i;
3103
3104 for (i = 0; i < count; i++) {
3105 int offset = 8 * ((address - i) % 4);
3106 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3107 return false;
3108
3109 buffer[i] = (data >> offset) & 0xff;
3110 }
3111
3112 return true;
3113}
3114
3115
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3116static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3117 int *length, int *major, int *minor)
3118{
3119 unsigned long value[4];
3120
3121 value[0] = best[0];
3122 value[1] = best[1];
3123 value[2] = best[2];
3124 value[3] = best[3];
3125 *code = ((value[0] >> 5) & 0x0007);
3126 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3127 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3128 *major = (value[2] & 0x000f);
3129 *minor = (value[3] & 0x00ff);
3130}
3131
3132static u16 ar9300_comp_cksum(u8 *data, int dsize)
3133{
3134 int it, checksum = 0;
3135
3136 for (it = 0; it < dsize; it++) {
3137 checksum += data[it];
3138 checksum &= 0xffff;
3139 }
3140
3141 return checksum;
3142}
3143
3144static bool ar9300_uncompress_block(struct ath_hw *ah,
3145 u8 *mptr,
3146 int mdataSize,
3147 u8 *block,
3148 int size)
3149{
3150 int it;
3151 int spot;
3152 int offset;
3153 int length;
3154 struct ath_common *common = ath9k_hw_common(ah);
3155
3156 spot = 0;
3157
3158 for (it = 0; it < size; it += (length+2)) {
3159 offset = block[it];
3160 offset &= 0xff;
3161 spot += offset;
3162 length = block[it+1];
3163 length &= 0xff;
3164
Luis R. Rodriguez803288e2010-08-30 19:26:32 -0400[diff] [blame]3165 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3166 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3167 "Restore at %d: spot=%d offset=%d length=%d\n",
3168 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3169 memcpy(&mptr[spot], &block[it+2], length);
3170 spot += length;
3171 } else if (length > 0) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3172 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3173 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3174 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3175 return false;
3176 }
3177 }
3178 return true;
3179}
3180
3181static int ar9300_compress_decision(struct ath_hw *ah,
3182 int it,
3183 int code,
3184 int reference,
3185 u8 *mptr,
3186 u8 *word, int length, int mdata_size)
3187{
3188 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3189 const struct ar9300_eeprom *eep = NULL;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3190
3191 switch (code) {
3192 case _CompressNone:
3193 if (length != mdata_size) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3194 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3195 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3196 mdata_size, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3197 return -1;
3198 }
Joe Perches2c208892012-06-04 12:44:17 +0000[diff] [blame]3199 memcpy(mptr, word + COMP_HDR_LEN, length);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3200 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3201 "restored eeprom %d: uncompressed, length %d\n",
3202 it, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3203 break;
3204 case _CompressBlock:
Eduardo Abinaderceda5152016-05-02 17:44:11 +0200[diff] [blame]3205 if (reference != 0) {
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3206 eep = ar9003_eeprom_struct_find_by_id(reference);
3207 if (eep == NULL) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3208 ath_dbg(common, EEPROM,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]3209 "can't find reference eeprom struct %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3210 reference);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3211 return -1;
3212 }
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3213 memcpy(mptr, eep, mdata_size);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3214 }
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3215 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3216 "restore eeprom %d: block, reference %d, length %d\n",
3217 it, reference, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3218 ar9300_uncompress_block(ah, mptr, mdata_size,
Joe Perches2c208892012-06-04 12:44:17 +0000[diff] [blame]3219 (word + COMP_HDR_LEN), length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3220 break;
3221 default:
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3222 ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3223 return -1;
3224 }
3225 return 0;
3226}
3227
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3228typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3229 int count);
3230
3231static bool ar9300_check_header(void *data)
3232{
3233 u32 *word = data;
3234 return !(*word == 0 || *word == ~0);
3235}
3236
3237static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3238 int base_addr)
3239{
3240 u8 header[4];
3241
3242 if (!read(ah, base_addr, header, 4))
3243 return false;
3244
3245 return ar9300_check_header(header);
3246}
3247
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3248static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3249 int mdata_size)
3250{
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3251 u16 *data = (u16 *) mptr;
3252 int i;
3253
3254 for (i = 0; i < mdata_size / 2; i++, data++)
Gabor Juhos0e4b9f22012-12-10 15:30:27 +0100[diff] [blame]3255 ath9k_hw_nvram_read(ah, i, data);
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3256
3257 return 0;
3258}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3259/*
3260 * Read the configuration data from the eeprom.
3261 * The data can be put in any specified memory buffer.
3262 *
3263 * Returns -1 on error.
3264 * Returns address of next memory location on success.
3265 */
3266static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3267 u8 *mptr, int mdata_size)
3268{
3269#define MDEFAULT 15
3270#define MSTATE 100
3271 int cptr;
3272 u8 *word;
3273 int code;
3274 int reference, length, major, minor;
3275 int osize;
3276 int it;
3277 u16 checksum, mchecksum;
3278 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau01967362012-07-15 19:53:29 +0200[diff] [blame]3279 struct ar9300_eeprom *eep;
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3280 eeprom_read_op read;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3281
Felix Fietkau01967362012-07-15 19:53:29 +0200[diff] [blame]3282 if (ath9k_hw_use_flash(ah)) {
3283 u8 txrx;
3284
3285 ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3286
3287 /* check if eeprom contains valid data */
3288 eep = (struct ar9300_eeprom *) mptr;
3289 txrx = eep->baseEepHeader.txrxMask;
3290 if (txrx != 0 && txrx != 0xff)
3291 return 0;
3292 }
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3293
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3294 word = kzalloc(2048, GFP_KERNEL);
3295 if (!word)
Larry Finger1ba45b92011-08-27 13:56:00 -0500[diff] [blame]3296 return -ENOMEM;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3297
3298 memcpy(mptr, &ar9300_default, mdata_size);
3299
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3300 read = ar9300_read_eeprom;
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3301 if (AR_SREV_9485(ah))
3302 cptr = AR9300_BASE_ADDR_4K;
Gabor Juhos5b5c0332011-06-21 11:23:38 +0200[diff] [blame]3303 else if (AR_SREV_9330(ah))
3304 cptr = AR9300_BASE_ADDR_512;
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3305 else
3306 cptr = AR9300_BASE_ADDR;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3307 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3308 cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3309 if (ar9300_check_eeprom_header(ah, read, cptr))
3310 goto found;
3311
3312 cptr = AR9300_BASE_ADDR_512;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3313 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3314 cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3315 if (ar9300_check_eeprom_header(ah, read, cptr))
3316 goto found;
3317
3318 read = ar9300_read_otp;
3319 cptr = AR9300_BASE_ADDR;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3320 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3321 if (ar9300_check_eeprom_header(ah, read, cptr))
3322 goto found;
3323
3324 cptr = AR9300_BASE_ADDR_512;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3325 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3326 if (ar9300_check_eeprom_header(ah, read, cptr))
3327 goto found;
3328
3329 goto fail;
3330
3331found:
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3332 ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3333
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3334 for (it = 0; it < MSTATE; it++) {
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3335 if (!read(ah, cptr, word, COMP_HDR_LEN))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3336 goto fail;
3337
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3338 if (!ar9300_check_header(word))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3339 break;
3340
3341 ar9300_comp_hdr_unpack(word, &code, &reference,
3342 &length, &major, &minor);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3343 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3344 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3345 cptr, code, reference, length, major, minor);
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3346 if ((!AR_SREV_9485(ah) && length >= 1024) ||
Vasanthakumar Thiagarajand0ce2d12010-12-21 01:42:43 -0800[diff] [blame]3347 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3348 ath_dbg(common, EEPROM, "Skipping bad header\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3349 cptr -= COMP_HDR_LEN;
3350 continue;
3351 }
3352
3353 osize = length;
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3354 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3355 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]3356 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3357 ath_dbg(common, EEPROM, "checksum %x %x\n",
3358 checksum, mchecksum);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3359 if (checksum == mchecksum) {
3360 ar9300_compress_decision(ah, it, code, reference, mptr,
3361 word, length, mdata_size);
3362 } else {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3363 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3364 "skipping block with bad checksum\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3365 }
3366 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3367 }
3368
3369 kfree(word);
3370 return cptr;
3371
3372fail:
3373 kfree(word);
3374 return -1;
3375}
3376
3377/*
3378 * Restore the configuration structure by reading the eeprom.
3379 * This function destroys any existing in-memory structure
3380 * content.
3381 */
3382static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3383{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3384 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3385
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3386 if (ar9300_eeprom_restore_internal(ah, mptr,
3387 sizeof(struct ar9300_eeprom)) < 0)
3388 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3389
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3390 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3391}
3392
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3393#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3394static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3395 struct ar9300_modal_eep_header *modal_hdr)
3396{
3397 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3398 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3399 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3400 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3401 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3402 PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3403 PR_EEP("Switch Settle", modal_hdr->switchSettling);
3404 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3405 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3406 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3407 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3408 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3409 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3410 PR_EEP("Temp Slope", modal_hdr->tempSlope);
3411 PR_EEP("Volt Slope", modal_hdr->voltSlope);
3412 PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3413 PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3414 PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3415 PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3416 PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3417 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3418 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3419 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3420 PR_EEP("Quick Drop", modal_hdr->quick_drop);
Rajkumar Manoharan202bff02011-11-08 14:19:33 +0530[diff] [blame]3421 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3422 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3423 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3424 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3425 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3426 PR_EEP("txClip", modal_hdr->txClip);
3427 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3428
3429 return len;
3430}
3431
3432static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3433 u8 *buf, u32 len, u32 size)
3434{
3435 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3436 struct ar9300_base_eep_hdr *pBase;
3437
3438 if (!dump_base_hdr) {
Zefir Kurtisi5e88ba62013-09-05 14:11:57 +0200[diff] [blame]3439 len += scnprintf(buf + len, size - len,
3440 "%20s :\n", "2GHz modal Header");
Mohammed Shafi Shajakhand25360b2012-05-15 15:24:47 +0530[diff] [blame]3441 len = ar9003_dump_modal_eeprom(buf, len, size,
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3442 &eep->modalHeader2G);
Zefir Kurtisi5e88ba62013-09-05 14:11:57 +0200[diff] [blame]3443 len += scnprintf(buf + len, size - len,
3444 "%20s :\n", "5GHz modal Header");
Mohammed Shafi Shajakhand25360b2012-05-15 15:24:47 +0530[diff] [blame]3445 len = ar9003_dump_modal_eeprom(buf, len, size,
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3446 &eep->modalHeader5G);
3447 goto out;
3448 }
3449
3450 pBase = &eep->baseEepHeader;
3451
3452 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3453 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3454 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3455 PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3456 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3457 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3458 AR5416_OPFLAGS_11A));
3459 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3460 AR5416_OPFLAGS_11G));
3461 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3462 AR5416_OPFLAGS_N_2G_HT20));
3463 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3464 AR5416_OPFLAGS_N_2G_HT40));
3465 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3466 AR5416_OPFLAGS_N_5G_HT20));
3467 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3468 AR5416_OPFLAGS_N_5G_HT40));
3469 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3470 PR_EEP("RF Silent", pBase->rfSilent);
3471 PR_EEP("BT option", pBase->blueToothOptions);
3472 PR_EEP("Device Cap", pBase->deviceCap);
3473 PR_EEP("Device Type", pBase->deviceType);
3474 PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3475 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3476 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3477 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3478 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3479 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3480 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3481 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3482 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3483 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3484 PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3485 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3486 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3487 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3488 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3489 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3490 PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3491 PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3492 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3493
Zefir Kurtisi5e88ba62013-09-05 14:11:57 +0200[diff] [blame]3494 len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3495 ah->eeprom.ar9300_eep.macAddr);
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3496out:
3497 if (len > size)
3498 len = size;
3499
3500 return len;
3501}
3502#else
3503static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3504 u8 *buf, u32 len, u32 size)
3505{
3506 return 0;
3507}
3508#endif
3509
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3510/* XXX: review hardware docs */
3511static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3512{
3513 return ah->eeprom.ar9300_eep.eepromVersion;
3514}
3515
3516/* XXX: could be read from the eepromVersion, not sure yet */
3517static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3518{
3519 return 0;
3520}
3521
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3522static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
3523 bool is2ghz)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3524{
3525 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3526
3527 if (is2ghz)
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3528 return &eep->modalHeader2G;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3529 else
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3530 return &eep->modalHeader5G;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3531}
3532
3533static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3534{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3535 int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3536
Rajkumar Manoharanddbbd9e2014-06-24 22:27:38 +0530[diff] [blame]3537 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530[diff] [blame]3538 AR_SREV_9531(ah) || AR_SREV_9561(ah))
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3539 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
Sujith Manoharana4a29542012-09-10 09:20:03 +0530[diff] [blame]3540 else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3541 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3542 else {
3543 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
Rajkumar Manoharan165af962011-05-09 19:11:26 +0530[diff] [blame]3544 REG_RMW_FIELD(ah, AR_CH0_THERM,
3545 AR_CH0_THERM_XPABIASLVL_MSB,
3546 bias >> 2);
3547 REG_RMW_FIELD(ah, AR_CH0_THERM,
3548 AR_CH0_THERM_XPASHORT2GND, 1);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3549 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3550}
3551
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3552static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3553{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3554 return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3555}
3556
Sujith Manoharan84893812013-08-04 14:22:02 +0530[diff] [blame]3557u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3558{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3559 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3560}
3561
Sujith Manoharan84893812013-08-04 14:22:02 +0530[diff] [blame]3562u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3563{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3564 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3565}
3566
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3567static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3568 bool is2ghz)
3569{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3570 __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3571 return le16_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3572}
3573
3574static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3575{
Sujith Manoharan7bdea962013-08-04 14:22:00 +0530[diff] [blame]3576 struct ath_common *common = ath9k_hw_common(ah);
Sujith Manoharan915154b2012-09-16 08:05:23 +0530[diff] [blame]3577 struct ath9k_hw_capabilities *pCap = &ah->caps;
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3578 int chain;
Sujith Manoharan9b60b642013-06-13 22:51:26 +0530[diff] [blame]3579 u32 regval, value, gpio;
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3580 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3581 AR_PHY_SWITCH_CHAIN_0,
3582 AR_PHY_SWITCH_CHAIN_1,
3583 AR_PHY_SWITCH_CHAIN_2,
3584 };
3585
Sujith Manoharan9b60b642013-06-13 22:51:26 +0530[diff] [blame]3586 if (AR_SREV_9485(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) {
3587 if (ah->config.xlna_gpio)
3588 gpio = ah->config.xlna_gpio;
3589 else
3590 gpio = AR9300_EXT_LNA_CTL_GPIO_AR9485;
3591
Miaoqing Panb2d70d42016-03-07 10:38:15 +0800[diff] [blame]3592 ath9k_hw_gpio_request_out(ah, gpio, NULL,
3593 AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED);
Sujith Manoharan9b60b642013-06-13 22:51:26 +0530[diff] [blame]3594 }
Sujith Manoharan30d5b702013-06-10 13:49:38 +0530[diff] [blame]3595
3596 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3597
Sujith Manoharana4a29542012-09-10 09:20:03 +0530[diff] [blame]3598 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3599 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3600 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530[diff] [blame]3601 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
Gabor Juhos2d00de42012-07-03 19:13:26 +0200[diff] [blame]3602 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3603 AR_SWITCH_TABLE_COM_AR9550_ALL, value);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3604 } else
3605 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3606 AR_SWITCH_TABLE_COM_ALL, value);
3607
3608
3609 /*
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3610 * AR9462 defines new switch table for BT/WLAN,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3611 * here's new field name in XXX.ref for both 2G and 5G.
3612 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3613 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
3614 * SWITCH_TABLE_COM_SPDT_WLAN_RX
3615 *
3616 * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX
3617 * SWITCH_TABLE_COM_SPDT_WLAN_TX
3618 *
3619 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3620 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3621 */
Sujith Manoharan2b5e54e2013-06-24 18:18:46 +0530[diff] [blame]3622 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3623 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3624 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3625 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
Rajkumar Manoharan9dc08ec2012-06-04 16:28:20 +0530[diff] [blame]3626 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3627 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3628
3629 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
Sujith Manoharanb21e3e12013-08-05 15:08:27 +0530[diff] [blame]3630 if (AR_SREV_9485(ah) && common->bt_ant_diversity) {
John W. Linville53b2f822013-08-28 11:05:36 -0400[diff] [blame]3631 value &= ~AR_SWITCH_TABLE_COM2_ALL;
3632 value |= ah->config.ant_ctrl_comm2g_switch_enable;
Sujith Manoharanb21e3e12013-08-05 15:08:27 +0530[diff] [blame]3633
3634 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3635 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3636
Sujith Manoharanef95e582013-03-04 12:42:55 +0530[diff] [blame]3637 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) {
3638 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3639 REG_RMW_FIELD(ah, switch_chain_reg[0],
3640 AR_SWITCH_TABLE_ALL, value);
3641 }
3642
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3643 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3644 if ((ah->rxchainmask & BIT(chain)) ||
3645 (ah->txchainmask & BIT(chain))) {
3646 value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3647 is2ghz);
3648 REG_RMW_FIELD(ah, switch_chain_reg[chain],
3649 AR_SWITCH_TABLE_ALL, value);
3650 }
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3651 }
3652
Sujith Manoharana4a29542012-09-10 09:20:03 +0530[diff] [blame]3653 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3654 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3655 /*
3656 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3657 * are the fields present
3658 */
3659 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3660 regval &= (~AR_ANT_DIV_CTRL_ALL);
3661 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3662 /* enable_lnadiv */
Sujith Manoharan9aa49ea2012-09-11 10:46:38 +0530[diff] [blame]3663 regval &= (~AR_PHY_ANT_DIV_LNADIV);
3664 regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
Sujith Manoharan362cd032012-09-16 08:06:36 +0530[diff] [blame]3665
Sujith Manoharanb21e3e12013-08-05 15:08:27 +0530[diff] [blame]3666 if (AR_SREV_9485(ah) && common->bt_ant_diversity)
3667 regval |= AR_ANT_DIV_ENABLE;
3668
Sujith Manoharan362cd032012-09-16 08:06:36 +0530[diff] [blame]3669 if (AR_SREV_9565(ah)) {
Sujith Manoharan7bdea962013-08-04 14:22:00 +0530[diff] [blame]3670 if (common->bt_ant_diversity) {
Sujith Manoharan362cd032012-09-16 08:06:36 +0530[diff] [blame]3671 regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S);
Sujith Manoharanc9468682013-09-02 13:59:01 +0530[diff] [blame]3672
3673 REG_SET_BIT(ah, AR_PHY_RESTART,
3674 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
3675
3676 /* Force WLAN LNA diversity ON */
3677 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
3678 AR_BTCOEX_WL_LNADIV_FORCE_ON);
Sujith Manoharan362cd032012-09-16 08:06:36 +0530[diff] [blame]3679 } else {
3680 regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S);
3681 regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S);
Sujith Manoharanc9468682013-09-02 13:59:01 +0530[diff] [blame]3682
3683 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
3684 (1 << AR_PHY_ANT_SW_RX_PROT_S));
3685
3686 /* Force WLAN LNA diversity OFF */
3687 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
3688 AR_BTCOEX_WL_LNADIV_FORCE_ON);
Sujith Manoharan362cd032012-09-16 08:06:36 +0530[diff] [blame]3689 }
3690 }
3691
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3692 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3693
Sujith Manoharanb21e3e12013-08-05 15:08:27 +0530[diff] [blame]3694 /* enable fast_div */
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3695 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3696 regval &= (~AR_FAST_DIV_ENABLE);
Sujith Manoharan9aa49ea2012-09-11 10:46:38 +0530[diff] [blame]3697 regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
Sujith Manoharanb21e3e12013-08-05 15:08:27 +0530[diff] [blame]3698
Sujith Manoharanc9468682013-09-02 13:59:01 +0530[diff] [blame]3699 if ((AR_SREV_9485(ah) || AR_SREV_9565(ah))
3700 && common->bt_ant_diversity)
Sujith Manoharanb21e3e12013-08-05 15:08:27 +0530[diff] [blame]3701 regval |= AR_FAST_DIV_ENABLE;
3702
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3703 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
Sujith Manoharan915154b2012-09-16 08:05:23 +0530[diff] [blame]3704
3705 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3706 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3707 /*
3708 * clear bits 25-30 main_lnaconf, alt_lnaconf,
3709 * main_tb, alt_tb
3710 */
Sujith Manoharan9aa49ea2012-09-11 10:46:38 +0530[diff] [blame]3711 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
3712 AR_PHY_ANT_DIV_ALT_LNACONF |
3713 AR_PHY_ANT_DIV_ALT_GAINTB |
3714 AR_PHY_ANT_DIV_MAIN_GAINTB));
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3715 /* by default use LNA1 for the main antenna */
Sujith Manoharanc2b83592013-07-23 16:25:17 +0530[diff] [blame]3716 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
Sujith Manoharan9aa49ea2012-09-11 10:46:38 +0530[diff] [blame]3717 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
Sujith Manoharanc2b83592013-07-23 16:25:17 +0530[diff] [blame]3718 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
Sujith Manoharan9aa49ea2012-09-11 10:46:38 +0530[diff] [blame]3719 AR_PHY_ANT_DIV_ALT_LNACONF_S);
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3720 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3721 }
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3722 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3723}
3724
3725static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3726{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3727 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3728 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3729 int drive_strength;
3730 unsigned long reg;
3731
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3732 drive_strength = pBase->miscConfiguration & BIT(0);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3733 if (!drive_strength)
3734 return;
3735
3736 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3737 reg &= ~0x00ffffc0;
3738 reg |= 0x5 << 21;
3739 reg |= 0x5 << 18;
3740 reg |= 0x5 << 15;
3741 reg |= 0x5 << 12;
3742 reg |= 0x5 << 9;
3743 reg |= 0x5 << 6;
3744 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3745
3746 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3747 reg &= ~0xffffffe0;
3748 reg |= 0x5 << 29;
3749 reg |= 0x5 << 26;
3750 reg |= 0x5 << 23;
3751 reg |= 0x5 << 20;
3752 reg |= 0x5 << 17;
3753 reg |= 0x5 << 14;
3754 reg |= 0x5 << 11;
3755 reg |= 0x5 << 8;
3756 reg |= 0x5 << 5;
3757 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3758
3759 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3760 reg &= ~0xff800000;
3761 reg |= 0x5 << 29;
3762 reg |= 0x5 << 26;
3763 reg |= 0x5 << 23;
3764 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3765}
3766
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3767static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3768 struct ath9k_channel *chan)
3769{
3770 int f[3], t[3];
3771 u16 value;
3772 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3773
3774 if (chain >= 0 && chain < 3) {
3775 if (IS_CHAN_2GHZ(chan))
3776 return eep->modalHeader2G.xatten1DB[chain];
3777 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3778 t[0] = eep->base_ext2.xatten1DBLow[chain];
3779 f[0] = 5180;
3780 t[1] = eep->modalHeader5G.xatten1DB[chain];
3781 f[1] = 5500;
3782 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3783 f[2] = 5785;
3784 value = ar9003_hw_power_interpolate((s32) chan->channel,
3785 f, t, 3);
3786 return value;
3787 } else
3788 return eep->modalHeader5G.xatten1DB[chain];
3789 }
3790
3791 return 0;
3792}
3793
3794
3795static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3796 struct ath9k_channel *chan)
3797{
3798 int f[3], t[3];
3799 u16 value;
3800 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3801
3802 if (chain >= 0 && chain < 3) {
3803 if (IS_CHAN_2GHZ(chan))
3804 return eep->modalHeader2G.xatten1Margin[chain];
3805 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3806 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3807 f[0] = 5180;
3808 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3809 f[1] = 5500;
3810 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3811 f[2] = 5785;
3812 value = ar9003_hw_power_interpolate((s32) chan->channel,
3813 f, t, 3);
3814 return value;
3815 } else
3816 return eep->modalHeader5G.xatten1Margin[chain];
3817 }
3818
3819 return 0;
3820}
3821
3822static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3823{
3824 int i;
3825 u16 value;
3826 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3827 AR_PHY_EXT_ATTEN_CTL_1,
3828 AR_PHY_EXT_ATTEN_CTL_2,
3829 };
3830
Sujith Manoharanef95e582013-03-04 12:42:55 +0530[diff] [blame]3831 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) {
3832 value = ar9003_hw_atten_chain_get(ah, 1, chan);
3833 REG_RMW_FIELD(ah, ext_atten_reg[0],
3834 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3835
3836 value = ar9003_hw_atten_chain_get_margin(ah, 1, chan);
3837 REG_RMW_FIELD(ah, ext_atten_reg[0],
3838 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3839 value);
3840 }
3841
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3842 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3843 for (i = 0; i < 3; i++) {
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3844 if (ah->txchainmask & BIT(i)) {
3845 value = ar9003_hw_atten_chain_get(ah, i, chan);
3846 REG_RMW_FIELD(ah, ext_atten_reg[i],
3847 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3848
Sujith Manoharan9b60b642013-06-13 22:51:26 +0530[diff] [blame]3849 if (AR_SREV_9485(ah) &&
3850 (ar9003_hw_get_rx_gain_idx(ah) == 0) &&
3851 ah->config.xatten_margin_cfg)
3852 value = 5;
3853 else
3854 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3855
Sujith Manoharane083a422013-08-19 11:04:01 +0530[diff] [blame]3856 if (ah->config.alt_mingainidx)
3857 REG_RMW_FIELD(ah, AR_PHY_EXT_ATTEN_CTL_0,
3858 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3859 value);
3860
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3861 REG_RMW_FIELD(ah, ext_atten_reg[i],
3862 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3863 value);
3864 }
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3865 }
3866}
3867
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3868static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3869{
3870 int timeout = 100;
3871
3872 while (pmu_set != REG_READ(ah, pmu_reg)) {
3873 if (timeout-- == 0)
3874 return false;
3875 REG_WRITE(ah, pmu_reg, pmu_set);
3876 udelay(10);
3877 }
3878
3879 return true;
3880}
3881
Felix Fietkaubfc441a2012-05-24 14:32:22 +0200[diff] [blame]3882void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3883{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3884 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3885 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3886 u32 reg_val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3887
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3888 if (pBase->featureEnable & BIT(4)) {
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3889 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3890 int reg_pmu_set;
3891
3892 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3893 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3894 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3895 return;
3896
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3897 if (AR_SREV_9330(ah)) {
3898 if (ah->is_clk_25mhz) {
3899 reg_pmu_set = (3 << 1) | (8 << 4) |
3900 (3 << 8) | (1 << 14) |
3901 (6 << 17) | (1 << 20) |
3902 (3 << 24);
3903 } else {
3904 reg_pmu_set = (4 << 1) | (7 << 4) |
3905 (3 << 8) | (1 << 14) |
3906 (6 << 17) | (1 << 20) |
3907 (3 << 24);
3908 }
3909 } else {
3910 reg_pmu_set = (5 << 1) | (7 << 4) |
Rajkumar Manoharan1fa707a2011-07-29 17:38:17 +0530[diff] [blame]3911 (2 << 8) | (2 << 14) |
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3912 (6 << 17) | (1 << 20) |
3913 (3 << 24) | (1 << 28);
3914 }
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3915
3916 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3917 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3918 return;
3919
3920 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3921 | (4 << 26);
3922 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3923 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3924 return;
3925
3926 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3927 | (1 << 21);
3928 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3929 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3930 return;
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530[diff] [blame]3931 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah) ||
3932 AR_SREV_9561(ah)) {
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3933 reg_val = le32_to_cpu(pBase->swreg);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3934 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530[diff] [blame]3935
3936 if (AR_SREV_9561(ah))
3937 REG_WRITE(ah, AR_PHY_PMU2, 0x10200000);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3938 } else {
3939 /* Internal regulator is ON. Write swreg register. */
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3940 reg_val = le32_to_cpu(pBase->swreg);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3941 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3942 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3943 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3944 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3945 /* Set REG_CONTROL1.SWREG_PROGRAM */
3946 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3947 REG_READ(ah,
3948 AR_RTC_REG_CONTROL1) |
3949 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3950 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3951 } else {
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3952 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3953 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3954 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3955 AR_PHY_PMU2_PGM))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3956 udelay(10);
3957
3958 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3959 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3960 AR_PHY_PMU1_PWD))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3961 udelay(10);
3962 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3963 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3964 AR_PHY_PMU2_PGM))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3965 udelay(10);
Sujith Manoharana4a29542012-09-10 09:20:03 +0530[diff] [blame]3966 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3967 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3968 else {
3969 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3970 AR_RTC_FORCE_SWREG_PRD;
3971 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3972 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3973 }
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3974
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3975}
3976
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame]3977static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3978{
3979 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3980 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3981
Sujith Manoharan2c323052013-12-31 08:12:02 +0530[diff] [blame]3982 if (AR_SREV_9340(ah) || AR_SREV_9531(ah))
Felix Fietkau08a4a1a2012-07-15 19:53:40 +0200[diff] [blame]3983 return;
3984
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame]3985 if (eep->baseEepHeader.featureEnable & 0x40) {
3986 tuning_caps_param &= 0x7f;
3987 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3988 tuning_caps_param);
3989 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3990 tuning_caps_param);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3991 }
3992}
3993
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3994static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3995{
3996 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3997 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3998 int quick_drop;
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3999 s32 t[3], f[3] = {5180, 5500, 5785};
4000
Sujith Manoharan93c1cfb2013-11-26 07:21:08 +0530[diff] [blame]4001 if (!(pBase->miscConfiguration & BIT(4)))
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]4002 return;
4003
Sujith Manoharan93c1cfb2013-11-26 07:21:08 +0530[diff] [blame]4004 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) {
4005 if (freq < 4000) {
4006 quick_drop = eep->modalHeader2G.quick_drop;
4007 } else {
4008 t[0] = eep->base_ext1.quick_drop_low;
4009 t[1] = eep->modalHeader5G.quick_drop;
4010 t[2] = eep->base_ext1.quick_drop_high;
4011 quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
4012 }
4013 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]4014 }
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]4015}
4016
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]4017static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
Rajkumar Manoharan202bff02011-11-08 14:19:33 +0530[diff] [blame]4018{
Rajkumar Manoharan202bff02011-11-08 14:19:33 +0530[diff] [blame]4019 u32 value;
4020
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]4021 value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
Rajkumar Manoharan202bff02011-11-08 14:19:33 +0530[diff] [blame]4022
4023 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4024 AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
4025 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4026 AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
4027}
4028
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]4029static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
Felix Fietkau89be49e2012-07-15 19:53:37 +0200[diff] [blame]4030{
4031 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4032 u8 xpa_ctl;
4033
4034 if (!(eep->baseEepHeader.featureEnable & 0x80))
4035 return;
4036
Sujith Manoharan2c323052013-12-31 08:12:02 +0530[diff] [blame]4037 if (!AR_SREV_9300(ah) &&
4038 !AR_SREV_9340(ah) &&
4039 !AR_SREV_9580(ah) &&
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530[diff] [blame]4040 !AR_SREV_9531(ah) &&
4041 !AR_SREV_9561(ah))
Felix Fietkau89be49e2012-07-15 19:53:37 +0200[diff] [blame]4042 return;
4043
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]4044 xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
4045 if (is2ghz)
Felix Fietkau89be49e2012-07-15 19:53:37 +0200[diff] [blame]4046 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4047 AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl);
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]4048 else
Felix Fietkau89be49e2012-07-15 19:53:37 +0200[diff] [blame]4049 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
4050 AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
Felix Fietkau89be49e2012-07-15 19:53:37 +0200[diff] [blame]4051}
4052
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]4053static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
4054{
4055 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4056 u8 bias;
4057
Sujith Manoharana1783a72013-11-26 07:21:39 +0530[diff] [blame]4058 if (!(eep->baseEepHeader.miscConfiguration & 0x40))
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]4059 return;
4060
4061 if (!AR_SREV_9300(ah))
4062 return;
4063
4064 bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
4065 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
4066 bias & 0x3);
4067 bias >>= 2;
4068 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
4069 bias & 0x3);
4070 bias >>= 2;
4071 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
4072 bias & 0x3);
4073}
4074
Rajkumar Manoharan02eba422012-09-07 12:15:15 +0530[diff] [blame]4075static int ar9003_hw_get_thermometer(struct ath_hw *ah)
4076{
4077 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4078 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
4079 int thermometer = (pBase->miscConfiguration >> 1) & 0x3;
4080
4081 return --thermometer;
4082}
4083
4084static void ar9003_hw_thermometer_apply(struct ath_hw *ah)
4085{
Sujith Manoharan89b6e352014-11-16 06:11:05 +0530[diff] [blame]4086 struct ath9k_hw_capabilities *pCap = &ah->caps;
Rajkumar Manoharan02eba422012-09-07 12:15:15 +0530[diff] [blame]4087 int thermometer = ar9003_hw_get_thermometer(ah);
4088 u8 therm_on = (thermometer < 0) ? 0 : 1;
4089
4090 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
4091 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
Sujith Manoharan89b6e352014-11-16 06:11:05 +0530[diff] [blame]4092 if (pCap->chip_chainmask & BIT(1))
Rajkumar Manoharan02eba422012-09-07 12:15:15 +0530[diff] [blame]4093 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4094 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
Sujith Manoharan89b6e352014-11-16 06:11:05 +0530[diff] [blame]4095 if (pCap->chip_chainmask & BIT(2))
Rajkumar Manoharan02eba422012-09-07 12:15:15 +0530[diff] [blame]4096 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4097 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4098
Ivan Safonov0fef3c72016-03-18 13:16:26 +1100[diff] [blame]4099 therm_on = thermometer == 0;
Rajkumar Manoharan02eba422012-09-07 12:15:15 +0530[diff] [blame]4100 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
4101 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
Sujith Manoharan89b6e352014-11-16 06:11:05 +0530[diff] [blame]4102 if (pCap->chip_chainmask & BIT(1)) {
Ivan Safonov0fef3c72016-03-18 13:16:26 +1100[diff] [blame]4103 therm_on = thermometer == 1;
Rajkumar Manoharan02eba422012-09-07 12:15:15 +0530[diff] [blame]4104 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4105 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4106 }
Sujith Manoharan89b6e352014-11-16 06:11:05 +0530[diff] [blame]4107 if (pCap->chip_chainmask & BIT(2)) {
Ivan Safonov0fef3c72016-03-18 13:16:26 +1100[diff] [blame]4108 therm_on = thermometer == 2;
Rajkumar Manoharan02eba422012-09-07 12:15:15 +0530[diff] [blame]4109 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4110 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4111 }
4112}
4113
Rajkumar Manoharan80fe43f2012-09-07 12:15:16 +0530[diff] [blame]4114static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah)
4115{
4116 u32 data, ko, kg;
4117
Sujith Manoharan2b5e54e2013-06-24 18:18:46 +0530[diff] [blame]4118 if (!AR_SREV_9462_20_OR_LATER(ah))
Rajkumar Manoharan80fe43f2012-09-07 12:15:16 +0530[diff] [blame]4119 return;
Sujith Manoharan2b5e54e2013-06-24 18:18:46 +0530[diff] [blame]4120
Rajkumar Manoharan80fe43f2012-09-07 12:15:16 +0530[diff] [blame]4121 ar9300_otp_read_word(ah, 1, &data);
4122 ko = data & 0xff;
4123 kg = (data >> 8) & 0xff;
4124 if (ko || kg) {
4125 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4126 AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET, ko);
4127 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4128 AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN,
4129 kg + 256);
4130 }
4131}
4132
Sujith Manoharan3533bf62013-12-18 09:53:23 +0530[diff] [blame]4133static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah,
4134 bool is2ghz)
4135{
4136 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4137 const u_int32_t cca_ctrl[AR9300_MAX_CHAINS] = {
4138 AR_PHY_CCA_CTRL_0,
4139 AR_PHY_CCA_CTRL_1,
4140 AR_PHY_CCA_CTRL_2,
4141 };
4142 int chain;
4143 u32 val;
4144
4145 if (is2ghz) {
4146 if (!(eep->base_ext1.misc_enable & BIT(2)))
4147 return;
4148 } else {
4149 if (!(eep->base_ext1.misc_enable & BIT(3)))
4150 return;
4151 }
4152
4153 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
4154 if (!(ah->caps.tx_chainmask & BIT(chain)))
4155 continue;
4156
4157 val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain];
4158 REG_RMW_FIELD(ah, cca_ctrl[chain],
4159 AR_PHY_EXT_CCA0_THRESH62_1, val);
4160 }
4161
4162}
4163
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4164static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
4165 struct ath9k_channel *chan)
4166{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]4167 bool is2ghz = IS_CHAN_2GHZ(chan);
4168 ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
4169 ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
4170 ar9003_hw_ant_ctrl_apply(ah, is2ghz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4171 ar9003_hw_drive_strength_apply(ah);
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]4172 ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]4173 ar9003_hw_atten_apply(ah, chan);
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]4174 ar9003_hw_quick_drop_apply(ah, chan->channel);
Sujith Manoharan2c323052013-12-31 08:12:02 +0530[diff] [blame]4175 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9531(ah))
Vasanthakumar Thiagarajan3594bea2011-04-19 19:29:12 +0530[diff] [blame]4176 ar9003_hw_internal_regulator_apply(ah);
Felix Fietkau08a4a1a2012-07-15 19:53:40 +0200[diff] [blame]4177 ar9003_hw_apply_tuning_caps(ah);
Sven Eckelmannaaab50f2016-06-29 19:29:30 +0300[diff] [blame]4178 ar9003_hw_apply_minccapwr_thresh(ah, is2ghz);
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]4179 ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
Rajkumar Manoharan02eba422012-09-07 12:15:15 +0530[diff] [blame]4180 ar9003_hw_thermometer_apply(ah);
Rajkumar Manoharan80fe43f2012-09-07 12:15:16 +0530[diff] [blame]4181 ar9003_hw_thermo_cal_apply(ah);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4182}
4183
4184static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
4185 struct ath9k_channel *chan)
4186{
4187}
4188
4189/*
4190 * Returns the interpolated y value corresponding to the specified x value
4191 * from the np ordered pairs of data (px,py).
4192 * The pairs do not have to be in any order.
4193 * If the specified x value is less than any of the px,
4194 * the returned y value is equal to the py for the lowest px.
4195 * If the specified x value is greater than any of the px,
4196 * the returned y value is equal to the py for the highest px.
4197 */
4198static int ar9003_hw_power_interpolate(int32_t x,
4199 int32_t *px, int32_t *py, u_int16_t np)
4200{
4201 int ip = 0;
4202 int lx = 0, ly = 0, lhave = 0;
4203 int hx = 0, hy = 0, hhave = 0;
4204 int dx = 0;
4205 int y = 0;
4206
4207 lhave = 0;
4208 hhave = 0;
4209
4210 /* identify best lower and higher x calibration measurement */
4211 for (ip = 0; ip < np; ip++) {
4212 dx = x - px[ip];
4213
4214 /* this measurement is higher than our desired x */
4215 if (dx <= 0) {
4216 if (!hhave || dx > (x - hx)) {
4217 /* new best higher x measurement */
4218 hx = px[ip];
4219 hy = py[ip];
4220 hhave = 1;
4221 }
4222 }
4223 /* this measurement is lower than our desired x */
4224 if (dx >= 0) {
4225 if (!lhave || dx < (x - lx)) {
4226 /* new best lower x measurement */
4227 lx = px[ip];
4228 ly = py[ip];
4229 lhave = 1;
4230 }
4231 }
4232 }
4233
4234 /* the low x is good */
4235 if (lhave) {
4236 /* so is the high x */
4237 if (hhave) {
4238 /* they're the same, so just pick one */
4239 if (hx == lx)
4240 y = ly;
4241 else /* interpolate */
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4242 y = interpolate(x, lx, hx, ly, hy);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4243 } else /* only low is good, use it */
4244 y = ly;
4245 } else if (hhave) /* only high is good, use it */
4246 y = hy;
4247 else /* nothing is good,this should never happen unless np=0, ???? */
4248 y = -(1 << 30);
4249 return y;
4250}
4251
4252static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4253 u16 rateIndex, u16 freq, bool is2GHz)
4254{
4255 u16 numPiers, i;
4256 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4257 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4258 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4259 struct cal_tgt_pow_legacy *pEepromTargetPwr;
4260 u8 *pFreqBin;
4261
4262 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]4263 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4264 pEepromTargetPwr = eep->calTargetPower2G;
4265 pFreqBin = eep->calTarget_freqbin_2G;
4266 } else {
4267 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4268 pEepromTargetPwr = eep->calTargetPower5G;
4269 pFreqBin = eep->calTarget_freqbin_5G;
4270 }
4271
4272 /*
4273 * create array of channels and targetpower from
4274 * targetpower piers stored on eeprom
4275 */
4276 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame]4277 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4278 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4279 }
4280
4281 /* interpolate to get target power for given frequency */
4282 return (u8) ar9003_hw_power_interpolate((s32) freq,
4283 freqArray,
4284 targetPowerArray, numPiers);
4285}
4286
4287static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4288 u16 rateIndex,
4289 u16 freq, bool is2GHz)
4290{
4291 u16 numPiers, i;
4292 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4293 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4294 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4295 struct cal_tgt_pow_ht *pEepromTargetPwr;
4296 u8 *pFreqBin;
4297
4298 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]4299 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4300 pEepromTargetPwr = eep->calTargetPower2GHT20;
4301 pFreqBin = eep->calTarget_freqbin_2GHT20;
4302 } else {
4303 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4304 pEepromTargetPwr = eep->calTargetPower5GHT20;
4305 pFreqBin = eep->calTarget_freqbin_5GHT20;
4306 }
4307
4308 /*
4309 * create array of channels and targetpower
4310 * from targetpower piers stored on eeprom
4311 */
4312 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame]4313 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4314 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4315 }
4316
4317 /* interpolate to get target power for given frequency */
4318 return (u8) ar9003_hw_power_interpolate((s32) freq,
4319 freqArray,
4320 targetPowerArray, numPiers);
4321}
4322
4323static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4324 u16 rateIndex,
4325 u16 freq, bool is2GHz)
4326{
4327 u16 numPiers, i;
4328 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4329 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4330 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4331 struct cal_tgt_pow_ht *pEepromTargetPwr;
4332 u8 *pFreqBin;
4333
4334 if (is2GHz) {
4335 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4336 pEepromTargetPwr = eep->calTargetPower2GHT40;
4337 pFreqBin = eep->calTarget_freqbin_2GHT40;
4338 } else {
4339 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4340 pEepromTargetPwr = eep->calTargetPower5GHT40;
4341 pFreqBin = eep->calTarget_freqbin_5GHT40;
4342 }
4343
4344 /*
4345 * create array of channels and targetpower from
4346 * targetpower piers stored on eeprom
4347 */
4348 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame]4349 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4350 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4351 }
4352
4353 /* interpolate to get target power for given frequency */
4354 return (u8) ar9003_hw_power_interpolate((s32) freq,
4355 freqArray,
4356 targetPowerArray, numPiers);
4357}
4358
4359static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4360 u16 rateIndex, u16 freq)
4361{
4362 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4363 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4364 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4365 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4366 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4367 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4368
4369 /*
4370 * create array of channels and targetpower from
4371 * targetpower piers stored on eeprom
4372 */
4373 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame]4374 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4375 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4376 }
4377
4378 /* interpolate to get target power for given frequency */
4379 return (u8) ar9003_hw_power_interpolate((s32) freq,
4380 freqArray,
4381 targetPowerArray, numPiers);
4382}
4383
Lorenzo Bianconi23f53dd32014-11-25 00:21:40 +0100[diff] [blame]4384static void ar9003_hw_selfgen_tpc_txpower(struct ath_hw *ah,
4385 struct ath9k_channel *chan,
4386 u8 *pwr_array)
4387{
4388 u32 val;
4389
4390 /* target power values for self generated frames (ACK,RTS/CTS) */
4391 if (IS_CHAN_2GHZ(chan)) {
4392 val = SM(pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_ACK) |
4393 SM(pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_CTS) |
4394 SM(0x3f, AR_TPC_CHIRP) | SM(0x3f, AR_TPC_RPT);
4395 } else {
4396 val = SM(pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_ACK) |
4397 SM(pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_CTS) |
4398 SM(0x3f, AR_TPC_CHIRP) | SM(0x3f, AR_TPC_RPT);
4399 }
4400 REG_WRITE(ah, AR_TPC, val);
4401}
4402
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4403/* Set tx power registers to array of values passed in */
Helmut Schaa8569f592016-04-28 16:45:04 +0200[diff] [blame]4404int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4405{
4406#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4407 /* make sure forced gain is not set */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4408 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4409
4410 /* Write the OFDM power per rate set */
4411
4412 /* 6 (LSB), 9, 12, 18 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4413 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4414 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4415 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4416 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4417 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4418
4419 /* 24 (LSB), 36, 48, 54 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4420 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4421 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4422 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4423 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4424 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4425
4426 /* Write the CCK power per rate set */
4427
4428 /* 1L (LSB), reserved, 2L, 2S (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4429 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4430 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4431 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4432 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4433 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4434
4435 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4436 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4437 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4438 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4439 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4440 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4441 );
4442
Luis R. Rodriguezcf3a03b2011-05-04 14:01:26 -0700[diff] [blame]4443 /* Write the power for duplicated frames - HT40 */
4444
4445 /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
Alex Hacker8d7763b2011-08-03 17:41:54 +0600[diff] [blame]4446 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
Luis R. Rodriguezcf3a03b2011-05-04 14:01:26 -0700[diff] [blame]4447 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4448 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4449 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4450 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4451 );
4452
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4453 /* Write the HT20 power per rate set */
4454
4455 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4456 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4457 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4458 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4459 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4460 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4461 );
4462
4463 /* 6 (LSB), 7, 12, 13 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4464 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4465 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4466 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4467 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4468 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4469 );
4470
4471 /* 14 (LSB), 15, 20, 21 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4472 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4473 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4474 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4475 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4476 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4477 );
4478
4479 /* Mixed HT20 and HT40 rates */
4480
4481 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4482 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4483 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4484 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4485 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4486 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4487 );
4488
4489 /*
4490 * Write the HT40 power per rate set
4491 * correct PAR difference between HT40 and HT20/LEGACY
4492 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4493 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4494 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4495 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4496 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4497 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4498 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4499 );
4500
4501 /* 6 (LSB), 7, 12, 13 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4502 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4503 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4504 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4505 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4506 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4507 );
4508
4509 /* 14 (LSB), 15, 20, 21 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4510 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4511 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4512 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4513 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4514 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4515 );
4516
4517 return 0;
4518#undef POW_SM
4519}
4520
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]4521static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
4522 u8 *targetPowerValT2,
4523 bool is2GHz)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4524{
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4525 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4526 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4527 is2GHz);
4528 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4529 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4530 is2GHz);
4531 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4532 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4533 is2GHz);
4534 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4535 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4536 is2GHz);
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]4537}
4538
4539static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
4540 u8 *targetPowerValT2)
4541{
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4542 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4543 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4544 freq);
4545 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4546 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4547 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4548 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4549 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4550 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]4551}
4552
4553static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
4554 u8 *targetPowerValT2, bool is2GHz)
4555{
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4556 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4557 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4558 is2GHz);
4559 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4560 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4561 freq, is2GHz);
4562 targetPowerValT2[ALL_TARGET_HT20_4] =
4563 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4564 is2GHz);
4565 targetPowerValT2[ALL_TARGET_HT20_5] =
4566 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4567 is2GHz);
4568 targetPowerValT2[ALL_TARGET_HT20_6] =
4569 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4570 is2GHz);
4571 targetPowerValT2[ALL_TARGET_HT20_7] =
4572 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4573 is2GHz);
4574 targetPowerValT2[ALL_TARGET_HT20_12] =
4575 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4576 is2GHz);
4577 targetPowerValT2[ALL_TARGET_HT20_13] =
4578 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4579 is2GHz);
4580 targetPowerValT2[ALL_TARGET_HT20_14] =
4581 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4582 is2GHz);
4583 targetPowerValT2[ALL_TARGET_HT20_15] =
4584 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4585 is2GHz);
4586 targetPowerValT2[ALL_TARGET_HT20_20] =
4587 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4588 is2GHz);
4589 targetPowerValT2[ALL_TARGET_HT20_21] =
4590 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4591 is2GHz);
4592 targetPowerValT2[ALL_TARGET_HT20_22] =
4593 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4594 is2GHz);
4595 targetPowerValT2[ALL_TARGET_HT20_23] =
4596 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4597 is2GHz);
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]4598}
4599
4600static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
4601 u16 freq,
4602 u8 *targetPowerValT2,
4603 bool is2GHz)
4604{
4605 /* XXX: hard code for now, need to get from eeprom struct */
4606 u8 ht40PowerIncForPdadc = 0;
4607
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4608 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4609 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4610 is2GHz) + ht40PowerIncForPdadc;
4611 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4612 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4613 freq,
4614 is2GHz) + ht40PowerIncForPdadc;
4615 targetPowerValT2[ALL_TARGET_HT40_4] =
4616 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4617 is2GHz) + ht40PowerIncForPdadc;
4618 targetPowerValT2[ALL_TARGET_HT40_5] =
4619 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4620 is2GHz) + ht40PowerIncForPdadc;
4621 targetPowerValT2[ALL_TARGET_HT40_6] =
4622 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4623 is2GHz) + ht40PowerIncForPdadc;
4624 targetPowerValT2[ALL_TARGET_HT40_7] =
4625 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4626 is2GHz) + ht40PowerIncForPdadc;
4627 targetPowerValT2[ALL_TARGET_HT40_12] =
4628 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4629 is2GHz) + ht40PowerIncForPdadc;
4630 targetPowerValT2[ALL_TARGET_HT40_13] =
4631 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4632 is2GHz) + ht40PowerIncForPdadc;
4633 targetPowerValT2[ALL_TARGET_HT40_14] =
4634 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4635 is2GHz) + ht40PowerIncForPdadc;
4636 targetPowerValT2[ALL_TARGET_HT40_15] =
4637 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4638 is2GHz) + ht40PowerIncForPdadc;
4639 targetPowerValT2[ALL_TARGET_HT40_20] =
4640 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4641 is2GHz) + ht40PowerIncForPdadc;
4642 targetPowerValT2[ALL_TARGET_HT40_21] =
4643 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4644 is2GHz) + ht40PowerIncForPdadc;
4645 targetPowerValT2[ALL_TARGET_HT40_22] =
4646 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4647 is2GHz) + ht40PowerIncForPdadc;
4648 targetPowerValT2[ALL_TARGET_HT40_23] =
4649 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4650 is2GHz) + ht40PowerIncForPdadc;
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]4651}
4652
4653static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
4654 struct ath9k_channel *chan,
4655 u8 *targetPowerValT2)
4656{
4657 bool is2GHz = IS_CHAN_2GHZ(chan);
4658 unsigned int i = 0;
4659 struct ath_common *common = ath9k_hw_common(ah);
4660 u16 freq = chan->channel;
4661
4662 if (is2GHz)
4663 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
4664
4665 ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
4666 ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
4667
4668 if (IS_CHAN_HT40(chan))
4669 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
4670 is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4671
Joe Perchesa1cbc7a2010-12-02 19:12:38 -0800[diff] [blame]4672 for (i = 0; i < ar9300RateSize; i++) {
Sujith Manoharandf401902013-06-18 10:13:40 +0530[diff] [blame]4673 ath_dbg(common, REGULATORY, "TPC[%02d] 0x%08x\n",
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4674 i, targetPowerValT2[i]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4675 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4676}
4677
4678static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4679 int mode,
4680 int ipier,
4681 int ichain,
4682 int *pfrequency,
4683 int *pcorrection,
4684 int *ptemperature, int *pvoltage)
4685{
4686 u8 *pCalPier;
4687 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4688 int is2GHz;
4689 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4690 struct ath_common *common = ath9k_hw_common(ah);
4691
4692 if (ichain >= AR9300_MAX_CHAINS) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4693 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4694 "Invalid chain index, must be less than %d\n",
4695 AR9300_MAX_CHAINS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4696 return -1;
4697 }
4698
4699 if (mode) { /* 5GHz */
4700 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4701 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4702 "Invalid 5GHz cal pier index, must be less than %d\n",
4703 AR9300_NUM_5G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4704 return -1;
4705 }
4706 pCalPier = &(eep->calFreqPier5G[ipier]);
4707 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4708 is2GHz = 0;
4709 } else {
4710 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4711 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4712 "Invalid 2GHz cal pier index, must be less than %d\n",
4713 AR9300_NUM_2G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4714 return -1;
4715 }
4716
4717 pCalPier = &(eep->calFreqPier2G[ipier]);
4718 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4719 is2GHz = 1;
4720 }
4721
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame]4722 *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4723 *pcorrection = pCalPierStruct->refPower;
4724 *ptemperature = pCalPierStruct->tempMeas;
4725 *pvoltage = pCalPierStruct->voltMeas;
4726
4727 return 0;
4728}
4729
Sujith Manoharan2d7caef2013-01-08 20:57:52 +0530[diff] [blame]4730static void ar9003_hw_power_control_override(struct ath_hw *ah,
4731 int frequency,
4732 int *correction,
4733 int *voltage, int *temperature)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4734{
Sujith Manoharan2d7caef2013-01-08 20:57:52 +0530[diff] [blame]4735 int temp_slope = 0, temp_slope1 = 0, temp_slope2 = 0;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4736 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Sujith Manoharan2d7caef2013-01-08 20:57:52 +0530[diff] [blame]4737 int f[8], t[8], t1[3], t2[3], i;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4738
4739 REG_RMW(ah, AR_PHY_TPC_11_B0,
4740 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4741 AR_PHY_TPC_OLPC_GAIN_DELTA);
Vasanthakumar Thiagarajan5f139eb2010-12-06 04:27:53 -0800[diff] [blame]4742 if (ah->caps.tx_chainmask & BIT(1))
4743 REG_RMW(ah, AR_PHY_TPC_11_B1,
4744 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4745 AR_PHY_TPC_OLPC_GAIN_DELTA);
4746 if (ah->caps.tx_chainmask & BIT(2))
4747 REG_RMW(ah, AR_PHY_TPC_11_B2,
4748 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4749 AR_PHY_TPC_OLPC_GAIN_DELTA);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4750
4751 /* enable open loop power control on chip */
4752 REG_RMW(ah, AR_PHY_TPC_6_B0,
4753 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4754 AR_PHY_TPC_6_ERROR_EST_MODE);
Vasanthakumar Thiagarajan5f139eb2010-12-06 04:27:53 -0800[diff] [blame]4755 if (ah->caps.tx_chainmask & BIT(1))
4756 REG_RMW(ah, AR_PHY_TPC_6_B1,
4757 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4758 AR_PHY_TPC_6_ERROR_EST_MODE);
4759 if (ah->caps.tx_chainmask & BIT(2))
4760 REG_RMW(ah, AR_PHY_TPC_6_B2,
4761 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4762 AR_PHY_TPC_6_ERROR_EST_MODE);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4763
4764 /*
4765 * enable temperature compensation
4766 * Need to use register names
4767 */
Sujith Manoharan2d7caef2013-01-08 20:57:52 +0530[diff] [blame]4768 if (frequency < 4000) {
4769 temp_slope = eep->modalHeader2G.tempSlope;
4770 } else {
4771 if (AR_SREV_9550(ah)) {
4772 t[0] = eep->base_ext1.tempslopextension[2];
4773 t1[0] = eep->base_ext1.tempslopextension[3];
4774 t2[0] = eep->base_ext1.tempslopextension[4];
4775 f[0] = 5180;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4776
Sujith Manoharan2d7caef2013-01-08 20:57:52 +0530[diff] [blame]4777 t[1] = eep->modalHeader5G.tempSlope;
4778 t1[1] = eep->base_ext1.tempslopextension[0];
4779 t2[1] = eep->base_ext1.tempslopextension[1];
4780 f[1] = 5500;
4781
4782 t[2] = eep->base_ext1.tempslopextension[5];
4783 t1[2] = eep->base_ext1.tempslopextension[6];
4784 t2[2] = eep->base_ext1.tempslopextension[7];
4785 f[2] = 5785;
4786
4787 temp_slope = ar9003_hw_power_interpolate(frequency,
4788 f, t, 3);
4789 temp_slope1 = ar9003_hw_power_interpolate(frequency,
4790 f, t1, 3);
4791 temp_slope2 = ar9003_hw_power_interpolate(frequency,
4792 f, t2, 3);
4793
4794 goto tempslope;
4795 }
4796
4797 if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) {
4798 for (i = 0; i < 8; i++) {
4799 t[i] = eep->base_ext1.tempslopextension[i];
4800 f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0);
4801 }
4802 temp_slope = ar9003_hw_power_interpolate((s32) frequency,
4803 f, t, 8);
4804 } else if (eep->base_ext2.tempSlopeLow != 0) {
4805 t[0] = eep->base_ext2.tempSlopeLow;
4806 f[0] = 5180;
4807 t[1] = eep->modalHeader5G.tempSlope;
4808 f[1] = 5500;
4809 t[2] = eep->base_ext2.tempSlopeHigh;
4810 f[2] = 5785;
4811 temp_slope = ar9003_hw_power_interpolate((s32) frequency,
4812 f, t, 3);
4813 } else {
4814 temp_slope = eep->modalHeader5G.tempSlope;
4815 }
4816 }
4817
4818tempslope:
Miaoqing Panede6a5e2014-12-19 06:33:59 +0530[diff] [blame]4819 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
Sujith Manoharand65b1272014-03-17 15:02:48 +0530[diff] [blame]4820 u8 txmask = (eep->baseEepHeader.txrxMask & 0xf0) >> 4;
4821
Sujith Manoharan2d7caef2013-01-08 20:57:52 +0530[diff] [blame]4822 /*
4823 * AR955x has tempSlope register for each chain.
4824 * Check whether temp_compensation feature is enabled or not.
4825 */
4826 if (eep->baseEepHeader.featureEnable & 0x1) {
4827 if (frequency < 4000) {
Sujith Manoharand65b1272014-03-17 15:02:48 +0530[diff] [blame]4828 if (txmask & BIT(0))
4829 REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4830 AR_PHY_TPC_19_ALPHA_THERM,
4831 eep->base_ext2.tempSlopeLow);
4832 if (txmask & BIT(1))
4833 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4834 AR_PHY_TPC_19_ALPHA_THERM,
4835 temp_slope);
4836 if (txmask & BIT(2))
4837 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
4838 AR_PHY_TPC_19_ALPHA_THERM,
4839 eep->base_ext2.tempSlopeHigh);
Sujith Manoharan2d7caef2013-01-08 20:57:52 +0530[diff] [blame]4840 } else {
Sujith Manoharand65b1272014-03-17 15:02:48 +0530[diff] [blame]4841 if (txmask & BIT(0))
4842 REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4843 AR_PHY_TPC_19_ALPHA_THERM,
4844 temp_slope);
4845 if (txmask & BIT(1))
4846 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4847 AR_PHY_TPC_19_ALPHA_THERM,
4848 temp_slope1);
4849 if (txmask & BIT(2))
4850 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
4851 AR_PHY_TPC_19_ALPHA_THERM,
4852 temp_slope2);
Sujith Manoharan2d7caef2013-01-08 20:57:52 +0530[diff] [blame]4853 }
4854 } else {
4855 /*
4856 * If temp compensation is not enabled,
4857 * set all registers to 0.
4858 */
Sujith Manoharand65b1272014-03-17 15:02:48 +0530[diff] [blame]4859 if (txmask & BIT(0))
4860 REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4861 AR_PHY_TPC_19_ALPHA_THERM, 0);
4862 if (txmask & BIT(1))
4863 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4864 AR_PHY_TPC_19_ALPHA_THERM, 0);
4865 if (txmask & BIT(2))
4866 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
4867 AR_PHY_TPC_19_ALPHA_THERM, 0);
Sujith Manoharan2d7caef2013-01-08 20:57:52 +0530[diff] [blame]4868 }
4869 } else {
4870 REG_RMW_FIELD(ah, AR_PHY_TPC_19,
4871 AR_PHY_TPC_19_ALPHA_THERM, temp_slope);
4872 }
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]4873
Sujith Manoharan2b5e54e2013-06-24 18:18:46 +0530[diff] [blame]4874 if (AR_SREV_9462_20_OR_LATER(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]4875 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
Sujith Manoharan2d7caef2013-01-08 20:57:52 +0530[diff] [blame]4876 AR_PHY_TPC_19_B1_ALPHA_THERM, temp_slope);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]4877
4878
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4879 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4880 temperature[0]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4881}
4882
4883/* Apply the recorded correction values. */
4884static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4885{
4886 int ichain, ipier, npier;
4887 int mode;
4888 int lfrequency[AR9300_MAX_CHAINS],
4889 lcorrection[AR9300_MAX_CHAINS],
4890 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4891 int hfrequency[AR9300_MAX_CHAINS],
4892 hcorrection[AR9300_MAX_CHAINS],
4893 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4894 int fdiff;
4895 int correction[AR9300_MAX_CHAINS],
4896 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4897 int pfrequency, pcorrection, ptemperature, pvoltage;
4898 struct ath_common *common = ath9k_hw_common(ah);
4899
4900 mode = (frequency >= 4000);
4901 if (mode)
4902 npier = AR9300_NUM_5G_CAL_PIERS;
4903 else
4904 npier = AR9300_NUM_2G_CAL_PIERS;
4905
4906 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4907 lfrequency[ichain] = 0;
4908 hfrequency[ichain] = 100000;
4909 }
4910 /* identify best lower and higher frequency calibration measurement */
4911 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4912 for (ipier = 0; ipier < npier; ipier++) {
4913 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4914 &pfrequency, &pcorrection,
4915 &ptemperature, &pvoltage)) {
4916 fdiff = frequency - pfrequency;
4917
4918 /*
4919 * this measurement is higher than
4920 * our desired frequency
4921 */
4922 if (fdiff <= 0) {
4923 if (hfrequency[ichain] <= 0 ||
4924 hfrequency[ichain] >= 100000 ||
4925 fdiff >
4926 (frequency - hfrequency[ichain])) {
4927 /*
4928 * new best higher
4929 * frequency measurement
4930 */
4931 hfrequency[ichain] = pfrequency;
4932 hcorrection[ichain] =
4933 pcorrection;
4934 htemperature[ichain] =
4935 ptemperature;
4936 hvoltage[ichain] = pvoltage;
4937 }
4938 }
4939 if (fdiff >= 0) {
4940 if (lfrequency[ichain] <= 0
4941 || fdiff <
4942 (frequency - lfrequency[ichain])) {
4943 /*
4944 * new best lower
4945 * frequency measurement
4946 */
4947 lfrequency[ichain] = pfrequency;
4948 lcorrection[ichain] =
4949 pcorrection;
4950 ltemperature[ichain] =
4951 ptemperature;
4952 lvoltage[ichain] = pvoltage;
4953 }
4954 }
4955 }
4956 }
4957 }
4958
4959 /* interpolate */
4960 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4961 ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4962 ichain, frequency, lfrequency[ichain],
4963 lcorrection[ichain], hfrequency[ichain],
4964 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4965 /* they're the same, so just pick one */
4966 if (hfrequency[ichain] == lfrequency[ichain]) {
4967 correction[ichain] = lcorrection[ichain];
4968 voltage[ichain] = lvoltage[ichain];
4969 temperature[ichain] = ltemperature[ichain];
4970 }
4971 /* the low frequency is good */
4972 else if (frequency - lfrequency[ichain] < 1000) {
4973 /* so is the high frequency, interpolate */
4974 if (hfrequency[ichain] - frequency < 1000) {
4975
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4976 correction[ichain] = interpolate(frequency,
4977 lfrequency[ichain],
4978 hfrequency[ichain],
4979 lcorrection[ichain],
4980 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4981
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4982 temperature[ichain] = interpolate(frequency,
4983 lfrequency[ichain],
4984 hfrequency[ichain],
4985 ltemperature[ichain],
4986 htemperature[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4987
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4988 voltage[ichain] = interpolate(frequency,
4989 lfrequency[ichain],
4990 hfrequency[ichain],
4991 lvoltage[ichain],
4992 hvoltage[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4993 }
4994 /* only low is good, use it */
4995 else {
4996 correction[ichain] = lcorrection[ichain];
4997 temperature[ichain] = ltemperature[ichain];
4998 voltage[ichain] = lvoltage[ichain];
4999 }
5000 }
5001 /* only high is good, use it */
5002 else if (hfrequency[ichain] - frequency < 1000) {
5003 correction[ichain] = hcorrection[ichain];
5004 temperature[ichain] = htemperature[ichain];
5005 voltage[ichain] = hvoltage[ichain];
5006 } else { /* nothing is good, presume 0???? */
5007 correction[ichain] = 0;
5008 temperature[ichain] = 0;
5009 voltage[ichain] = 0;
5010 }
5011 }
5012
5013 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
5014 temperature);
5015
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]5016 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]5017 "for frequency=%d, calibration correction = %d %d %d\n",
5018 frequency, correction[0], correction[1], correction[2]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5019
5020 return 0;
5021}
5022
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5023static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
5024 int idx,
5025 int edge,
5026 bool is2GHz)
5027{
5028 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
5029 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
5030
5031 if (is2GHz)
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]5032 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5033 else
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]5034 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5035}
5036
5037static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
5038 int idx,
5039 unsigned int edge,
5040 u16 freq,
5041 bool is2GHz)
5042{
5043 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
5044 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
5045
5046 u8 *ctl_freqbin = is2GHz ?
5047 &eep->ctl_freqbin_2G[idx][0] :
5048 &eep->ctl_freqbin_5G[idx][0];
5049
5050 if (is2GHz) {
5051 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]5052 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
5053 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5054 } else {
5055 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]5056 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
5057 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5058 }
5059
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]5060 return MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5061}
5062
5063/*
5064 * Find the maximum conformance test limit for the given channel and CTL info
5065 */
5066static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
5067 u16 freq, int idx, bool is2GHz)
5068{
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]5069 u16 twiceMaxEdgePower = MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5070 u8 *ctl_freqbin = is2GHz ?
5071 &eep->ctl_freqbin_2G[idx][0] :
5072 &eep->ctl_freqbin_5G[idx][0];
5073 u16 num_edges = is2GHz ?
5074 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
5075 unsigned int edge;
5076
5077 /* Get the edge power */
5078 for (edge = 0;
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]5079 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5080 edge++) {
5081 /*
5082 * If there's an exact channel match or an inband flag set
5083 * on the lower channel use the given rdEdgePower
5084 */
5085 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
5086 twiceMaxEdgePower =
5087 ar9003_hw_get_direct_edge_power(eep, idx,
5088 edge, is2GHz);
5089 break;
5090 } else if ((edge > 0) &&
5091 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
5092 is2GHz))) {
5093 twiceMaxEdgePower =
5094 ar9003_hw_get_indirect_edge_power(eep, idx,
5095 edge, freq,
5096 is2GHz);
5097 /*
5098 * Leave loop - no more affecting edges possible in
5099 * this monotonic increasing list
5100 */
5101 break;
5102 }
5103 }
Sujith Manoharan4cfe9a82014-02-04 08:37:54 +0530[diff] [blame]5104
5105 if (is2GHz && !twiceMaxEdgePower)
5106 twiceMaxEdgePower = 60;
5107
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5108 return twiceMaxEdgePower;
5109}
5110
5111static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
5112 struct ath9k_channel *chan,
5113 u8 *pPwrArray, u16 cfgCtl,
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame]5114 u8 antenna_reduction,
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5115 u16 powerLimit)
5116{
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5117 struct ath_common *common = ath9k_hw_common(ah);
5118 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
Rajkumar Manoharana261f0e2011-11-22 18:52:00 +0530[diff] [blame]5119 u16 twiceMaxEdgePower;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5120 int i;
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame]5121 u16 scaledPower = 0, minCtlPower;
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]5122 static const u16 ctlModesFor11a[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5123 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
5124 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]5125 static const u16 ctlModesFor11g[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5126 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
5127 CTL_11G_EXT, CTL_2GHT40
5128 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]5129 u16 numCtlModes;
5130 const u16 *pCtlMode;
5131 u16 ctlMode, freq;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5132 struct chan_centers centers;
5133 u8 *ctlIndex;
5134 u8 ctlNum;
5135 u16 twiceMinEdgePower;
5136 bool is2ghz = IS_CHAN_2GHZ(chan);
5137
5138 ath9k_hw_get_channel_centers(ah, chan, &centers);
Gabor Juhosea6f7922012-04-14 22:01:58 +0200[diff] [blame]5139 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
5140 antenna_reduction);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5141
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5142 if (is2ghz) {
5143 /* Setup for CTL modes */
5144 /* CTL_11B, CTL_11G, CTL_2GHT20 */
5145 numCtlModes =
5146 ARRAY_SIZE(ctlModesFor11g) -
5147 SUB_NUM_CTL_MODES_AT_2G_40;
5148 pCtlMode = ctlModesFor11g;
5149 if (IS_CHAN_HT40(chan))
5150 /* All 2G CTL's */
5151 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
5152 } else {
5153 /* Setup for CTL modes */
5154 /* CTL_11A, CTL_5GHT20 */
5155 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
5156 SUB_NUM_CTL_MODES_AT_5G_40;
5157 pCtlMode = ctlModesFor11a;
5158 if (IS_CHAN_HT40(chan))
5159 /* All 5G CTL's */
5160 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
5161 }
5162
5163 /*
5164 * For MIMO, need to apply regulatory caps individually across
5165 * dynamically running modes: CCK, OFDM, HT20, HT40
5166 *
5167 * The outer loop walks through each possible applicable runtime mode.
5168 * The inner loop walks through each ctlIndex entry in EEPROM.
5169 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
5170 */
5171 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
5172 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
5173 (pCtlMode[ctlMode] == CTL_2GHT40);
5174 if (isHt40CtlMode)
5175 freq = centers.synth_center;
5176 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
5177 freq = centers.ext_center;
5178 else
5179 freq = centers.ctl_center;
5180
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]5181 ath_dbg(common, REGULATORY,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]5182 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
5183 ctlMode, numCtlModes, isHt40CtlMode,
5184 (pCtlMode[ctlMode] & EXT_ADDITIVE));
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5185
5186 /* walk through each CTL index stored in EEPROM */
5187 if (is2ghz) {
5188 ctlIndex = pEepData->ctlIndex_2G;
5189 ctlNum = AR9300_NUM_CTLS_2G;
5190 } else {
5191 ctlIndex = pEepData->ctlIndex_5G;
5192 ctlNum = AR9300_NUM_CTLS_5G;
5193 }
5194
Rajkumar Manoharana261f0e2011-11-22 18:52:00 +0530[diff] [blame]5195 twiceMaxEdgePower = MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5196 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]5197 ath_dbg(common, REGULATORY,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]5198 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
5199 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
5200 chan->channel);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5201
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5202 /*
5203 * compare test group from regulatory
5204 * channel list with test mode from pCtlMode
5205 * list
5206 */
5207 if ((((cfgCtl & ~CTL_MODE_M) |
5208 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
5209 ctlIndex[i]) ||
5210 (((cfgCtl & ~CTL_MODE_M) |
5211 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
5212 ((ctlIndex[i] & CTL_MODE_M) |
5213 SD_NO_CTL))) {
5214 twiceMinEdgePower =
5215 ar9003_hw_get_max_edge_power(pEepData,
5216 freq, i,
5217 is2ghz);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5218
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5219 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
5220 /*
5221 * Find the minimum of all CTL
5222 * edge powers that apply to
5223 * this channel
5224 */
5225 twiceMaxEdgePower =
5226 min(twiceMaxEdgePower,
5227 twiceMinEdgePower);
5228 else {
5229 /* specific */
5230 twiceMaxEdgePower = twiceMinEdgePower;
5231 break;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5232 }
5233 }
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5234 }
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5235
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5236 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5237
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5238 ath_dbg(common, REGULATORY,
5239 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
5240 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
5241 scaledPower, minCtlPower);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5242
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5243 /* Apply ctl mode to correct target power set */
5244 switch (pCtlMode[ctlMode]) {
5245 case CTL_11B:
5246 for (i = ALL_TARGET_LEGACY_1L_5L;
5247 i <= ALL_TARGET_LEGACY_11S; i++)
5248 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5249 minCtlPower);
5250 break;
5251 case CTL_11A:
5252 case CTL_11G:
5253 for (i = ALL_TARGET_LEGACY_6_24;
5254 i <= ALL_TARGET_LEGACY_54; i++)
5255 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5256 minCtlPower);
5257 break;
5258 case CTL_5GHT20:
5259 case CTL_2GHT20:
5260 for (i = ALL_TARGET_HT20_0_8_16;
Rajkumar Manoharane82cb032012-10-12 14:07:25 +0530[diff] [blame]5261 i <= ALL_TARGET_HT20_23; i++) {
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5262 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5263 minCtlPower);
Rajkumar Manoharane82cb032012-10-12 14:07:25 +0530[diff] [blame]5264 if (ath9k_hw_mci_is_enabled(ah))
5265 pPwrArray[i] =
5266 (u8)min((u16)pPwrArray[i],
5267 ar9003_mci_get_max_txpower(ah,
5268 pCtlMode[ctlMode]));
5269 }
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5270 break;
5271 case CTL_5GHT40:
5272 case CTL_2GHT40:
5273 for (i = ALL_TARGET_HT40_0_8_16;
Rajkumar Manoharane82cb032012-10-12 14:07:25 +0530[diff] [blame]5274 i <= ALL_TARGET_HT40_23; i++) {
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5275 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5276 minCtlPower);
Rajkumar Manoharane82cb032012-10-12 14:07:25 +0530[diff] [blame]5277 if (ath9k_hw_mci_is_enabled(ah))
5278 pPwrArray[i] =
5279 (u8)min((u16)pPwrArray[i],
5280 ar9003_mci_get_max_txpower(ah,
5281 pCtlMode[ctlMode]));
5282 }
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5283 break;
5284 default:
5285 break;
5286 }
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5287 } /* end ctl mode checking */
5288}
5289
Vasanthakumar Thiagarajan45ef6a0b2010-12-15 07:30:53 -0800[diff] [blame]5290static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
5291{
5292 u8 mod_idx = mcs_idx % 8;
5293
5294 if (mod_idx <= 3)
5295 return mod_idx ? (base_pwridx + 1) : base_pwridx;
5296 else
5297 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
5298}
5299
Sujith Manoharan15625802012-12-10 07:22:38 +0530[diff] [blame]5300static void ar9003_paprd_set_txpower(struct ath_hw *ah,
5301 struct ath9k_channel *chan,
5302 u8 *targetPowerValT2)
5303{
5304 int i;
5305
5306 if (!ar9003_is_paprd_enabled(ah))
5307 return;
5308
5309 if (IS_CHAN_HT40(chan))
5310 i = ALL_TARGET_HT40_7;
5311 else
5312 i = ALL_TARGET_HT20_7;
5313
5314 if (IS_CHAN_2GHZ(chan)) {
5315 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) &&
5316 !AR_SREV_9462(ah) && !AR_SREV_9565(ah)) {
5317 if (IS_CHAN_HT40(chan))
5318 i = ALL_TARGET_HT40_0_8_16;
5319 else
5320 i = ALL_TARGET_HT20_0_8_16;
5321 }
5322 }
5323
5324 ah->paprd_target_power = targetPowerValT2[i];
5325}
5326
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5327static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
5328 struct ath9k_channel *chan, u16 cfgCtl,
5329 u8 twiceAntennaReduction,
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5330 u8 powerLimit, bool test)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5331{
Felix Fietkau6b7b6cf2010-10-20 02:09:44 +0200[diff] [blame]5332 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5333 struct ath_common *common = ath9k_hw_common(ah);
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5334 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]5335 struct ar9300_modal_eep_header *modal_hdr;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5336 u8 targetPowerValT2[ar9300RateSize];
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5337 u8 target_power_val_t2_eep[ar9300RateSize];
Lorenzo Bianconi23f53dd32014-11-25 00:21:40 +0100[diff] [blame]5338 u8 targetPowerValT2_tpc[ar9300RateSize];
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5339 unsigned int i = 0, paprd_scale_factor = 0;
Vasanthakumar Thiagarajan45ef6a0b2010-12-15 07:30:53 -0800[diff] [blame]5340 u8 pwr_idx, min_pwridx = 0;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5341
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]5342 memset(targetPowerValT2, 0 , sizeof(targetPowerValT2));
5343
5344 /*
5345 * Get target powers from EEPROM - our baseline for TX Power
5346 */
5347 ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5348
Sujith Manoharan0f21ee82012-12-10 07:22:37 +0530[diff] [blame]5349 if (ar9003_is_paprd_enabled(ah)) {
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5350 if (IS_CHAN_2GHZ(chan))
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]5351 modal_hdr = &eep->modalHeader2G;
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5352 else
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]5353 modal_hdr = &eep->modalHeader5G;
5354
5355 ah->paprd_ratemask =
5356 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
5357 AR9300_PAPRD_RATE_MASK;
5358
5359 ah->paprd_ratemask_ht40 =
5360 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
5361 AR9300_PAPRD_RATE_MASK;
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5362
Vasanthakumar Thiagarajan45ef6a0b2010-12-15 07:30:53 -0800[diff] [blame]5363 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5364 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5365 ALL_TARGET_HT20_0_8_16;
5366
5367 if (!ah->paprd_table_write_done) {
5368 memcpy(target_power_val_t2_eep, targetPowerValT2,
5369 sizeof(targetPowerValT2));
5370 for (i = 0; i < 24; i++) {
5371 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5372 if (ah->paprd_ratemask & (1 << i)) {
5373 if (targetPowerValT2[pwr_idx] &&
5374 targetPowerValT2[pwr_idx] ==
5375 target_power_val_t2_eep[pwr_idx])
5376 targetPowerValT2[pwr_idx] -=
5377 paprd_scale_factor;
5378 }
5379 }
5380 }
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5381 memcpy(target_power_val_t2_eep, targetPowerValT2,
5382 sizeof(targetPowerValT2));
5383 }
5384
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5385 ar9003_hw_set_power_per_rate_table(ah, chan,
5386 targetPowerValT2, cfgCtl,
5387 twiceAntennaReduction,
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5388 powerLimit);
5389
Lorenzo Bianconi23f53dd32014-11-25 00:21:40 +0100[diff] [blame]5390 memcpy(targetPowerValT2_tpc, targetPowerValT2,
5391 sizeof(targetPowerValT2));
5392
Sujith Manoharan0f21ee82012-12-10 07:22:37 +0530[diff] [blame]5393 if (ar9003_is_paprd_enabled(ah)) {
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5394 for (i = 0; i < ar9300RateSize; i++) {
5395 if ((ah->paprd_ratemask & (1 << i)) &&
5396 (abs(targetPowerValT2[i] -
5397 target_power_val_t2_eep[i]) >
5398 paprd_scale_factor)) {
5399 ah->paprd_ratemask &= ~(1 << i);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]5400 ath_dbg(common, EEPROM,
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5401 "paprd disabled for mcs %d\n", i);
5402 }
5403 }
5404 }
5405
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5406 regulatory->max_power_level = 0;
5407 for (i = 0; i < ar9300RateSize; i++) {
5408 if (targetPowerValT2[i] > regulatory->max_power_level)
5409 regulatory->max_power_level = targetPowerValT2[i];
5410 }
5411
Rajkumar Manoharan8915f982011-11-10 15:14:57 +0530[diff] [blame]5412 ath9k_hw_update_regulatory_maxpower(ah);
5413
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5414 if (test)
5415 return;
5416
5417 for (i = 0; i < ar9300RateSize; i++) {
Sujith Manoharandf401902013-06-18 10:13:40 +0530[diff] [blame]5418 ath_dbg(common, REGULATORY, "TPC[%02d] 0x%08x\n",
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]5419 i, targetPowerValT2[i]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5420 }
5421
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5422 /* Write target power array to registers */
5423 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5424 ar9003_hw_calibration_apply(ah, chan->channel);
Sujith Manoharan15625802012-12-10 07:22:38 +0530[diff] [blame]5425 ar9003_paprd_set_txpower(ah, chan, targetPowerValT2);
Lorenzo Bianconi23f53dd32014-11-25 00:21:40 +0100[diff] [blame]5426
5427 ar9003_hw_selfgen_tpc_txpower(ah, chan, targetPowerValT2);
5428
5429 /* TPC initializations */
5430 if (ah->tpc_enabled) {
5431 u32 val;
5432
5433 ar9003_hw_init_rate_txpower(ah, targetPowerValT2_tpc, chan);
5434
5435 /* Enable TPC */
5436 REG_WRITE(ah, AR_PHY_PWRTX_MAX,
5437 AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE);
5438 /* Disable per chain power reduction */
5439 val = REG_READ(ah, AR_PHY_POWER_TX_SUB);
5440 if (AR_SREV_9340(ah))
5441 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
5442 val & 0xFFFFFFC0);
5443 else
5444 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
5445 val & 0xFFFFF000);
5446 } else {
5447 /* Disable TPC */
5448 REG_WRITE(ah, AR_PHY_PWRTX_MAX, 0);
5449 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5450}
5451
5452static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5453 u16 i, bool is2GHz)
5454{
5455 return AR_NO_SPUR;
5456}
5457
Luis R. Rodriguezc14a85d2010-04-15 17:39:21 -0400[diff] [blame]5458s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5459{
5460 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5461
5462 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5463}
5464
5465s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5466{
5467 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5468
5469 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5470}
5471
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]5472u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
Vasanthakumar Thiagarajan272ceba2010-12-06 04:27:46 -0800[diff] [blame]5473{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]5474 return ar9003_modal_header(ah, is2ghz)->spurChans;
Vasanthakumar Thiagarajan272ceba2010-12-06 04:27:46 -0800[diff] [blame]5475}
5476
Vasanthakumar Thiagarajan8698bca2010-12-15 07:30:51 -0800[diff] [blame]5477unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5478 struct ath9k_channel *chan)
5479{
5480 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5481
5482 if (IS_CHAN_2GHZ(chan))
5483 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5484 AR9300_PAPRD_SCALE_1);
5485 else {
5486 if (chan->channel >= 5700)
Miaoqing Pan1542bc32016-01-18 09:33:49 +0800[diff] [blame]5487 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5488 AR9300_PAPRD_SCALE_1);
Vasanthakumar Thiagarajan8698bca2010-12-15 07:30:51 -0800[diff] [blame]5489 else if (chan->channel >= 5400)
5490 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
Miaoqing Pan1542bc32016-01-18 09:33:49 +0800[diff] [blame]5491 AR9300_PAPRD_SCALE_2);
Vasanthakumar Thiagarajan8698bca2010-12-15 07:30:51 -0800[diff] [blame]5492 else
5493 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5494 AR9300_PAPRD_SCALE_1);
5495 }
5496}
5497
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5498const struct eeprom_ops eep_ar9300_ops = {
5499 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5500 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5501 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]5502 .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5503 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5504 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5505 .set_board_values = ath9k_hw_ar9300_set_board_values,
5506 .set_addac = ath9k_hw_ar9300_set_addac,
5507 .set_txpower = ath9k_hw_ar9300_set_txpower,
5508 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5509};