Jakub Kicinski | c869f77 | 2015-05-26 11:16:00 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (c) Copyright 2002-2010, Ralink Technology, Inc. |
| 3 | * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> |
| 4 | * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 |
| 8 | * as published by the Free Software Foundation |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include "mt7601u.h" |
| 17 | #include "mcu.h" |
| 18 | #include "eeprom.h" |
| 19 | #include "trace.h" |
| 20 | #include "initvals_phy.h" |
| 21 | |
| 22 | #include <linux/etherdevice.h> |
| 23 | |
| 24 | static void mt7601u_agc_reset(struct mt7601u_dev *dev); |
| 25 | |
| 26 | static int |
| 27 | mt7601u_rf_wr(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 value) |
| 28 | { |
| 29 | int ret = 0; |
| 30 | |
| 31 | if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || |
| 32 | WARN_ON(offset > 63)) |
| 33 | return -EINVAL; |
| 34 | if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) |
| 35 | return 0; |
| 36 | |
| 37 | mutex_lock(&dev->reg_atomic_mutex); |
| 38 | |
| 39 | if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) { |
| 40 | ret = -ETIMEDOUT; |
| 41 | goto out; |
| 42 | } |
| 43 | |
| 44 | mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_DATA, value) | |
| 45 | MT76_SET(MT_RF_CSR_CFG_REG_BANK, bank) | |
| 46 | MT76_SET(MT_RF_CSR_CFG_REG_ID, offset) | |
| 47 | MT_RF_CSR_CFG_WR | |
| 48 | MT_RF_CSR_CFG_KICK); |
| 49 | trace_rf_write(dev, bank, offset, value); |
| 50 | out: |
| 51 | mutex_unlock(&dev->reg_atomic_mutex); |
| 52 | |
| 53 | if (ret < 0) |
| 54 | dev_err(dev->dev, "Error: RF write %02hhx:%02hhx failed:%d!!\n", |
| 55 | bank, offset, ret); |
| 56 | |
| 57 | return ret; |
| 58 | } |
| 59 | |
| 60 | static int |
| 61 | mt7601u_rf_rr(struct mt7601u_dev *dev, u8 bank, u8 offset) |
| 62 | { |
| 63 | int ret = -ETIMEDOUT; |
| 64 | u32 val; |
| 65 | |
| 66 | if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || |
| 67 | WARN_ON(offset > 63)) |
| 68 | return -EINVAL; |
| 69 | if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) |
| 70 | return 0xff; |
| 71 | |
| 72 | mutex_lock(&dev->reg_atomic_mutex); |
| 73 | |
| 74 | if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) |
| 75 | goto out; |
| 76 | |
| 77 | mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_REG_BANK, bank) | |
| 78 | MT76_SET(MT_RF_CSR_CFG_REG_ID, offset) | |
| 79 | MT_RF_CSR_CFG_KICK); |
| 80 | |
| 81 | if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) |
| 82 | goto out; |
| 83 | |
| 84 | val = mt7601u_rr(dev, MT_RF_CSR_CFG); |
| 85 | if (MT76_GET(MT_RF_CSR_CFG_REG_ID, val) == offset && |
| 86 | MT76_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) { |
| 87 | ret = MT76_GET(MT_RF_CSR_CFG_DATA, val); |
| 88 | trace_rf_read(dev, bank, offset, ret); |
| 89 | } |
| 90 | out: |
| 91 | mutex_unlock(&dev->reg_atomic_mutex); |
| 92 | |
| 93 | if (ret < 0) |
| 94 | dev_err(dev->dev, "Error: RF read %02hhx:%02hhx failed:%d!!\n", |
| 95 | bank, offset, ret); |
| 96 | |
| 97 | return ret; |
| 98 | } |
| 99 | |
| 100 | static int |
| 101 | mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val) |
| 102 | { |
| 103 | int ret; |
| 104 | |
| 105 | ret = mt7601u_rf_rr(dev, bank, offset); |
| 106 | if (ret < 0) |
| 107 | return ret; |
| 108 | val |= ret & ~mask; |
| 109 | ret = mt7601u_rf_wr(dev, bank, offset, val); |
| 110 | if (ret) |
| 111 | return ret; |
| 112 | |
| 113 | return val; |
| 114 | } |
| 115 | |
| 116 | static int |
| 117 | mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val) |
| 118 | { |
| 119 | return mt7601u_rf_rmw(dev, bank, offset, 0, val); |
| 120 | } |
| 121 | |
| 122 | static int |
| 123 | mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask) |
| 124 | { |
| 125 | return mt7601u_rf_rmw(dev, bank, offset, mask, 0); |
| 126 | } |
| 127 | |
| 128 | static void mt7601u_bbp_wr(struct mt7601u_dev *dev, u8 offset, u8 val) |
| 129 | { |
| 130 | if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || |
| 131 | test_bit(MT7601U_STATE_REMOVED, &dev->state)) |
| 132 | return; |
| 133 | |
| 134 | mutex_lock(&dev->reg_atomic_mutex); |
| 135 | |
| 136 | if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) { |
| 137 | dev_err(dev->dev, "Error: BBP write %02hhx failed!!\n", offset); |
| 138 | goto out; |
| 139 | } |
| 140 | |
| 141 | mt7601u_wr(dev, MT_BBP_CSR_CFG, |
| 142 | MT76_SET(MT_BBP_CSR_CFG_VAL, val) | |
| 143 | MT76_SET(MT_BBP_CSR_CFG_REG_NUM, offset) | |
| 144 | MT_BBP_CSR_CFG_RW_MODE | MT_BBP_CSR_CFG_BUSY); |
| 145 | trace_bbp_write(dev, offset, val); |
| 146 | out: |
| 147 | mutex_unlock(&dev->reg_atomic_mutex); |
| 148 | } |
| 149 | |
| 150 | static int mt7601u_bbp_rr(struct mt7601u_dev *dev, u8 offset) |
| 151 | { |
| 152 | u32 val; |
| 153 | int ret = -ETIMEDOUT; |
| 154 | |
| 155 | if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state))) |
| 156 | return -EINVAL; |
| 157 | if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) |
| 158 | return 0xff; |
| 159 | |
| 160 | mutex_lock(&dev->reg_atomic_mutex); |
| 161 | |
| 162 | if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) |
| 163 | goto out; |
| 164 | |
| 165 | mt7601u_wr(dev, MT_BBP_CSR_CFG, |
| 166 | MT76_SET(MT_BBP_CSR_CFG_REG_NUM, offset) | |
| 167 | MT_BBP_CSR_CFG_RW_MODE | MT_BBP_CSR_CFG_BUSY | |
| 168 | MT_BBP_CSR_CFG_READ); |
| 169 | |
| 170 | if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) |
| 171 | goto out; |
| 172 | |
| 173 | val = mt7601u_rr(dev, MT_BBP_CSR_CFG); |
| 174 | if (MT76_GET(MT_BBP_CSR_CFG_REG_NUM, val) == offset) { |
| 175 | ret = MT76_GET(MT_BBP_CSR_CFG_VAL, val); |
| 176 | trace_bbp_read(dev, offset, ret); |
| 177 | } |
| 178 | out: |
| 179 | mutex_unlock(&dev->reg_atomic_mutex); |
| 180 | |
| 181 | if (ret < 0) |
| 182 | dev_err(dev->dev, "Error: BBP read %02hhx failed:%d!!\n", |
| 183 | offset, ret); |
| 184 | |
| 185 | return ret; |
| 186 | } |
| 187 | |
| 188 | static int mt7601u_bbp_rmw(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) |
| 189 | { |
| 190 | int ret; |
| 191 | |
| 192 | ret = mt7601u_bbp_rr(dev, offset); |
| 193 | if (ret < 0) |
| 194 | return ret; |
| 195 | val |= ret & ~mask; |
| 196 | mt7601u_bbp_wr(dev, offset, val); |
| 197 | |
| 198 | return val; |
| 199 | } |
| 200 | |
| 201 | static u8 mt7601u_bbp_rmc(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) |
| 202 | { |
| 203 | int ret; |
| 204 | |
| 205 | ret = mt7601u_bbp_rr(dev, offset); |
| 206 | if (ret < 0) |
| 207 | return ret; |
| 208 | val |= ret & ~mask; |
| 209 | if (ret != val) |
| 210 | mt7601u_bbp_wr(dev, offset, val); |
| 211 | |
| 212 | return val; |
| 213 | } |
| 214 | |
| 215 | int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev) |
| 216 | { |
| 217 | int i = 20; |
| 218 | u8 val; |
| 219 | |
| 220 | do { |
| 221 | val = mt7601u_bbp_rr(dev, MT_BBP_REG_VERSION); |
| 222 | if (val && ~val) |
| 223 | break; |
| 224 | } while (--i); |
| 225 | |
| 226 | if (!i) { |
| 227 | dev_err(dev->dev, "Error: BBP is not ready\n"); |
| 228 | return -EIO; |
| 229 | } |
| 230 | |
| 231 | return 0; |
| 232 | } |
| 233 | |
| 234 | u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below) |
| 235 | { |
| 236 | return mt7601u_bbp_rmc(dev, 3, 0x20, below ? 0x20 : 0); |
| 237 | } |
| 238 | |
| 239 | int mt7601u_phy_get_rssi(struct mt7601u_dev *dev, |
| 240 | struct mt7601u_rxwi *rxwi, u16 rate) |
| 241 | { |
| 242 | static const s8 lna[2][2][3] = { |
| 243 | /* main LNA */ { |
| 244 | /* bw20 */ { -2, 15, 33 }, |
| 245 | /* bw40 */ { 0, 16, 34 } |
| 246 | }, |
| 247 | /* aux LNA */ { |
| 248 | /* bw20 */ { -2, 15, 33 }, |
| 249 | /* bw40 */ { -2, 16, 34 } |
| 250 | } |
| 251 | }; |
| 252 | int bw = MT76_GET(MT_RXWI_RATE_BW, rate); |
| 253 | int aux_lna = MT76_GET(MT_RXWI_ANT_AUX_LNA, rxwi->ant); |
| 254 | int lna_id = MT76_GET(MT_RXWI_GAIN_RSSI_LNA_ID, rxwi->gain); |
| 255 | int val; |
| 256 | |
| 257 | if (lna_id) /* LNA id can be 0, 2, 3. */ |
| 258 | lna_id--; |
| 259 | |
| 260 | val = 8; |
| 261 | val -= lna[aux_lna][bw][lna_id]; |
| 262 | val -= MT76_GET(MT_RXWI_GAIN_RSSI_VAL, rxwi->gain); |
| 263 | val -= dev->ee->lna_gain; |
| 264 | val -= dev->ee->rssi_offset[0]; |
| 265 | |
| 266 | return val; |
| 267 | } |
| 268 | |
| 269 | static void mt7601u_vco_cal(struct mt7601u_dev *dev) |
| 270 | { |
| 271 | mt7601u_rf_wr(dev, 0, 4, 0x0a); |
| 272 | mt7601u_rf_wr(dev, 0, 5, 0x20); |
| 273 | mt7601u_rf_set(dev, 0, 4, BIT(7)); |
| 274 | msleep(2); |
| 275 | } |
| 276 | |
| 277 | static int mt7601u_set_bw_filter(struct mt7601u_dev *dev, bool cal) |
| 278 | { |
| 279 | u32 filter = 0; |
| 280 | int ret; |
| 281 | |
| 282 | if (!cal) |
| 283 | filter |= 0x10000; |
| 284 | if (dev->bw != MT_BW_20) |
| 285 | filter |= 0x00100; |
| 286 | |
| 287 | /* TX */ |
| 288 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter | 1); |
| 289 | if (ret) |
| 290 | return ret; |
| 291 | /* RX */ |
| 292 | return mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter); |
| 293 | } |
| 294 | |
| 295 | static int mt7601u_load_bbp_temp_table_bw(struct mt7601u_dev *dev) |
| 296 | { |
| 297 | const struct reg_table *t; |
| 298 | |
| 299 | if (WARN_ON(dev->temp_mode > MT_TEMP_MODE_LOW)) |
| 300 | return -EINVAL; |
| 301 | |
| 302 | t = &bbp_mode_table[dev->temp_mode][dev->bw]; |
| 303 | |
| 304 | return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, t->regs, t->n); |
| 305 | } |
| 306 | |
| 307 | static int mt7601u_bbp_temp(struct mt7601u_dev *dev, int mode, const char *name) |
| 308 | { |
| 309 | const struct reg_table *t; |
| 310 | int ret; |
| 311 | |
| 312 | if (dev->temp_mode == mode) |
| 313 | return 0; |
| 314 | |
| 315 | dev->temp_mode = mode; |
| 316 | trace_temp_mode(dev, mode); |
| 317 | |
| 318 | t = bbp_mode_table[dev->temp_mode]; |
| 319 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, |
| 320 | t[2].regs, t[2].n); |
| 321 | if (ret) |
| 322 | return ret; |
| 323 | |
| 324 | return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, |
| 325 | t[dev->bw].regs, t[dev->bw].n); |
| 326 | } |
| 327 | |
| 328 | static void mt7601u_apply_ch14_fixup(struct mt7601u_dev *dev, int hw_chan) |
| 329 | { |
| 330 | struct mt7601u_rate_power *t = &dev->ee->power_rate_table; |
| 331 | |
| 332 | if (hw_chan != 14 || dev->bw != MT_BW_20) { |
| 333 | mt7601u_bbp_rmw(dev, 4, 0x20, 0); |
| 334 | mt7601u_bbp_wr(dev, 178, 0xff); |
| 335 | |
| 336 | t->cck[0].bw20 = dev->ee->real_cck_bw20[0]; |
| 337 | t->cck[1].bw20 = dev->ee->real_cck_bw20[1]; |
| 338 | } else { /* Apply CH14 OBW fixup */ |
| 339 | mt7601u_bbp_wr(dev, 4, 0x60); |
| 340 | mt7601u_bbp_wr(dev, 178, 0); |
| 341 | |
| 342 | /* Note: vendor code is buggy here for negative values */ |
| 343 | t->cck[0].bw20 = dev->ee->real_cck_bw20[0] - 2; |
| 344 | t->cck[1].bw20 = dev->ee->real_cck_bw20[1] - 2; |
| 345 | } |
| 346 | } |
| 347 | |
| 348 | static int __mt7601u_phy_set_channel(struct mt7601u_dev *dev, |
| 349 | struct cfg80211_chan_def *chandef) |
| 350 | { |
| 351 | #define FREQ_PLAN_REGS 4 |
| 352 | static const u8 freq_plan[14][FREQ_PLAN_REGS] = { |
| 353 | { 0x99, 0x99, 0x09, 0x50 }, |
| 354 | { 0x46, 0x44, 0x0a, 0x50 }, |
| 355 | { 0xec, 0xee, 0x0a, 0x50 }, |
| 356 | { 0x99, 0x99, 0x0b, 0x50 }, |
| 357 | { 0x46, 0x44, 0x08, 0x51 }, |
| 358 | { 0xec, 0xee, 0x08, 0x51 }, |
| 359 | { 0x99, 0x99, 0x09, 0x51 }, |
| 360 | { 0x46, 0x44, 0x0a, 0x51 }, |
| 361 | { 0xec, 0xee, 0x0a, 0x51 }, |
| 362 | { 0x99, 0x99, 0x0b, 0x51 }, |
| 363 | { 0x46, 0x44, 0x08, 0x52 }, |
| 364 | { 0xec, 0xee, 0x08, 0x52 }, |
| 365 | { 0x99, 0x99, 0x09, 0x52 }, |
| 366 | { 0x33, 0x33, 0x0b, 0x52 }, |
| 367 | }; |
| 368 | struct mt76_reg_pair channel_freq_plan[FREQ_PLAN_REGS] = { |
| 369 | { 17, 0 }, { 18, 0 }, { 19, 0 }, { 20, 0 }, |
| 370 | }; |
| 371 | struct mt76_reg_pair bbp_settings[3] = { |
| 372 | { 62, 0x37 - dev->ee->lna_gain }, |
| 373 | { 63, 0x37 - dev->ee->lna_gain }, |
| 374 | { 64, 0x37 - dev->ee->lna_gain }, |
| 375 | }; |
| 376 | |
| 377 | struct ieee80211_channel *chan = chandef->chan; |
| 378 | enum nl80211_channel_type chan_type = |
| 379 | cfg80211_get_chandef_type(chandef); |
| 380 | struct mt7601u_rate_power *t = &dev->ee->power_rate_table; |
| 381 | int chan_idx; |
| 382 | bool chan_ext_below; |
| 383 | u8 bw; |
| 384 | int i, ret; |
| 385 | |
| 386 | bw = MT_BW_20; |
| 387 | chan_ext_below = (chan_type == NL80211_CHAN_HT40MINUS); |
| 388 | chan_idx = chan->hw_value - 1; |
| 389 | |
| 390 | if (chandef->width == NL80211_CHAN_WIDTH_40) { |
| 391 | bw = MT_BW_40; |
| 392 | |
| 393 | if (chan_idx > 1 && chan_type == NL80211_CHAN_HT40MINUS) |
| 394 | chan_idx -= 2; |
| 395 | else if (chan_idx < 12 && chan_type == NL80211_CHAN_HT40PLUS) |
| 396 | chan_idx += 2; |
| 397 | else |
| 398 | dev_err(dev->dev, "Error: invalid 40MHz channel!!\n"); |
| 399 | } |
| 400 | |
| 401 | if (bw != dev->bw || chan_ext_below != dev->chan_ext_below) { |
| 402 | dev_dbg(dev->dev, "Info: switching HT mode bw:%d below:%d\n", |
| 403 | bw, chan_ext_below); |
| 404 | |
| 405 | mt7601u_bbp_set_bw(dev, bw); |
| 406 | |
| 407 | mt7601u_bbp_set_ctrlch(dev, chan_ext_below); |
| 408 | mt7601u_mac_set_ctrlch(dev, chan_ext_below); |
| 409 | dev->chan_ext_below = chan_ext_below; |
| 410 | } |
| 411 | |
| 412 | for (i = 0; i < FREQ_PLAN_REGS; i++) |
| 413 | channel_freq_plan[i].value = freq_plan[chan_idx][i]; |
| 414 | |
| 415 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_RF, |
| 416 | channel_freq_plan, FREQ_PLAN_REGS); |
| 417 | if (ret) |
| 418 | return ret; |
| 419 | |
| 420 | mt7601u_rmw(dev, MT_TX_ALC_CFG_0, 0x3f3f, |
| 421 | dev->ee->chan_pwr[chan_idx] & 0x3f); |
| 422 | |
| 423 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, |
| 424 | bbp_settings, ARRAY_SIZE(bbp_settings)); |
| 425 | if (ret) |
| 426 | return ret; |
| 427 | |
| 428 | mt7601u_vco_cal(dev); |
| 429 | mt7601u_bbp_set_bw(dev, bw); |
| 430 | ret = mt7601u_set_bw_filter(dev, false); |
| 431 | if (ret) |
| 432 | return ret; |
| 433 | |
| 434 | mt7601u_apply_ch14_fixup(dev, chan->hw_value); |
| 435 | mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 | |
| 436 | int_to_s6(t->ofdm[0].bw20) << 16 | |
| 437 | int_to_s6(t->cck[1].bw20) << 8 | |
| 438 | int_to_s6(t->cck[0].bw20)); |
| 439 | |
| 440 | if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) |
| 441 | mt7601u_agc_reset(dev); |
| 442 | |
| 443 | dev->chandef = *chandef; |
| 444 | |
| 445 | return 0; |
| 446 | } |
| 447 | |
| 448 | int mt7601u_phy_set_channel(struct mt7601u_dev *dev, |
| 449 | struct cfg80211_chan_def *chandef) |
| 450 | { |
| 451 | int ret; |
| 452 | |
| 453 | cancel_delayed_work_sync(&dev->cal_work); |
| 454 | cancel_delayed_work_sync(&dev->freq_cal.work); |
| 455 | |
| 456 | mutex_lock(&dev->hw_atomic_mutex); |
| 457 | ret = __mt7601u_phy_set_channel(dev, chandef); |
| 458 | mutex_unlock(&dev->hw_atomic_mutex); |
| 459 | if (ret) |
| 460 | return ret; |
| 461 | |
| 462 | if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) |
| 463 | return 0; |
| 464 | |
| 465 | ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, |
| 466 | MT_CALIBRATE_INTERVAL); |
| 467 | if (dev->freq_cal.enabled) |
| 468 | ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, |
| 469 | MT_FREQ_CAL_INIT_DELAY); |
| 470 | return 0; |
| 471 | } |
| 472 | |
| 473 | #define BBP_R47_FLAG GENMASK(2, 0) |
| 474 | #define BBP_R47_F_TSSI 0 |
| 475 | #define BBP_R47_F_PKT_T 1 |
| 476 | #define BBP_R47_F_TX_RATE 2 |
| 477 | #define BBP_R47_F_TEMP 4 |
| 478 | /** |
| 479 | * mt7601u_bbp_r47_get - read value through BBP R47/R49 pair |
| 480 | * @dev: pointer to adapter structure |
| 481 | * @reg: value of BBP R47 before the operation |
| 482 | * @flag: one of the BBP_R47_F_* flags |
| 483 | * |
| 484 | * Convenience helper for reading values through BBP R47/R49 pair. |
| 485 | * Takes old value of BBP R47 as @reg, because callers usually have it |
| 486 | * cached already. |
| 487 | * |
| 488 | * Return: value of BBP R49. |
| 489 | */ |
| 490 | static u8 mt7601u_bbp_r47_get(struct mt7601u_dev *dev, u8 reg, u8 flag) |
| 491 | { |
| 492 | flag |= reg & ~BBP_R47_FLAG; |
| 493 | mt7601u_bbp_wr(dev, 47, flag); |
| 494 | usleep_range(500, 700); |
| 495 | return mt7601u_bbp_rr(dev, 49); |
| 496 | } |
| 497 | |
| 498 | static s8 mt7601u_read_bootup_temp(struct mt7601u_dev *dev) |
| 499 | { |
| 500 | u8 bbp_val, temp; |
| 501 | u32 rf_bp, rf_set; |
| 502 | int i; |
| 503 | |
| 504 | rf_set = mt7601u_rr(dev, MT_RF_SETTING_0); |
| 505 | rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0); |
| 506 | |
| 507 | mt7601u_wr(dev, MT_RF_BYPASS_0, 0); |
| 508 | mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010); |
| 509 | mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010); |
| 510 | |
| 511 | bbp_val = mt7601u_bbp_rmw(dev, 47, 0, 0x10); |
| 512 | |
| 513 | mt7601u_bbp_wr(dev, 22, 0x40); |
| 514 | |
| 515 | for (i = 100; i && (bbp_val & 0x10); i--) |
| 516 | bbp_val = mt7601u_bbp_rr(dev, 47); |
| 517 | |
| 518 | temp = mt7601u_bbp_r47_get(dev, bbp_val, BBP_R47_F_TEMP); |
| 519 | |
| 520 | mt7601u_bbp_wr(dev, 22, 0); |
| 521 | |
| 522 | bbp_val = mt7601u_bbp_rr(dev, 21); |
| 523 | bbp_val |= 0x02; |
| 524 | mt7601u_bbp_wr(dev, 21, bbp_val); |
| 525 | bbp_val &= ~0x02; |
| 526 | mt7601u_bbp_wr(dev, 21, bbp_val); |
| 527 | |
| 528 | mt7601u_wr(dev, MT_RF_BYPASS_0, 0); |
| 529 | mt7601u_wr(dev, MT_RF_SETTING_0, rf_set); |
| 530 | mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp); |
| 531 | |
| 532 | trace_read_temp(dev, temp); |
| 533 | return temp; |
| 534 | } |
| 535 | |
| 536 | static s8 mt7601u_read_temp(struct mt7601u_dev *dev) |
| 537 | { |
| 538 | int i; |
| 539 | u8 val; |
| 540 | s8 temp; |
| 541 | |
| 542 | val = mt7601u_bbp_rmw(dev, 47, 0x7f, 0x10); |
| 543 | |
| 544 | /* Note: this rarely succeeds, temp can change even if it fails. */ |
| 545 | for (i = 100; i && (val & 0x10); i--) |
| 546 | val = mt7601u_bbp_rr(dev, 47); |
| 547 | |
| 548 | temp = mt7601u_bbp_r47_get(dev, val, BBP_R47_F_TEMP); |
| 549 | |
| 550 | trace_read_temp(dev, temp); |
| 551 | return temp; |
| 552 | } |
| 553 | |
| 554 | static void mt7601u_rxdc_cal(struct mt7601u_dev *dev) |
| 555 | { |
| 556 | static const struct mt76_reg_pair intro[] = { |
| 557 | { 158, 0x8d }, { 159, 0xfc }, |
| 558 | { 158, 0x8c }, { 159, 0x4c }, |
| 559 | }, outro[] = { |
| 560 | { 158, 0x8d }, { 159, 0xe0 }, |
| 561 | }; |
| 562 | u32 mac_ctrl; |
| 563 | int i, ret; |
| 564 | |
| 565 | mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); |
| 566 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX); |
| 567 | |
| 568 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, |
| 569 | intro, ARRAY_SIZE(intro)); |
| 570 | if (ret) |
| 571 | dev_err(dev->dev, "%s intro failed:%d\n", __func__, ret); |
| 572 | |
| 573 | for (i = 20; i; i--) { |
| 574 | usleep_range(300, 500); |
| 575 | |
| 576 | mt7601u_bbp_wr(dev, 158, 0x8c); |
| 577 | if (mt7601u_bbp_rr(dev, 159) == 0x0c) |
| 578 | break; |
| 579 | } |
| 580 | if (!i) |
| 581 | dev_err(dev->dev, "%s timed out\n", __func__); |
| 582 | |
| 583 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); |
| 584 | |
| 585 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, |
| 586 | outro, ARRAY_SIZE(outro)); |
| 587 | if (ret) |
| 588 | dev_err(dev->dev, "%s outro failed:%d\n", __func__, ret); |
| 589 | |
| 590 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl); |
| 591 | } |
| 592 | |
| 593 | void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev) |
| 594 | { |
| 595 | mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->curr_temp); |
| 596 | |
| 597 | mt7601u_rxdc_cal(dev); |
| 598 | } |
| 599 | |
| 600 | /* Note: function copied from vendor driver */ |
| 601 | static s16 lin2dBd(u16 linear) |
| 602 | { |
| 603 | short exp = 0; |
| 604 | unsigned int mantisa; |
| 605 | int app, dBd; |
| 606 | |
| 607 | if (WARN_ON(!linear)) |
| 608 | return -10000; |
| 609 | |
| 610 | mantisa = linear; |
| 611 | |
| 612 | exp = fls(mantisa) - 16; |
| 613 | if (exp > 0) |
| 614 | mantisa >>= exp; |
| 615 | else |
| 616 | mantisa <<= abs(exp); |
| 617 | |
| 618 | if (mantisa <= 0xb800) |
| 619 | app = (mantisa + (mantisa >> 3) + (mantisa >> 4) - 0x9600); |
| 620 | else |
| 621 | app = (mantisa - (mantisa >> 3) - (mantisa >> 6) - 0x5a00); |
| 622 | if (app < 0) |
| 623 | app = 0; |
| 624 | |
| 625 | dBd = ((15 + exp) << 15) + app; |
| 626 | dBd = (dBd << 2) + (dBd << 1) + (dBd >> 6) + (dBd >> 7); |
| 627 | dBd = (dBd >> 10); |
| 628 | |
| 629 | return dBd; |
| 630 | } |
| 631 | |
| 632 | static void |
| 633 | mt7601u_set_initial_tssi(struct mt7601u_dev *dev, s16 tssi_db, s16 tssi_hvga_db) |
| 634 | { |
| 635 | struct tssi_data *d = &dev->ee->tssi_data; |
| 636 | int init_offset; |
| 637 | |
| 638 | init_offset = -((tssi_db * d->slope + d->offset[1]) / 4096) + 10; |
| 639 | |
| 640 | mt76_rmw(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, |
| 641 | int_to_s6(init_offset) & MT_TX_ALC_CFG_1_TEMP_COMP); |
| 642 | } |
| 643 | |
| 644 | static void mt7601u_tssi_dc_gain_cal(struct mt7601u_dev *dev) |
| 645 | { |
| 646 | u8 rf_vga, rf_mixer, bbp_r47; |
| 647 | int i, j; |
| 648 | s8 res[4]; |
| 649 | s16 tssi_init_db, tssi_init_hvga_db; |
| 650 | |
| 651 | mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030); |
| 652 | mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030); |
| 653 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); |
| 654 | |
| 655 | mt7601u_bbp_wr(dev, 58, 0); |
| 656 | mt7601u_bbp_wr(dev, 241, 0x2); |
| 657 | mt7601u_bbp_wr(dev, 23, 0x8); |
| 658 | bbp_r47 = mt7601u_bbp_rr(dev, 47); |
| 659 | |
| 660 | /* Set VGA gain */ |
| 661 | rf_vga = mt7601u_rf_rr(dev, 5, 3); |
| 662 | mt7601u_rf_wr(dev, 5, 3, 8); |
| 663 | |
| 664 | /* Mixer disable */ |
| 665 | rf_mixer = mt7601u_rf_rr(dev, 4, 39); |
| 666 | mt7601u_rf_wr(dev, 4, 39, 0); |
| 667 | |
| 668 | for (i = 0; i < 4; i++) { |
| 669 | mt7601u_rf_wr(dev, 4, 39, (i & 1) ? rf_mixer : 0); |
| 670 | |
| 671 | mt7601u_bbp_wr(dev, 23, (i < 2) ? 0x08 : 0x02); |
| 672 | mt7601u_rf_wr(dev, 5, 3, (i < 2) ? 0x08 : 0x11); |
| 673 | |
| 674 | /* BBP TSSI initial and soft reset */ |
| 675 | mt7601u_bbp_wr(dev, 22, 0); |
| 676 | mt7601u_bbp_wr(dev, 244, 0); |
| 677 | |
| 678 | mt7601u_bbp_wr(dev, 21, 1); |
| 679 | udelay(1); |
| 680 | mt7601u_bbp_wr(dev, 21, 0); |
| 681 | |
| 682 | /* TSSI measurement */ |
| 683 | mt7601u_bbp_wr(dev, 47, 0x50); |
| 684 | mt7601u_bbp_wr(dev, (i & 1) ? 244 : 22, (i & 1) ? 0x31 : 0x40); |
| 685 | |
| 686 | for (j = 20; j; j--) |
| 687 | if (!(mt7601u_bbp_rr(dev, 47) & 0x10)) |
| 688 | break; |
| 689 | if (!j) |
| 690 | dev_err(dev->dev, "%s timed out\n", __func__); |
| 691 | |
| 692 | /* TSSI read */ |
| 693 | mt7601u_bbp_wr(dev, 47, 0x40); |
| 694 | res[i] = mt7601u_bbp_rr(dev, 49); |
| 695 | } |
| 696 | |
| 697 | tssi_init_db = lin2dBd((short)res[1] - res[0]); |
| 698 | tssi_init_hvga_db = lin2dBd(((short)res[3] - res[2]) * 4); |
| 699 | dev->tssi_init = res[0]; |
| 700 | dev->tssi_init_hvga = res[2]; |
| 701 | dev->tssi_init_hvga_offset_db = tssi_init_hvga_db - tssi_init_db; |
| 702 | |
| 703 | dev_dbg(dev->dev, |
| 704 | "TSSI_init:%hhx db:%hx hvga:%hhx hvga_db:%hx off_db:%hx\n", |
| 705 | dev->tssi_init, tssi_init_db, dev->tssi_init_hvga, |
| 706 | tssi_init_hvga_db, dev->tssi_init_hvga_offset_db); |
| 707 | |
| 708 | mt7601u_bbp_wr(dev, 22, 0); |
| 709 | mt7601u_bbp_wr(dev, 244, 0); |
| 710 | |
| 711 | mt7601u_bbp_wr(dev, 21, 1); |
| 712 | udelay(1); |
| 713 | mt7601u_bbp_wr(dev, 21, 0); |
| 714 | |
| 715 | mt7601u_wr(dev, MT_RF_BYPASS_0, 0); |
| 716 | mt7601u_wr(dev, MT_RF_SETTING_0, 0); |
| 717 | |
| 718 | mt7601u_rf_wr(dev, 5, 3, rf_vga); |
| 719 | mt7601u_rf_wr(dev, 4, 39, rf_mixer); |
| 720 | mt7601u_bbp_wr(dev, 47, bbp_r47); |
| 721 | |
| 722 | mt7601u_set_initial_tssi(dev, tssi_init_db, tssi_init_hvga_db); |
| 723 | } |
| 724 | |
| 725 | static int mt7601u_temp_comp(struct mt7601u_dev *dev, bool on) |
| 726 | { |
| 727 | int ret, temp, hi_temp = 400, lo_temp = -200; |
| 728 | |
| 729 | temp = (dev->raw_temp - dev->ee->ref_temp) * MT_EE_TEMPERATURE_SLOPE; |
| 730 | dev->curr_temp = temp; |
| 731 | |
| 732 | /* DPD Calibration */ |
| 733 | if (temp - dev->dpd_temp > 450 || temp - dev->dpd_temp < -450) { |
| 734 | dev->dpd_temp = temp; |
| 735 | |
| 736 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp); |
| 737 | if (ret) |
| 738 | return ret; |
| 739 | |
| 740 | mt7601u_vco_cal(dev); |
| 741 | |
| 742 | dev_dbg(dev->dev, "Recalibrate DPD\n"); |
| 743 | } |
| 744 | |
| 745 | /* PLL Lock Protect */ |
| 746 | if (temp < -50 && !dev->pll_lock_protect) { /* < 20C */ |
| 747 | dev->pll_lock_protect = true; |
| 748 | |
| 749 | mt7601u_rf_wr(dev, 4, 4, 6); |
| 750 | mt7601u_rf_clear(dev, 4, 10, 0x30); |
| 751 | |
| 752 | dev_dbg(dev->dev, "PLL lock protect on - too cold\n"); |
| 753 | } else if (temp > 50 && dev->pll_lock_protect) { /* > 30C */ |
| 754 | dev->pll_lock_protect = false; |
| 755 | |
| 756 | mt7601u_rf_wr(dev, 4, 4, 0); |
| 757 | mt7601u_rf_rmw(dev, 4, 10, 0x30, 0x10); |
| 758 | |
| 759 | dev_dbg(dev->dev, "PLL lock protect off\n"); |
| 760 | } |
| 761 | |
| 762 | if (on) { |
| 763 | hi_temp -= 50; |
| 764 | lo_temp -= 50; |
| 765 | } |
| 766 | |
| 767 | /* BBP CR for H, L, N temperature */ |
| 768 | if (temp > hi_temp) |
| 769 | return mt7601u_bbp_temp(dev, MT_TEMP_MODE_HIGH, "high"); |
| 770 | else if (temp > lo_temp) |
| 771 | return mt7601u_bbp_temp(dev, MT_TEMP_MODE_NORMAL, "normal"); |
| 772 | else |
| 773 | return mt7601u_bbp_temp(dev, MT_TEMP_MODE_LOW, "low"); |
| 774 | } |
| 775 | |
| 776 | /* Note: this is used only with TSSI, we can just use trgt_pwr from eeprom. */ |
| 777 | static int mt7601u_current_tx_power(struct mt7601u_dev *dev) |
| 778 | { |
| 779 | return dev->ee->chan_pwr[dev->chandef.chan->hw_value - 1]; |
| 780 | } |
| 781 | |
| 782 | static bool mt7601u_use_hvga(struct mt7601u_dev *dev) |
| 783 | { |
| 784 | return !(mt7601u_current_tx_power(dev) > 20); |
| 785 | } |
| 786 | |
| 787 | static s16 |
| 788 | mt7601u_phy_rf_pa_mode_val(struct mt7601u_dev *dev, int phy_mode, int tx_rate) |
| 789 | { |
| 790 | static const s16 decode_tb[] = { 0, 8847, -5734, -5734 }; |
| 791 | u32 reg; |
| 792 | |
| 793 | switch (phy_mode) { |
| 794 | case MT_PHY_TYPE_OFDM: |
| 795 | tx_rate += 4; |
| 796 | case MT_PHY_TYPE_CCK: |
| 797 | reg = dev->rf_pa_mode[0]; |
| 798 | break; |
| 799 | default: |
| 800 | reg = dev->rf_pa_mode[1]; |
| 801 | break; |
| 802 | } |
| 803 | |
| 804 | return decode_tb[(reg >> (tx_rate * 2)) & 0x3]; |
| 805 | } |
| 806 | |
| 807 | static struct mt7601u_tssi_params |
| 808 | mt7601u_tssi_params_get(struct mt7601u_dev *dev) |
| 809 | { |
| 810 | static const u8 ofdm_pkt2rate[8] = { 6, 4, 2, 0, 7, 5, 3, 1 }; |
| 811 | static const int static_power[4] = { 0, -49152, -98304, 49152 }; |
| 812 | struct mt7601u_tssi_params p; |
| 813 | u8 bbp_r47, pkt_type, tx_rate; |
| 814 | struct power_per_rate *rate_table; |
| 815 | |
| 816 | bbp_r47 = mt7601u_bbp_rr(dev, 47); |
| 817 | |
| 818 | p.tssi0 = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TSSI); |
| 819 | dev->raw_temp = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TEMP); |
| 820 | pkt_type = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_PKT_T); |
| 821 | |
| 822 | p.trgt_power = mt7601u_current_tx_power(dev); |
| 823 | |
| 824 | switch (pkt_type & 0x03) { |
| 825 | case MT_PHY_TYPE_CCK: |
| 826 | tx_rate = (pkt_type >> 4) & 0x03; |
| 827 | rate_table = dev->ee->power_rate_table.cck; |
| 828 | break; |
| 829 | |
| 830 | case MT_PHY_TYPE_OFDM: |
| 831 | tx_rate = ofdm_pkt2rate[(pkt_type >> 4) & 0x07]; |
| 832 | rate_table = dev->ee->power_rate_table.ofdm; |
| 833 | break; |
| 834 | |
| 835 | default: |
| 836 | tx_rate = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TX_RATE); |
| 837 | tx_rate &= 0x7f; |
| 838 | rate_table = dev->ee->power_rate_table.ht; |
| 839 | break; |
| 840 | } |
| 841 | |
| 842 | if (dev->bw == MT_BW_20) |
| 843 | p.trgt_power += rate_table[tx_rate / 2].bw20; |
| 844 | else |
| 845 | p.trgt_power += rate_table[tx_rate / 2].bw40; |
| 846 | |
| 847 | p.trgt_power <<= 12; |
| 848 | |
| 849 | dev_dbg(dev->dev, "tx_rate:%02hhx pwr:%08x\n", tx_rate, p.trgt_power); |
| 850 | |
| 851 | p.trgt_power += mt7601u_phy_rf_pa_mode_val(dev, pkt_type & 0x03, |
| 852 | tx_rate); |
| 853 | |
| 854 | /* Channel 14, cck, bw20 */ |
| 855 | if ((pkt_type & 0x03) == MT_PHY_TYPE_CCK) { |
| 856 | if (mt7601u_bbp_rr(dev, 4) & 0x20) |
| 857 | p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 18022 : 9830; |
| 858 | else |
| 859 | p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 819 : 24576; |
| 860 | } |
| 861 | |
| 862 | p.trgt_power += static_power[mt7601u_bbp_rr(dev, 1) & 0x03]; |
| 863 | |
| 864 | p.trgt_power += dev->ee->tssi_data.tx0_delta_offset; |
| 865 | |
| 866 | dev_dbg(dev->dev, |
| 867 | "tssi:%02hhx t_power:%08x temp:%02hhx pkt_type:%02hhx\n", |
| 868 | p.tssi0, p.trgt_power, dev->raw_temp, pkt_type); |
| 869 | |
| 870 | return p; |
| 871 | } |
| 872 | |
| 873 | static bool mt7601u_tssi_read_ready(struct mt7601u_dev *dev) |
| 874 | { |
| 875 | return !(mt7601u_bbp_rr(dev, 47) & 0x10); |
| 876 | } |
| 877 | |
| 878 | static int mt7601u_tssi_cal(struct mt7601u_dev *dev) |
| 879 | { |
| 880 | struct mt7601u_tssi_params params; |
| 881 | int curr_pwr, diff_pwr; |
| 882 | char tssi_offset; |
| 883 | s8 tssi_init; |
| 884 | s16 tssi_m_dc, tssi_db; |
| 885 | bool hvga; |
| 886 | u32 val; |
| 887 | |
| 888 | if (!dev->ee->tssi_enabled) |
| 889 | return 0; |
| 890 | |
| 891 | hvga = mt7601u_use_hvga(dev); |
| 892 | if (!dev->tssi_read_trig) |
| 893 | return mt7601u_mcu_tssi_read_kick(dev, hvga); |
| 894 | |
| 895 | if (!mt7601u_tssi_read_ready(dev)) |
| 896 | return 0; |
| 897 | |
| 898 | params = mt7601u_tssi_params_get(dev); |
| 899 | |
| 900 | tssi_init = (hvga ? dev->tssi_init_hvga : dev->tssi_init); |
| 901 | tssi_m_dc = params.tssi0 - tssi_init; |
| 902 | tssi_db = lin2dBd(tssi_m_dc); |
| 903 | dev_dbg(dev->dev, "tssi dc:%04hx db:%04hx hvga:%d\n", |
| 904 | tssi_m_dc, tssi_db, hvga); |
| 905 | |
| 906 | if (dev->chandef.chan->hw_value < 5) |
| 907 | tssi_offset = dev->ee->tssi_data.offset[0]; |
| 908 | else if (dev->chandef.chan->hw_value < 9) |
| 909 | tssi_offset = dev->ee->tssi_data.offset[1]; |
| 910 | else |
| 911 | tssi_offset = dev->ee->tssi_data.offset[2]; |
| 912 | |
| 913 | if (hvga) |
| 914 | tssi_db -= dev->tssi_init_hvga_offset_db; |
| 915 | |
| 916 | curr_pwr = tssi_db * dev->ee->tssi_data.slope + (tssi_offset << 9); |
| 917 | diff_pwr = params.trgt_power - curr_pwr; |
| 918 | dev_dbg(dev->dev, "Power curr:%08x diff:%08x\n", curr_pwr, diff_pwr); |
| 919 | |
| 920 | if (params.tssi0 > 126 && diff_pwr > 0) { |
| 921 | dev_err(dev->dev, "Error: TSSI upper saturation\n"); |
| 922 | diff_pwr = 0; |
| 923 | } |
| 924 | if (params.tssi0 - tssi_init < 1 && diff_pwr < 0) { |
| 925 | dev_err(dev->dev, "Error: TSSI lower saturation\n"); |
| 926 | diff_pwr = 0; |
| 927 | } |
| 928 | |
| 929 | if ((dev->prev_pwr_diff ^ diff_pwr) < 0 && abs(diff_pwr) < 4096 && |
| 930 | (abs(diff_pwr) > abs(dev->prev_pwr_diff) || |
| 931 | (diff_pwr > 0 && diff_pwr == -dev->prev_pwr_diff))) |
| 932 | diff_pwr = 0; |
| 933 | else |
| 934 | dev->prev_pwr_diff = diff_pwr; |
| 935 | |
| 936 | diff_pwr += (diff_pwr > 0) ? 2048 : -2048; |
| 937 | diff_pwr /= 4096; |
| 938 | |
| 939 | dev_dbg(dev->dev, "final diff: %08x\n", diff_pwr); |
| 940 | |
| 941 | val = mt7601u_rr(dev, MT_TX_ALC_CFG_1); |
| 942 | curr_pwr = s6_to_int(MT76_GET(MT_TX_ALC_CFG_1_TEMP_COMP, val)); |
| 943 | diff_pwr += curr_pwr; |
| 944 | val = (val & ~MT_TX_ALC_CFG_1_TEMP_COMP) | int_to_s6(diff_pwr); |
| 945 | mt7601u_wr(dev, MT_TX_ALC_CFG_1, val); |
| 946 | |
| 947 | return mt7601u_mcu_tssi_read_kick(dev, hvga); |
| 948 | } |
| 949 | |
| 950 | static u8 mt7601u_agc_default(struct mt7601u_dev *dev) |
| 951 | { |
| 952 | return (dev->ee->lna_gain - 8) * 2 + 0x34; |
| 953 | } |
| 954 | |
| 955 | static void mt7601u_agc_reset(struct mt7601u_dev *dev) |
| 956 | { |
| 957 | u8 agc = mt7601u_agc_default(dev); |
| 958 | |
| 959 | mt7601u_bbp_wr(dev, 66, agc); |
| 960 | } |
| 961 | |
| 962 | void mt7601u_agc_save(struct mt7601u_dev *dev) |
| 963 | { |
| 964 | dev->agc_save = mt7601u_bbp_rr(dev, 66); |
| 965 | } |
| 966 | |
| 967 | void mt7601u_agc_restore(struct mt7601u_dev *dev) |
| 968 | { |
| 969 | mt7601u_bbp_wr(dev, 66, dev->agc_save); |
| 970 | } |
| 971 | |
| 972 | static void mt7601u_agc_tune(struct mt7601u_dev *dev) |
| 973 | { |
| 974 | u8 val = mt7601u_agc_default(dev); |
| 975 | |
| 976 | if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) |
| 977 | return; |
| 978 | |
| 979 | /* Note: only in STA mode and not dozing; perhaps do this only if |
| 980 | * there is enough rssi updates since last run? |
| 981 | * Rssi updates are only on beacons and U2M so should work... |
| 982 | */ |
| 983 | spin_lock_bh(&dev->con_mon_lock); |
| 984 | if (dev->avg_rssi <= -70) |
| 985 | val -= 0x20; |
| 986 | else if (dev->avg_rssi <= -60) |
| 987 | val -= 0x10; |
| 988 | spin_unlock_bh(&dev->con_mon_lock); |
| 989 | |
| 990 | if (val != mt7601u_bbp_rr(dev, 66)) |
| 991 | mt7601u_bbp_wr(dev, 66, val); |
| 992 | |
| 993 | /* TODO: also if lost a lot of beacons try resetting |
| 994 | * (see RTMPSetAGCInitValue() call in mlme.c). |
| 995 | */ |
| 996 | } |
| 997 | |
| 998 | static void mt7601u_phy_calibrate(struct work_struct *work) |
| 999 | { |
| 1000 | struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, |
| 1001 | cal_work.work); |
| 1002 | |
| 1003 | mt7601u_agc_tune(dev); |
| 1004 | mt7601u_tssi_cal(dev); |
| 1005 | /* If TSSI calibration was run it already updated temperature. */ |
| 1006 | if (!dev->ee->tssi_enabled) |
| 1007 | dev->raw_temp = mt7601u_read_temp(dev); |
| 1008 | mt7601u_temp_comp(dev, true); /* TODO: find right value for @on */ |
| 1009 | |
| 1010 | ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, |
| 1011 | MT_CALIBRATE_INTERVAL); |
| 1012 | } |
| 1013 | |
| 1014 | static unsigned long |
| 1015 | __mt7601u_phy_freq_cal(struct mt7601u_dev *dev, s8 last_offset, u8 phy_mode) |
| 1016 | { |
| 1017 | u8 activate_threshold, deactivate_threshold; |
| 1018 | |
| 1019 | trace_freq_cal_offset(dev, phy_mode, last_offset); |
| 1020 | |
| 1021 | /* No beacons received - reschedule soon */ |
| 1022 | if (last_offset == MT_FREQ_OFFSET_INVALID) |
| 1023 | return MT_FREQ_CAL_ADJ_INTERVAL; |
| 1024 | |
| 1025 | switch (phy_mode) { |
| 1026 | case MT_PHY_TYPE_CCK: |
| 1027 | activate_threshold = 19; |
| 1028 | deactivate_threshold = 5; |
| 1029 | break; |
| 1030 | case MT_PHY_TYPE_OFDM: |
| 1031 | activate_threshold = 102; |
| 1032 | deactivate_threshold = 32; |
| 1033 | break; |
| 1034 | case MT_PHY_TYPE_HT: |
| 1035 | case MT_PHY_TYPE_HT_GF: |
| 1036 | activate_threshold = 82; |
| 1037 | deactivate_threshold = 20; |
| 1038 | break; |
| 1039 | default: |
| 1040 | WARN_ON(1); |
| 1041 | return MT_FREQ_CAL_CHECK_INTERVAL; |
| 1042 | } |
| 1043 | |
| 1044 | if (abs(last_offset) >= activate_threshold) |
| 1045 | dev->freq_cal.adjusting = true; |
| 1046 | else if (abs(last_offset) <= deactivate_threshold) |
| 1047 | dev->freq_cal.adjusting = false; |
| 1048 | |
| 1049 | if (!dev->freq_cal.adjusting) |
| 1050 | return MT_FREQ_CAL_CHECK_INTERVAL; |
| 1051 | |
| 1052 | if (last_offset > deactivate_threshold) { |
| 1053 | if (dev->freq_cal.freq > 0) |
| 1054 | dev->freq_cal.freq--; |
| 1055 | else |
| 1056 | dev->freq_cal.adjusting = false; |
| 1057 | } else if (last_offset < -deactivate_threshold) { |
| 1058 | if (dev->freq_cal.freq < 0xbf) |
| 1059 | dev->freq_cal.freq++; |
| 1060 | else |
| 1061 | dev->freq_cal.adjusting = false; |
| 1062 | } |
| 1063 | |
| 1064 | trace_freq_cal_adjust(dev, dev->freq_cal.freq); |
| 1065 | mt7601u_rf_wr(dev, 0, 12, dev->freq_cal.freq); |
| 1066 | mt7601u_vco_cal(dev); |
| 1067 | |
| 1068 | return dev->freq_cal.adjusting ? MT_FREQ_CAL_ADJ_INTERVAL : |
| 1069 | MT_FREQ_CAL_CHECK_INTERVAL; |
| 1070 | } |
| 1071 | |
| 1072 | static void mt7601u_phy_freq_cal(struct work_struct *work) |
| 1073 | { |
| 1074 | struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, |
| 1075 | freq_cal.work.work); |
| 1076 | s8 last_offset; |
| 1077 | u8 phy_mode; |
| 1078 | unsigned long delay; |
| 1079 | |
| 1080 | spin_lock_bh(&dev->con_mon_lock); |
| 1081 | last_offset = dev->bcn_freq_off; |
| 1082 | phy_mode = dev->bcn_phy_mode; |
| 1083 | spin_unlock_bh(&dev->con_mon_lock); |
| 1084 | |
| 1085 | delay = __mt7601u_phy_freq_cal(dev, last_offset, phy_mode); |
| 1086 | ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, delay); |
| 1087 | |
| 1088 | spin_lock_bh(&dev->con_mon_lock); |
| 1089 | dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID; |
| 1090 | spin_unlock_bh(&dev->con_mon_lock); |
| 1091 | } |
| 1092 | |
| 1093 | void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev, |
| 1094 | struct ieee80211_bss_conf *info) |
| 1095 | { |
| 1096 | if (!info->assoc) |
| 1097 | cancel_delayed_work_sync(&dev->freq_cal.work); |
| 1098 | |
| 1099 | /* Start/stop collecting beacon data */ |
| 1100 | spin_lock_bh(&dev->con_mon_lock); |
| 1101 | ether_addr_copy(dev->ap_bssid, info->bssid); |
| 1102 | dev->avg_rssi = 0; |
| 1103 | dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID; |
| 1104 | spin_unlock_bh(&dev->con_mon_lock); |
| 1105 | |
| 1106 | dev->freq_cal.freq = dev->ee->rf_freq_off; |
| 1107 | dev->freq_cal.enabled = info->assoc; |
| 1108 | dev->freq_cal.adjusting = false; |
| 1109 | |
| 1110 | if (info->assoc) |
| 1111 | ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, |
| 1112 | MT_FREQ_CAL_INIT_DELAY); |
| 1113 | } |
| 1114 | |
| 1115 | static int mt7601u_init_cal(struct mt7601u_dev *dev) |
| 1116 | { |
| 1117 | u32 mac_ctrl; |
| 1118 | int ret; |
| 1119 | |
| 1120 | dev->raw_temp = mt7601u_read_bootup_temp(dev); |
| 1121 | dev->curr_temp = (dev->raw_temp - dev->ee->ref_temp) * |
| 1122 | MT_EE_TEMPERATURE_SLOPE; |
| 1123 | dev->dpd_temp = dev->curr_temp; |
| 1124 | |
| 1125 | mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); |
| 1126 | |
| 1127 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_R, 0); |
| 1128 | if (ret) |
| 1129 | return ret; |
| 1130 | |
| 1131 | ret = mt7601u_rf_rr(dev, 0, 4); |
| 1132 | if (ret < 0) |
| 1133 | return ret; |
| 1134 | ret |= 0x80; |
| 1135 | ret = mt7601u_rf_wr(dev, 0, 4, ret); |
| 1136 | if (ret) |
| 1137 | return ret; |
| 1138 | msleep(2); |
| 1139 | |
| 1140 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXDCOC, 0); |
| 1141 | if (ret) |
| 1142 | return ret; |
| 1143 | |
| 1144 | mt7601u_rxdc_cal(dev); |
| 1145 | |
| 1146 | ret = mt7601u_set_bw_filter(dev, true); |
| 1147 | if (ret) |
| 1148 | return ret; |
| 1149 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_LOFT, 0); |
| 1150 | if (ret) |
| 1151 | return ret; |
| 1152 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXIQ, 0); |
| 1153 | if (ret) |
| 1154 | return ret; |
| 1155 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_RXIQ, 0); |
| 1156 | if (ret) |
| 1157 | return ret; |
| 1158 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp); |
| 1159 | if (ret) |
| 1160 | return ret; |
| 1161 | |
| 1162 | mt7601u_rxdc_cal(dev); |
| 1163 | |
| 1164 | mt7601u_tssi_dc_gain_cal(dev); |
| 1165 | |
| 1166 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl); |
| 1167 | |
| 1168 | mt7601u_temp_comp(dev, true); |
| 1169 | |
| 1170 | return 0; |
| 1171 | } |
| 1172 | |
| 1173 | int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw) |
| 1174 | { |
| 1175 | u32 val, old; |
| 1176 | |
| 1177 | if (bw == dev->bw) { |
| 1178 | /* Vendor driver does the rmc even when no change is needed. */ |
| 1179 | mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10); |
| 1180 | |
| 1181 | return 0; |
| 1182 | } |
| 1183 | dev->bw = bw; |
| 1184 | |
| 1185 | /* Stop MAC for the time of bw change */ |
| 1186 | old = mt7601u_rr(dev, MT_MAC_SYS_CTRL); |
| 1187 | val = old & ~(MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); |
| 1188 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, val); |
| 1189 | mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, |
| 1190 | 0, 500000); |
| 1191 | |
| 1192 | mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10); |
| 1193 | |
| 1194 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, old); |
| 1195 | |
| 1196 | return mt7601u_load_bbp_temp_table_bw(dev); |
| 1197 | } |
| 1198 | |
| 1199 | /** |
| 1200 | * mt7601u_set_rx_path - set rx path in BBP |
| 1201 | * @dev: pointer to adapter structure |
| 1202 | * @path: rx path to set values are 0-based |
| 1203 | */ |
| 1204 | void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path) |
| 1205 | { |
| 1206 | mt7601u_bbp_rmw(dev, 3, 0x18, path << 3); |
| 1207 | } |
| 1208 | |
| 1209 | /** |
| 1210 | * mt7601u_set_tx_dac - set which tx DAC to use |
| 1211 | * @dev: pointer to adapter structure |
| 1212 | * @path: DAC index, values are 0-based |
| 1213 | */ |
| 1214 | void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 dac) |
| 1215 | { |
| 1216 | mt7601u_bbp_rmc(dev, 1, 0x18, dac << 3); |
| 1217 | } |
| 1218 | |
| 1219 | int mt7601u_phy_init(struct mt7601u_dev *dev) |
| 1220 | { |
| 1221 | int ret; |
| 1222 | |
| 1223 | dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0); |
| 1224 | dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1); |
| 1225 | |
| 1226 | ret = mt7601u_rf_wr(dev, 0, 12, dev->ee->rf_freq_off); |
| 1227 | if (ret) |
| 1228 | return ret; |
| 1229 | ret = mt7601u_write_reg_pairs(dev, 0, rf_central, |
| 1230 | ARRAY_SIZE(rf_central)); |
| 1231 | if (ret) |
| 1232 | return ret; |
| 1233 | ret = mt7601u_write_reg_pairs(dev, 0, rf_channel, |
| 1234 | ARRAY_SIZE(rf_channel)); |
| 1235 | if (ret) |
| 1236 | return ret; |
| 1237 | ret = mt7601u_write_reg_pairs(dev, 0, rf_vga, ARRAY_SIZE(rf_vga)); |
| 1238 | if (ret) |
| 1239 | return ret; |
| 1240 | |
| 1241 | ret = mt7601u_init_cal(dev); |
| 1242 | if (ret) |
| 1243 | return ret; |
| 1244 | |
| 1245 | dev->prev_pwr_diff = 100; |
| 1246 | |
| 1247 | INIT_DELAYED_WORK(&dev->cal_work, mt7601u_phy_calibrate); |
| 1248 | INIT_DELAYED_WORK(&dev->freq_cal.work, mt7601u_phy_freq_cal); |
| 1249 | |
| 1250 | return 0; |
| 1251 | } |