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Mika Westerbergcd7bed02013-01-22 12:26:28 +02001/*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef SPI_PXA2XX_H
11#define SPI_PXA2XX_H
12
Mika Westerberg59288082013-01-22 12:26:29 +020013#include <linux/atomic.h>
14#include <linux/dmaengine.h>
Mika Westerbergcd7bed02013-01-22 12:26:28 +020015#include <linux/errno.h>
16#include <linux/io.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/pxa2xx_ssp.h>
Mika Westerberg59288082013-01-22 12:26:29 +020020#include <linux/scatterlist.h>
21#include <linux/sizes.h>
Mika Westerbergcd7bed02013-01-22 12:26:28 +020022#include <linux/spi/spi.h>
23#include <linux/spi/pxa2xx_spi.h>
24
25struct driver_data {
26 /* Driver model hookup */
27 struct platform_device *pdev;
28
29 /* SSP Info */
30 struct ssp_device *ssp;
31
32 /* SPI framework hookup */
33 enum pxa_ssp_type ssp_type;
34 struct spi_master *master;
35
36 /* PXA hookup */
37 struct pxa2xx_spi_master *master_info;
38
Mika Westerbergcd7bed02013-01-22 12:26:28 +020039 /* SSP register addresses */
40 void __iomem *ioaddr;
41 u32 ssdr_physical;
42
43 /* SSP masks*/
44 u32 dma_cr1;
45 u32 int_cr1;
46 u32 clear_sr;
47 u32 mask_sr;
48
Mika Westerbergcd7bed02013-01-22 12:26:28 +020049 /* Message Transfer pump */
50 struct tasklet_struct pump_transfers;
51
Mika Westerberg59288082013-01-22 12:26:29 +020052 /* DMA engine support */
Mika Westerberg59288082013-01-22 12:26:29 +020053 atomic_t dma_running;
54
Mika Westerbergcd7bed02013-01-22 12:26:28 +020055 /* Current message transfer state info */
56 struct spi_message *cur_msg;
57 struct spi_transfer *cur_transfer;
58 struct chip_data *cur_chip;
59 size_t len;
60 void *tx;
61 void *tx_end;
62 void *rx;
63 void *rx_end;
Mika Westerbergcd7bed02013-01-22 12:26:28 +020064 u8 n_bytes;
65 int (*write)(struct driver_data *drv_data);
66 int (*read)(struct driver_data *drv_data);
67 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
68 void (*cs_control)(u32 command);
Mika Westerberga0d26422013-01-22 12:26:32 +020069
70 void __iomem *lpss_base;
Mika Westerbergcd7bed02013-01-22 12:26:28 +020071};
72
73struct chip_data {
Mika Westerbergcd7bed02013-01-22 12:26:28 +020074 u32 cr1;
Weike Chene5262d02014-11-26 02:35:10 -080075 u32 dds_rate;
Mika Westerbergcd7bed02013-01-22 12:26:28 +020076 u32 timeout;
77 u8 n_bytes;
78 u32 dma_burst_size;
79 u32 threshold;
80 u32 dma_threshold;
Mika Westerberga0d26422013-01-22 12:26:32 +020081 u16 lpss_rx_threshold;
82 u16 lpss_tx_threshold;
Mika Westerbergcd7bed02013-01-22 12:26:28 +020083 u8 enable_dma;
Mika Westerbergcd7bed02013-01-22 12:26:28 +020084 union {
85 int gpio_cs;
86 unsigned int frm;
87 };
88 int gpio_cs_inverted;
89 int (*write)(struct driver_data *drv_data);
90 int (*read)(struct driver_data *drv_data);
91 void (*cs_control)(u32 command);
92};
93
Jarkko Nikulac039dd22014-12-18 15:04:23 +020094static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
95 unsigned reg)
96{
97 return __raw_readl(drv_data->ioaddr + reg);
98}
Mika Westerbergcd7bed02013-01-22 12:26:28 +020099
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200100static inline void pxa2xx_spi_write(const struct driver_data *drv_data,
101 unsigned reg, u32 val)
102{
103 __raw_writel(val, drv_data->ioaddr + reg);
104}
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200105
106#define START_STATE ((void *)0)
107#define RUNNING_STATE ((void *)1)
108#define DONE_STATE ((void *)2)
109#define ERROR_STATE ((void *)-1)
110
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200111#define IS_DMA_ALIGNED(x) IS_ALIGNED((unsigned long)(x), DMA_ALIGNMENT)
112#define DMA_ALIGNMENT 8
113
114static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
115{
Weike Chene5262d02014-11-26 02:35:10 -0800116 switch (drv_data->ssp_type) {
117 case PXA25x_SSP:
118 case CE4100_SSP:
119 case QUARK_X1000_SSP:
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200120 return 1;
Weike Chene5262d02014-11-26 02:35:10 -0800121 default:
122 return 0;
123 }
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200124}
125
126static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
127{
Weike Chene5262d02014-11-26 02:35:10 -0800128 if (drv_data->ssp_type == CE4100_SSP ||
129 drv_data->ssp_type == QUARK_X1000_SSP)
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200130 val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200131
Jarkko Nikulac039dd22014-12-18 15:04:23 +0200132 pxa2xx_spi_write(drv_data, SSSR, val);
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200133}
134
135extern int pxa2xx_spi_flush(struct driver_data *drv_data);
136extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
137
Mika Westerberg59288082013-01-22 12:26:29 +0200138#define MAX_DMA_LEN SZ_64K
139#define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
Mika Westerberg59288082013-01-22 12:26:29 +0200140
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200141extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
142extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst);
143extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
144extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
145extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200146extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
147 struct spi_device *spi,
148 u8 bits_per_word,
149 u32 *burst_code,
150 u32 *threshold);
Mika Westerbergcd7bed02013-01-22 12:26:28 +0200151
152#endif /* SPI_PXA2XX_H */