H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_APICDEF_H |
| 2 | #define _ASM_X86_APICDEF_H |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 3 | |
| 4 | /* |
| 5 | * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) |
| 6 | * |
| 7 | * Alan Cox <Alan.Cox@linux.org>, 1995. |
| 8 | * Ingo Molnar <mingo@redhat.com>, 1999, 2000 |
| 9 | */ |
| 10 | |
| 11 | #define APIC_DEFAULT_PHYS_BASE 0xfee00000 |
| 12 | |
| 13 | #define APIC_ID 0x20 |
| 14 | |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 15 | #define APIC_LVR 0x30 |
| 16 | #define APIC_LVR_MASK 0xFF00FF |
Gleb Natapov | fc61b80 | 2009-07-05 17:39:35 +0300 | [diff] [blame^] | 17 | #define APIC_LVR_DIRECTED_EOI (1 << 24) |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 18 | #define GET_APIC_VERSION(x) ((x) & 0xFFu) |
| 19 | #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) |
Glauber de Oliveira Costa | ac56ef6 | 2008-03-19 14:25:10 -0300 | [diff] [blame] | 20 | #ifdef CONFIG_X86_32 |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 21 | # define APIC_INTEGRATED(x) ((x) & 0xF0u) |
Glauber de Oliveira Costa | ac56ef6 | 2008-03-19 14:25:10 -0300 | [diff] [blame] | 22 | #else |
| 23 | # define APIC_INTEGRATED(x) (1) |
| 24 | #endif |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 25 | #define APIC_XAPIC(x) ((x) >= 0x14) |
Andreas Herrmann | 97a5271 | 2009-05-08 18:23:50 +0200 | [diff] [blame] | 26 | #define APIC_EXT_SPACE(x) ((x) & 0x80000000) |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 27 | #define APIC_TASKPRI 0x80 |
| 28 | #define APIC_TPRI_MASK 0xFFu |
| 29 | #define APIC_ARBPRI 0x90 |
| 30 | #define APIC_ARBPRI_MASK 0xFFu |
| 31 | #define APIC_PROCPRI 0xA0 |
| 32 | #define APIC_EOI 0xB0 |
| 33 | #define APIC_EIO_ACK 0x0 |
| 34 | #define APIC_RRR 0xC0 |
| 35 | #define APIC_LDR 0xD0 |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 36 | #define APIC_LDR_MASK (0xFFu << 24) |
| 37 | #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) |
| 38 | #define SET_APIC_LOGICAL_ID(x) (((x) << 24)) |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 39 | #define APIC_ALL_CPUS 0xFFu |
| 40 | #define APIC_DFR 0xE0 |
| 41 | #define APIC_DFR_CLUSTER 0x0FFFFFFFul |
| 42 | #define APIC_DFR_FLAT 0xFFFFFFFFul |
| 43 | #define APIC_SPIV 0xF0 |
Gleb Natapov | fc61b80 | 2009-07-05 17:39:35 +0300 | [diff] [blame^] | 44 | #define APIC_SPIV_DIRECTED_EOI (1 << 12) |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 45 | #define APIC_SPIV_FOCUS_DISABLED (1 << 9) |
| 46 | #define APIC_SPIV_APIC_ENABLED (1 << 8) |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 47 | #define APIC_ISR 0x100 |
| 48 | #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ |
| 49 | #define APIC_TMR 0x180 |
| 50 | #define APIC_IRR 0x200 |
| 51 | #define APIC_ESR 0x280 |
| 52 | #define APIC_ESR_SEND_CS 0x00001 |
| 53 | #define APIC_ESR_RECV_CS 0x00002 |
| 54 | #define APIC_ESR_SEND_ACC 0x00004 |
| 55 | #define APIC_ESR_RECV_ACC 0x00008 |
| 56 | #define APIC_ESR_SENDILL 0x00020 |
| 57 | #define APIC_ESR_RECVILL 0x00040 |
| 58 | #define APIC_ESR_ILLREGA 0x00080 |
Andi Kleen | 03195c6 | 2009-02-12 13:49:35 +0100 | [diff] [blame] | 59 | #define APIC_LVTCMCI 0x2f0 |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 60 | #define APIC_ICR 0x300 |
| 61 | #define APIC_DEST_SELF 0x40000 |
| 62 | #define APIC_DEST_ALLINC 0x80000 |
| 63 | #define APIC_DEST_ALLBUT 0xC0000 |
| 64 | #define APIC_ICR_RR_MASK 0x30000 |
| 65 | #define APIC_ICR_RR_INVALID 0x00000 |
| 66 | #define APIC_ICR_RR_INPROG 0x10000 |
| 67 | #define APIC_ICR_RR_VALID 0x20000 |
| 68 | #define APIC_INT_LEVELTRIG 0x08000 |
| 69 | #define APIC_INT_ASSERT 0x04000 |
| 70 | #define APIC_ICR_BUSY 0x01000 |
| 71 | #define APIC_DEST_LOGICAL 0x00800 |
| 72 | #define APIC_DEST_PHYSICAL 0x00000 |
| 73 | #define APIC_DM_FIXED 0x00000 |
| 74 | #define APIC_DM_LOWEST 0x00100 |
| 75 | #define APIC_DM_SMI 0x00200 |
| 76 | #define APIC_DM_REMRD 0x00300 |
| 77 | #define APIC_DM_NMI 0x00400 |
| 78 | #define APIC_DM_INIT 0x00500 |
| 79 | #define APIC_DM_STARTUP 0x00600 |
| 80 | #define APIC_DM_EXTINT 0x00700 |
| 81 | #define APIC_VECTOR_MASK 0x000FF |
| 82 | #define APIC_ICR2 0x310 |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 83 | #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) |
| 84 | #define SET_APIC_DEST_FIELD(x) ((x) << 24) |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 85 | #define APIC_LVTT 0x320 |
| 86 | #define APIC_LVTTHMR 0x330 |
| 87 | #define APIC_LVTPC 0x340 |
| 88 | #define APIC_LVT0 0x350 |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 89 | #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) |
| 90 | #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) |
| 91 | #define SET_APIC_TIMER_BASE(x) (((x) << 18)) |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 92 | #define APIC_TIMER_BASE_CLKIN 0x0 |
| 93 | #define APIC_TIMER_BASE_TMBASE 0x1 |
| 94 | #define APIC_TIMER_BASE_DIV 0x2 |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 95 | #define APIC_LVT_TIMER_PERIODIC (1 << 17) |
| 96 | #define APIC_LVT_MASKED (1 << 16) |
| 97 | #define APIC_LVT_LEVEL_TRIGGER (1 << 15) |
| 98 | #define APIC_LVT_REMOTE_IRR (1 << 14) |
| 99 | #define APIC_INPUT_POLARITY (1 << 13) |
| 100 | #define APIC_SEND_PENDING (1 << 12) |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 101 | #define APIC_MODE_MASK 0x700 |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 102 | #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) |
| 103 | #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 104 | #define APIC_MODE_FIXED 0x0 |
| 105 | #define APIC_MODE_NMI 0x4 |
| 106 | #define APIC_MODE_EXTINT 0x7 |
| 107 | #define APIC_LVT1 0x360 |
| 108 | #define APIC_LVTERR 0x370 |
| 109 | #define APIC_TMICT 0x380 |
| 110 | #define APIC_TMCCT 0x390 |
| 111 | #define APIC_TDCR 0x3E0 |
Suresh Siddha | 13c88fb5 | 2008-07-10 11:16:52 -0700 | [diff] [blame] | 112 | #define APIC_SELF_IPI 0x3F0 |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 113 | #define APIC_TDR_DIV_TMBASE (1 << 2) |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 114 | #define APIC_TDR_DIV_1 0xB |
| 115 | #define APIC_TDR_DIV_2 0x0 |
| 116 | #define APIC_TDR_DIV_4 0x1 |
| 117 | #define APIC_TDR_DIV_8 0x2 |
| 118 | #define APIC_TDR_DIV_16 0x3 |
| 119 | #define APIC_TDR_DIV_32 0x8 |
| 120 | #define APIC_TDR_DIV_64 0x9 |
| 121 | #define APIC_TDR_DIV_128 0xA |
Andreas Herrmann | 97a5271 | 2009-05-08 18:23:50 +0200 | [diff] [blame] | 122 | #define APIC_EFEAT 0x400 |
| 123 | #define APIC_ECTRL 0x410 |
| 124 | #define APIC_EILVTn(n) (0x500 + 0x10 * n) |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 125 | #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 126 | #define APIC_EILVT_NR_AMD_10H 4 |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 127 | #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) |
Robert Richter | 7b83dae | 2008-01-30 13:30:40 +0100 | [diff] [blame] | 128 | #define APIC_EILVT_MSG_FIX 0x0 |
| 129 | #define APIC_EILVT_MSG_SMI 0x2 |
| 130 | #define APIC_EILVT_MSG_NMI 0x4 |
| 131 | #define APIC_EILVT_MSG_EXT 0x7 |
Joe Perches | 79a4a96 | 2008-03-23 01:01:39 -0700 | [diff] [blame] | 132 | #define APIC_EILVT_MASKED (1 << 16) |
Thomas Gleixner | cff90db | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 133 | |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 134 | #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) |
Suresh Siddha | 13c88fb5 | 2008-07-10 11:16:52 -0700 | [diff] [blame] | 135 | #define APIC_BASE_MSR 0x800 |
| 136 | #define X2APIC_ENABLE (1UL << 10) |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 137 | |
Thomas Gleixner | 96a388d | 2007-10-11 11:20:03 +0200 | [diff] [blame] | 138 | #ifdef CONFIG_X86_32 |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 139 | # define MAX_IO_APICS 64 |
Thomas Gleixner | 96a388d | 2007-10-11 11:20:03 +0200 | [diff] [blame] | 140 | #else |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 141 | # define MAX_IO_APICS 128 |
Jack Steiner | a65d1d6 | 2008-03-28 14:12:08 -0500 | [diff] [blame] | 142 | # define MAX_LOCAL_APIC 32768 |
Thomas Gleixner | 2d53955 | 2008-01-30 13:30:14 +0100 | [diff] [blame] | 143 | #endif |
| 144 | |
| 145 | /* |
| 146 | * All x86-64 systems are xAPIC compatible. |
| 147 | * In the following, "apicid" is a physical APIC ID. |
| 148 | */ |
| 149 | #define XAPIC_DEST_CPUS_SHIFT 4 |
| 150 | #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) |
| 151 | #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) |
| 152 | #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) |
| 153 | #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) |
| 154 | #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) |
| 155 | #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) |
| 156 | |
| 157 | /* |
| 158 | * the local APIC register structure, memory mapped. Not terribly well |
| 159 | * tested, but we might eventually use this one in the future - the |
| 160 | * problem why we cannot use it right now is the P5 APIC, it has an |
| 161 | * errata which cannot take 8-bit reads and writes, only 32-bit ones ... |
| 162 | */ |
| 163 | #define u32 unsigned int |
| 164 | |
| 165 | struct local_apic { |
| 166 | |
| 167 | /*000*/ struct { u32 __reserved[4]; } __reserved_01; |
| 168 | |
| 169 | /*010*/ struct { u32 __reserved[4]; } __reserved_02; |
| 170 | |
| 171 | /*020*/ struct { /* APIC ID Register */ |
| 172 | u32 __reserved_1 : 24, |
| 173 | phys_apic_id : 4, |
| 174 | __reserved_2 : 4; |
| 175 | u32 __reserved[3]; |
| 176 | } id; |
| 177 | |
| 178 | /*030*/ const |
| 179 | struct { /* APIC Version Register */ |
| 180 | u32 version : 8, |
| 181 | __reserved_1 : 8, |
| 182 | max_lvt : 8, |
| 183 | __reserved_2 : 8; |
| 184 | u32 __reserved[3]; |
| 185 | } version; |
| 186 | |
| 187 | /*040*/ struct { u32 __reserved[4]; } __reserved_03; |
| 188 | |
| 189 | /*050*/ struct { u32 __reserved[4]; } __reserved_04; |
| 190 | |
| 191 | /*060*/ struct { u32 __reserved[4]; } __reserved_05; |
| 192 | |
| 193 | /*070*/ struct { u32 __reserved[4]; } __reserved_06; |
| 194 | |
| 195 | /*080*/ struct { /* Task Priority Register */ |
| 196 | u32 priority : 8, |
| 197 | __reserved_1 : 24; |
| 198 | u32 __reserved_2[3]; |
| 199 | } tpr; |
| 200 | |
| 201 | /*090*/ const |
| 202 | struct { /* Arbitration Priority Register */ |
| 203 | u32 priority : 8, |
| 204 | __reserved_1 : 24; |
| 205 | u32 __reserved_2[3]; |
| 206 | } apr; |
| 207 | |
| 208 | /*0A0*/ const |
| 209 | struct { /* Processor Priority Register */ |
| 210 | u32 priority : 8, |
| 211 | __reserved_1 : 24; |
| 212 | u32 __reserved_2[3]; |
| 213 | } ppr; |
| 214 | |
| 215 | /*0B0*/ struct { /* End Of Interrupt Register */ |
| 216 | u32 eoi; |
| 217 | u32 __reserved[3]; |
| 218 | } eoi; |
| 219 | |
| 220 | /*0C0*/ struct { u32 __reserved[4]; } __reserved_07; |
| 221 | |
| 222 | /*0D0*/ struct { /* Logical Destination Register */ |
| 223 | u32 __reserved_1 : 24, |
| 224 | logical_dest : 8; |
| 225 | u32 __reserved_2[3]; |
| 226 | } ldr; |
| 227 | |
| 228 | /*0E0*/ struct { /* Destination Format Register */ |
| 229 | u32 __reserved_1 : 28, |
| 230 | model : 4; |
| 231 | u32 __reserved_2[3]; |
| 232 | } dfr; |
| 233 | |
| 234 | /*0F0*/ struct { /* Spurious Interrupt Vector Register */ |
| 235 | u32 spurious_vector : 8, |
| 236 | apic_enabled : 1, |
| 237 | focus_cpu : 1, |
| 238 | __reserved_2 : 22; |
| 239 | u32 __reserved_3[3]; |
| 240 | } svr; |
| 241 | |
| 242 | /*100*/ struct { /* In Service Register */ |
| 243 | /*170*/ u32 bitfield; |
| 244 | u32 __reserved[3]; |
| 245 | } isr [8]; |
| 246 | |
| 247 | /*180*/ struct { /* Trigger Mode Register */ |
| 248 | /*1F0*/ u32 bitfield; |
| 249 | u32 __reserved[3]; |
| 250 | } tmr [8]; |
| 251 | |
| 252 | /*200*/ struct { /* Interrupt Request Register */ |
| 253 | /*270*/ u32 bitfield; |
| 254 | u32 __reserved[3]; |
| 255 | } irr [8]; |
| 256 | |
| 257 | /*280*/ union { /* Error Status Register */ |
| 258 | struct { |
| 259 | u32 send_cs_error : 1, |
| 260 | receive_cs_error : 1, |
| 261 | send_accept_error : 1, |
| 262 | receive_accept_error : 1, |
| 263 | __reserved_1 : 1, |
| 264 | send_illegal_vector : 1, |
| 265 | receive_illegal_vector : 1, |
| 266 | illegal_register_address : 1, |
| 267 | __reserved_2 : 24; |
| 268 | u32 __reserved_3[3]; |
| 269 | } error_bits; |
| 270 | struct { |
| 271 | u32 errors; |
| 272 | u32 __reserved_3[3]; |
| 273 | } all_errors; |
| 274 | } esr; |
| 275 | |
| 276 | /*290*/ struct { u32 __reserved[4]; } __reserved_08; |
| 277 | |
| 278 | /*2A0*/ struct { u32 __reserved[4]; } __reserved_09; |
| 279 | |
| 280 | /*2B0*/ struct { u32 __reserved[4]; } __reserved_10; |
| 281 | |
| 282 | /*2C0*/ struct { u32 __reserved[4]; } __reserved_11; |
| 283 | |
| 284 | /*2D0*/ struct { u32 __reserved[4]; } __reserved_12; |
| 285 | |
| 286 | /*2E0*/ struct { u32 __reserved[4]; } __reserved_13; |
| 287 | |
| 288 | /*2F0*/ struct { u32 __reserved[4]; } __reserved_14; |
| 289 | |
| 290 | /*300*/ struct { /* Interrupt Command Register 1 */ |
| 291 | u32 vector : 8, |
| 292 | delivery_mode : 3, |
| 293 | destination_mode : 1, |
| 294 | delivery_status : 1, |
| 295 | __reserved_1 : 1, |
| 296 | level : 1, |
| 297 | trigger : 1, |
| 298 | __reserved_2 : 2, |
| 299 | shorthand : 2, |
| 300 | __reserved_3 : 12; |
| 301 | u32 __reserved_4[3]; |
| 302 | } icr1; |
| 303 | |
| 304 | /*310*/ struct { /* Interrupt Command Register 2 */ |
| 305 | union { |
| 306 | u32 __reserved_1 : 24, |
| 307 | phys_dest : 4, |
| 308 | __reserved_2 : 4; |
| 309 | u32 __reserved_3 : 24, |
| 310 | logical_dest : 8; |
| 311 | } dest; |
| 312 | u32 __reserved_4[3]; |
| 313 | } icr2; |
| 314 | |
| 315 | /*320*/ struct { /* LVT - Timer */ |
| 316 | u32 vector : 8, |
| 317 | __reserved_1 : 4, |
| 318 | delivery_status : 1, |
| 319 | __reserved_2 : 3, |
| 320 | mask : 1, |
| 321 | timer_mode : 1, |
| 322 | __reserved_3 : 14; |
| 323 | u32 __reserved_4[3]; |
| 324 | } lvt_timer; |
| 325 | |
| 326 | /*330*/ struct { /* LVT - Thermal Sensor */ |
| 327 | u32 vector : 8, |
| 328 | delivery_mode : 3, |
| 329 | __reserved_1 : 1, |
| 330 | delivery_status : 1, |
| 331 | __reserved_2 : 3, |
| 332 | mask : 1, |
| 333 | __reserved_3 : 15; |
| 334 | u32 __reserved_4[3]; |
| 335 | } lvt_thermal; |
| 336 | |
| 337 | /*340*/ struct { /* LVT - Performance Counter */ |
| 338 | u32 vector : 8, |
| 339 | delivery_mode : 3, |
| 340 | __reserved_1 : 1, |
| 341 | delivery_status : 1, |
| 342 | __reserved_2 : 3, |
| 343 | mask : 1, |
| 344 | __reserved_3 : 15; |
| 345 | u32 __reserved_4[3]; |
| 346 | } lvt_pc; |
| 347 | |
| 348 | /*350*/ struct { /* LVT - LINT0 */ |
| 349 | u32 vector : 8, |
| 350 | delivery_mode : 3, |
| 351 | __reserved_1 : 1, |
| 352 | delivery_status : 1, |
| 353 | polarity : 1, |
| 354 | remote_irr : 1, |
| 355 | trigger : 1, |
| 356 | mask : 1, |
| 357 | __reserved_2 : 15; |
| 358 | u32 __reserved_3[3]; |
| 359 | } lvt_lint0; |
| 360 | |
| 361 | /*360*/ struct { /* LVT - LINT1 */ |
| 362 | u32 vector : 8, |
| 363 | delivery_mode : 3, |
| 364 | __reserved_1 : 1, |
| 365 | delivery_status : 1, |
| 366 | polarity : 1, |
| 367 | remote_irr : 1, |
| 368 | trigger : 1, |
| 369 | mask : 1, |
| 370 | __reserved_2 : 15; |
| 371 | u32 __reserved_3[3]; |
| 372 | } lvt_lint1; |
| 373 | |
| 374 | /*370*/ struct { /* LVT - Error */ |
| 375 | u32 vector : 8, |
| 376 | __reserved_1 : 4, |
| 377 | delivery_status : 1, |
| 378 | __reserved_2 : 3, |
| 379 | mask : 1, |
| 380 | __reserved_3 : 15; |
| 381 | u32 __reserved_4[3]; |
| 382 | } lvt_error; |
| 383 | |
| 384 | /*380*/ struct { /* Timer Initial Count Register */ |
| 385 | u32 initial_count; |
| 386 | u32 __reserved_2[3]; |
| 387 | } timer_icr; |
| 388 | |
| 389 | /*390*/ const |
| 390 | struct { /* Timer Current Count Register */ |
| 391 | u32 curr_count; |
| 392 | u32 __reserved_2[3]; |
| 393 | } timer_ccr; |
| 394 | |
| 395 | /*3A0*/ struct { u32 __reserved[4]; } __reserved_16; |
| 396 | |
| 397 | /*3B0*/ struct { u32 __reserved[4]; } __reserved_17; |
| 398 | |
| 399 | /*3C0*/ struct { u32 __reserved[4]; } __reserved_18; |
| 400 | |
| 401 | /*3D0*/ struct { u32 __reserved[4]; } __reserved_19; |
| 402 | |
| 403 | /*3E0*/ struct { /* Timer Divide Configuration Register */ |
| 404 | u32 divisor : 4, |
| 405 | __reserved_1 : 28; |
| 406 | u32 __reserved_2[3]; |
| 407 | } timer_dcr; |
| 408 | |
| 409 | /*3F0*/ struct { u32 __reserved[4]; } __reserved_20; |
| 410 | |
| 411 | } __attribute__ ((packed)); |
| 412 | |
| 413 | #undef u32 |
| 414 | |
Jack Steiner | a65d1d6 | 2008-03-28 14:12:08 -0500 | [diff] [blame] | 415 | #ifdef CONFIG_X86_32 |
| 416 | #define BAD_APICID 0xFFu |
| 417 | #else |
| 418 | #define BAD_APICID 0xFFFFu |
| 419 | #endif |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 420 | #endif /* _ASM_X86_APICDEF_H */ |