blob: 589e937ed1ebedfd4e7802ff68316fad0255cc9e [file] [log] [blame]
Michael Henneriche6c91b62008-04-25 04:58:29 +08001/*
2 * asm-blackfin/time.h:
3 *
4 * Copyright 2004-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef _ASM_BLACKFIN_TIME_H
10#define _ASM_BLACKFIN_TIME_H
11
12/*
13 * The way that the Blackfin core timer works is:
14 * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
15 * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
16 *
17 * If you take the fastest clock (1ns, or 1GHz to make the math work easier)
18 * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
19 * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
20 * to use TSCALE, and program it to zero (which is pass CCLK through).
21 * If you feel like using it, try to keep HZ * TIMESCALE to some
22 * value that divides easy (like power of 2).
23 */
24
25#ifndef CONFIG_CPU_FREQ
26#define TIME_SCALE 1
Vitja Makarov1bfb4b22008-05-07 11:41:26 +080027#define __bfin_cycles_off (0)
28#define __bfin_cycles_mod (0)
Michael Henneriche6c91b62008-04-25 04:58:29 +080029#else
30/*
31 * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
32 * Whenever we change the Core Clock frequency changes we immediately
33 * adjust the Core Timer Presale Register. This way we don't lose time.
34 */
35#define TIME_SCALE 4
Vitja Makarov1bfb4b22008-05-07 11:41:26 +080036extern unsigned long long __bfin_cycles_off;
37extern unsigned int __bfin_cycles_mod;
Michael Henneriche6c91b62008-04-25 04:58:29 +080038#endif
39
Graf Yang1fa9be72009-05-15 11:01:59 +000040extern void __init setup_core_timer(void);
Michael Henneriche6c91b62008-04-25 04:58:29 +080041#endif