| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ESS Technology allegro audio driver. |
| 3 | * |
| 4 | * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | * |
| 20 | * Hacked for the maestro3 driver by zab |
| 21 | */ |
| 22 | |
| 23 | // Allegro PCI configuration registers |
| 24 | #define PCI_LEGACY_AUDIO_CTRL 0x40 |
| 25 | #define SOUND_BLASTER_ENABLE 0x00000001 |
| 26 | #define FM_SYNTHESIS_ENABLE 0x00000002 |
| 27 | #define GAME_PORT_ENABLE 0x00000004 |
| 28 | #define MPU401_IO_ENABLE 0x00000008 |
| 29 | #define MPU401_IRQ_ENABLE 0x00000010 |
| 30 | #define ALIAS_10BIT_IO 0x00000020 |
| 31 | #define SB_DMA_MASK 0x000000C0 |
| 32 | #define SB_DMA_0 0x00000040 |
| 33 | #define SB_DMA_1 0x00000040 |
| 34 | #define SB_DMA_R 0x00000080 |
| 35 | #define SB_DMA_3 0x000000C0 |
| 36 | #define SB_IRQ_MASK 0x00000700 |
| 37 | #define SB_IRQ_5 0x00000000 |
| 38 | #define SB_IRQ_7 0x00000100 |
| 39 | #define SB_IRQ_9 0x00000200 |
| 40 | #define SB_IRQ_10 0x00000300 |
| 41 | #define MIDI_IRQ_MASK 0x00003800 |
| 42 | #define SERIAL_IRQ_ENABLE 0x00004000 |
| 43 | #define DISABLE_LEGACY 0x00008000 |
| 44 | |
| 45 | #define PCI_ALLEGRO_CONFIG 0x50 |
| 46 | #define SB_ADDR_240 0x00000004 |
| 47 | #define MPU_ADDR_MASK 0x00000018 |
| 48 | #define MPU_ADDR_330 0x00000000 |
| 49 | #define MPU_ADDR_300 0x00000008 |
| 50 | #define MPU_ADDR_320 0x00000010 |
| 51 | #define MPU_ADDR_340 0x00000018 |
| 52 | #define USE_PCI_TIMING 0x00000040 |
| 53 | #define POSTED_WRITE_ENABLE 0x00000080 |
| 54 | #define DMA_POLICY_MASK 0x00000700 |
| 55 | #define DMA_DDMA 0x00000000 |
| 56 | #define DMA_TDMA 0x00000100 |
| 57 | #define DMA_PCPCI 0x00000200 |
| 58 | #define DMA_WBDMA16 0x00000400 |
| 59 | #define DMA_WBDMA4 0x00000500 |
| 60 | #define DMA_WBDMA2 0x00000600 |
| 61 | #define DMA_WBDMA1 0x00000700 |
| 62 | #define DMA_SAFE_GUARD 0x00000800 |
| 63 | #define HI_PERF_GP_ENABLE 0x00001000 |
| 64 | #define PIC_SNOOP_MODE_0 0x00002000 |
| 65 | #define PIC_SNOOP_MODE_1 0x00004000 |
| 66 | #define SOUNDBLASTER_IRQ_MASK 0x00008000 |
| 67 | #define RING_IN_ENABLE 0x00010000 |
| 68 | #define SPDIF_TEST_MODE 0x00020000 |
| 69 | #define CLK_MULT_MODE_SELECT_2 0x00040000 |
| 70 | #define EEPROM_WRITE_ENABLE 0x00080000 |
| 71 | #define CODEC_DIR_IN 0x00100000 |
| 72 | #define HV_BUTTON_FROM_GD 0x00200000 |
| 73 | #define REDUCED_DEBOUNCE 0x00400000 |
| 74 | #define HV_CTRL_ENABLE 0x00800000 |
| 75 | #define SPDIF_ENABLE 0x01000000 |
| 76 | #define CLK_DIV_SELECT 0x06000000 |
| 77 | #define CLK_DIV_BY_48 0x00000000 |
| 78 | #define CLK_DIV_BY_49 0x02000000 |
| 79 | #define CLK_DIV_BY_50 0x04000000 |
| 80 | #define CLK_DIV_RESERVED 0x06000000 |
| 81 | #define PM_CTRL_ENABLE 0x08000000 |
| 82 | #define CLK_MULT_MODE_SELECT 0x30000000 |
| 83 | #define CLK_MULT_MODE_SHIFT 28 |
| 84 | #define CLK_MULT_MODE_0 0x00000000 |
| 85 | #define CLK_MULT_MODE_1 0x10000000 |
| 86 | #define CLK_MULT_MODE_2 0x20000000 |
| 87 | #define CLK_MULT_MODE_3 0x30000000 |
| 88 | #define INT_CLK_SELECT 0x40000000 |
| 89 | #define INT_CLK_MULT_RESET 0x80000000 |
| 90 | |
| 91 | // M3 |
| 92 | #define INT_CLK_SRC_NOT_PCI 0x00100000 |
| 93 | #define INT_CLK_MULT_ENABLE 0x80000000 |
| 94 | |
| 95 | #define PCI_ACPI_CONTROL 0x54 |
| 96 | #define PCI_ACPI_D0 0x00000000 |
| 97 | #define PCI_ACPI_D1 0xB4F70000 |
| 98 | #define PCI_ACPI_D2 0xB4F7B4F7 |
| 99 | |
| 100 | #define PCI_USER_CONFIG 0x58 |
| 101 | #define EXT_PCI_MASTER_ENABLE 0x00000001 |
| 102 | #define SPDIF_OUT_SELECT 0x00000002 |
| 103 | #define TEST_PIN_DIR_CTRL 0x00000004 |
| 104 | #define AC97_CODEC_TEST 0x00000020 |
| 105 | #define TRI_STATE_BUFFER 0x00000080 |
| 106 | #define IN_CLK_12MHZ_SELECT 0x00000100 |
| 107 | #define MULTI_FUNC_DISABLE 0x00000200 |
| 108 | #define EXT_MASTER_PAIR_SEL 0x00000400 |
| 109 | #define PCI_MASTER_SUPPORT 0x00000800 |
| 110 | #define STOP_CLOCK_ENABLE 0x00001000 |
| 111 | #define EAPD_DRIVE_ENABLE 0x00002000 |
| 112 | #define REQ_TRI_STATE_ENABLE 0x00004000 |
| 113 | #define REQ_LOW_ENABLE 0x00008000 |
| 114 | #define MIDI_1_ENABLE 0x00010000 |
| 115 | #define MIDI_2_ENABLE 0x00020000 |
| 116 | #define SB_AUDIO_SYNC 0x00040000 |
| 117 | #define HV_CTRL_TEST 0x00100000 |
| 118 | #define SOUNDBLASTER_TEST 0x00400000 |
| 119 | |
| 120 | #define PCI_USER_CONFIG_C 0x5C |
| 121 | |
| 122 | #define PCI_DDMA_CTRL 0x60 |
| 123 | #define DDMA_ENABLE 0x00000001 |
| 124 | |
| 125 | |
| 126 | // Allegro registers |
| 127 | #define HOST_INT_CTRL 0x18 |
| 128 | #define SB_INT_ENABLE 0x0001 |
| 129 | #define MPU401_INT_ENABLE 0x0002 |
| 130 | #define ASSP_INT_ENABLE 0x0010 |
| 131 | #define RING_INT_ENABLE 0x0020 |
| 132 | #define HV_INT_ENABLE 0x0040 |
| 133 | #define CLKRUN_GEN_ENABLE 0x0100 |
| 134 | #define HV_CTRL_TO_PME 0x0400 |
| 135 | #define SOFTWARE_RESET_ENABLE 0x8000 |
| 136 | |
| 137 | /* |
| 138 | * should be using the above defines, probably. |
| 139 | */ |
| 140 | #define REGB_ENABLE_RESET 0x01 |
| 141 | #define REGB_STOP_CLOCK 0x10 |
| 142 | |
| 143 | #define HOST_INT_STATUS 0x1A |
| 144 | #define SB_INT_PENDING 0x01 |
| 145 | #define MPU401_INT_PENDING 0x02 |
| 146 | #define ASSP_INT_PENDING 0x10 |
| 147 | #define RING_INT_PENDING 0x20 |
| 148 | #define HV_INT_PENDING 0x40 |
| 149 | |
| 150 | #define HARDWARE_VOL_CTRL 0x1B |
| 151 | #define SHADOW_MIX_REG_VOICE 0x1C |
| 152 | #define HW_VOL_COUNTER_VOICE 0x1D |
| 153 | #define SHADOW_MIX_REG_MASTER 0x1E |
| 154 | #define HW_VOL_COUNTER_MASTER 0x1F |
| 155 | |
| 156 | #define CODEC_COMMAND 0x30 |
| 157 | #define CODEC_READ_B 0x80 |
| 158 | |
| 159 | #define CODEC_STATUS 0x30 |
| 160 | #define CODEC_BUSY_B 0x01 |
| 161 | |
| 162 | #define CODEC_DATA 0x32 |
| 163 | |
| 164 | #define RING_BUS_CTRL_A 0x36 |
| 165 | #define RAC_PME_ENABLE 0x0100 |
| 166 | #define RAC_SDFS_ENABLE 0x0200 |
| 167 | #define LAC_PME_ENABLE 0x0400 |
| 168 | #define LAC_SDFS_ENABLE 0x0800 |
| 169 | #define SERIAL_AC_LINK_ENABLE 0x1000 |
| 170 | #define IO_SRAM_ENABLE 0x2000 |
| 171 | #define IIS_INPUT_ENABLE 0x8000 |
| 172 | |
| 173 | #define RING_BUS_CTRL_B 0x38 |
| 174 | #define SECOND_CODEC_ID_MASK 0x0003 |
| 175 | #define SPDIF_FUNC_ENABLE 0x0010 |
| 176 | #define SECOND_AC_ENABLE 0x0020 |
| 177 | #define SB_MODULE_INTF_ENABLE 0x0040 |
| 178 | #define SSPE_ENABLE 0x0040 |
| 179 | #define M3I_DOCK_ENABLE 0x0080 |
| 180 | |
| 181 | #define SDO_OUT_DEST_CTRL 0x3A |
| 182 | #define COMMAND_ADDR_OUT 0x0003 |
| 183 | #define PCM_LR_OUT_LOCAL 0x0000 |
| 184 | #define PCM_LR_OUT_REMOTE 0x0004 |
| 185 | #define PCM_LR_OUT_MUTE 0x0008 |
| 186 | #define PCM_LR_OUT_BOTH 0x000C |
| 187 | #define LINE1_DAC_OUT_LOCAL 0x0000 |
| 188 | #define LINE1_DAC_OUT_REMOTE 0x0010 |
| 189 | #define LINE1_DAC_OUT_MUTE 0x0020 |
| 190 | #define LINE1_DAC_OUT_BOTH 0x0030 |
| 191 | #define PCM_CLS_OUT_LOCAL 0x0000 |
| 192 | #define PCM_CLS_OUT_REMOTE 0x0040 |
| 193 | #define PCM_CLS_OUT_MUTE 0x0080 |
| 194 | #define PCM_CLS_OUT_BOTH 0x00C0 |
| 195 | #define PCM_RLF_OUT_LOCAL 0x0000 |
| 196 | #define PCM_RLF_OUT_REMOTE 0x0100 |
| 197 | #define PCM_RLF_OUT_MUTE 0x0200 |
| 198 | #define PCM_RLF_OUT_BOTH 0x0300 |
| 199 | #define LINE2_DAC_OUT_LOCAL 0x0000 |
| 200 | #define LINE2_DAC_OUT_REMOTE 0x0400 |
| 201 | #define LINE2_DAC_OUT_MUTE 0x0800 |
| 202 | #define LINE2_DAC_OUT_BOTH 0x0C00 |
| 203 | #define HANDSET_OUT_LOCAL 0x0000 |
| 204 | #define HANDSET_OUT_REMOTE 0x1000 |
| 205 | #define HANDSET_OUT_MUTE 0x2000 |
| 206 | #define HANDSET_OUT_BOTH 0x3000 |
| 207 | #define IO_CTRL_OUT_LOCAL 0x0000 |
| 208 | #define IO_CTRL_OUT_REMOTE 0x4000 |
| 209 | #define IO_CTRL_OUT_MUTE 0x8000 |
| 210 | #define IO_CTRL_OUT_BOTH 0xC000 |
| 211 | |
| 212 | #define SDO_IN_DEST_CTRL 0x3C |
| 213 | #define STATUS_ADDR_IN 0x0003 |
| 214 | #define PCM_LR_IN_LOCAL 0x0000 |
| 215 | #define PCM_LR_IN_REMOTE 0x0004 |
| 216 | #define PCM_LR_RESERVED 0x0008 |
| 217 | #define PCM_LR_IN_BOTH 0x000C |
| 218 | #define LINE1_ADC_IN_LOCAL 0x0000 |
| 219 | #define LINE1_ADC_IN_REMOTE 0x0010 |
| 220 | #define LINE1_ADC_IN_MUTE 0x0020 |
| 221 | #define MIC_ADC_IN_LOCAL 0x0000 |
| 222 | #define MIC_ADC_IN_REMOTE 0x0040 |
| 223 | #define MIC_ADC_IN_MUTE 0x0080 |
| 224 | #define LINE2_DAC_IN_LOCAL 0x0000 |
| 225 | #define LINE2_DAC_IN_REMOTE 0x0400 |
| 226 | #define LINE2_DAC_IN_MUTE 0x0800 |
| 227 | #define HANDSET_IN_LOCAL 0x0000 |
| 228 | #define HANDSET_IN_REMOTE 0x1000 |
| 229 | #define HANDSET_IN_MUTE 0x2000 |
| 230 | #define IO_STATUS_IN_LOCAL 0x0000 |
| 231 | #define IO_STATUS_IN_REMOTE 0x4000 |
| 232 | |
| 233 | #define SPDIF_IN_CTRL 0x3E |
| 234 | #define SPDIF_IN_ENABLE 0x0001 |
| 235 | |
| 236 | #define GPIO_DATA 0x60 |
| 237 | #define GPIO_DATA_MASK 0x0FFF |
| 238 | #define GPIO_HV_STATUS 0x3000 |
| 239 | #define GPIO_PME_STATUS 0x4000 |
| 240 | |
| 241 | #define GPIO_MASK 0x64 |
| 242 | #define GPIO_DIRECTION 0x68 |
| 243 | #define GPO_PRIMARY_AC97 0x0001 |
| 244 | #define GPI_LINEOUT_SENSE 0x0004 |
| 245 | #define GPO_SECONDARY_AC97 0x0008 |
| 246 | #define GPI_VOL_DOWN 0x0010 |
| 247 | #define GPI_VOL_UP 0x0020 |
| 248 | #define GPI_IIS_CLK 0x0040 |
| 249 | #define GPI_IIS_LRCLK 0x0080 |
| 250 | #define GPI_IIS_DATA 0x0100 |
| 251 | #define GPI_DOCKING_STATUS 0x0100 |
| 252 | #define GPI_HEADPHONE_SENSE 0x0200 |
| 253 | #define GPO_EXT_AMP_SHUTDOWN 0x1000 |
| 254 | |
| 255 | // M3 |
| 256 | #define GPO_M3_EXT_AMP_SHUTDN 0x0002 |
| 257 | |
| 258 | #define ASSP_INDEX_PORT 0x80 |
| 259 | #define ASSP_MEMORY_PORT 0x82 |
| 260 | #define ASSP_DATA_PORT 0x84 |
| 261 | |
| 262 | #define MPU401_DATA_PORT 0x98 |
| 263 | #define MPU401_STATUS_PORT 0x99 |
| 264 | |
| 265 | #define CLK_MULT_DATA_PORT 0x9C |
| 266 | |
| 267 | #define ASSP_CONTROL_A 0xA2 |
| 268 | #define ASSP_0_WS_ENABLE 0x01 |
| 269 | #define ASSP_CTRL_A_RESERVED1 0x02 |
| 270 | #define ASSP_CTRL_A_RESERVED2 0x04 |
| 271 | #define ASSP_CLK_49MHZ_SELECT 0x08 |
| 272 | #define FAST_PLU_ENABLE 0x10 |
| 273 | #define ASSP_CTRL_A_RESERVED3 0x20 |
| 274 | #define DSP_CLK_36MHZ_SELECT 0x40 |
| 275 | |
| 276 | #define ASSP_CONTROL_B 0xA4 |
| 277 | #define RESET_ASSP 0x00 |
| 278 | #define RUN_ASSP 0x01 |
| 279 | #define ENABLE_ASSP_CLOCK 0x00 |
| 280 | #define STOP_ASSP_CLOCK 0x10 |
| 281 | #define RESET_TOGGLE 0x40 |
| 282 | |
| 283 | #define ASSP_CONTROL_C 0xA6 |
| 284 | #define ASSP_HOST_INT_ENABLE 0x01 |
| 285 | #define FM_ADDR_REMAP_DISABLE 0x02 |
| 286 | #define HOST_WRITE_PORT_ENABLE 0x08 |
| 287 | |
| 288 | #define ASSP_HOST_INT_STATUS 0xAC |
| 289 | #define DSP2HOST_REQ_PIORECORD 0x01 |
| 290 | #define DSP2HOST_REQ_I2SRATE 0x02 |
| 291 | #define DSP2HOST_REQ_TIMER 0x04 |
| 292 | |
| 293 | // AC97 registers |
| 294 | // XXX fix this crap up |
| 295 | /*#define AC97_RESET 0x00*/ |
| 296 | |
| 297 | #define AC97_VOL_MUTE_B 0x8000 |
| 298 | #define AC97_VOL_M 0x1F |
| 299 | #define AC97_LEFT_VOL_S 8 |
| 300 | |
| 301 | #define AC97_MASTER_VOL 0x02 |
| 302 | #define AC97_LINE_LEVEL_VOL 0x04 |
| 303 | #define AC97_MASTER_MONO_VOL 0x06 |
| 304 | #define AC97_PC_BEEP_VOL 0x0A |
| 305 | #define AC97_PC_BEEP_VOL_M 0x0F |
| 306 | #define AC97_SROUND_MASTER_VOL 0x38 |
| 307 | #define AC97_PC_BEEP_VOL_S 1 |
| 308 | |
| 309 | /*#define AC97_PHONE_VOL 0x0C |
| 310 | #define AC97_MIC_VOL 0x0E*/ |
| 311 | #define AC97_MIC_20DB_ENABLE 0x40 |
| 312 | |
| 313 | /*#define AC97_LINEIN_VOL 0x10 |
| 314 | #define AC97_CD_VOL 0x12 |
| 315 | #define AC97_VIDEO_VOL 0x14 |
| 316 | #define AC97_AUX_VOL 0x16*/ |
| 317 | #define AC97_PCM_OUT_VOL 0x18 |
| 318 | /*#define AC97_RECORD_SELECT 0x1A*/ |
| 319 | #define AC97_RECORD_MIC 0x00 |
| 320 | #define AC97_RECORD_CD 0x01 |
| 321 | #define AC97_RECORD_VIDEO 0x02 |
| 322 | #define AC97_RECORD_AUX 0x03 |
| 323 | #define AC97_RECORD_MONO_MUX 0x02 |
| 324 | #define AC97_RECORD_DIGITAL 0x03 |
| 325 | #define AC97_RECORD_LINE 0x04 |
| 326 | #define AC97_RECORD_STEREO 0x05 |
| 327 | #define AC97_RECORD_MONO 0x06 |
| 328 | #define AC97_RECORD_PHONE 0x07 |
| 329 | |
| 330 | /*#define AC97_RECORD_GAIN 0x1C*/ |
| 331 | #define AC97_RECORD_VOL_M 0x0F |
| 332 | |
| 333 | /*#define AC97_GENERAL_PURPOSE 0x20*/ |
| 334 | #define AC97_POWER_DOWN_CTRL 0x26 |
| 335 | #define AC97_ADC_READY 0x0001 |
| 336 | #define AC97_DAC_READY 0x0002 |
| 337 | #define AC97_ANALOG_READY 0x0004 |
| 338 | #define AC97_VREF_ON 0x0008 |
| 339 | #define AC97_PR0 0x0100 |
| 340 | #define AC97_PR1 0x0200 |
| 341 | #define AC97_PR2 0x0400 |
| 342 | #define AC97_PR3 0x0800 |
| 343 | #define AC97_PR4 0x1000 |
| 344 | |
| 345 | #define AC97_RESERVED1 0x28 |
| 346 | |
| 347 | #define AC97_VENDOR_TEST 0x5A |
| 348 | |
| 349 | #define AC97_CLOCK_DELAY 0x5C |
| 350 | #define AC97_LINEOUT_MUX_SEL 0x0001 |
| 351 | #define AC97_MONO_MUX_SEL 0x0002 |
| 352 | #define AC97_CLOCK_DELAY_SEL 0x1F |
| 353 | #define AC97_DAC_CDS_SHIFT 6 |
| 354 | #define AC97_ADC_CDS_SHIFT 11 |
| 355 | |
| 356 | #define AC97_MULTI_CHANNEL_SEL 0x74 |
| 357 | |
| 358 | /*#define AC97_VENDOR_ID1 0x7C |
| 359 | #define AC97_VENDOR_ID2 0x7E*/ |
| 360 | |
| 361 | /* |
| 362 | * ASSP control regs |
| 363 | */ |
| 364 | #define DSP_PORT_TIMER_COUNT 0x06 |
| 365 | |
| 366 | #define DSP_PORT_MEMORY_INDEX 0x80 |
| 367 | |
| 368 | #define DSP_PORT_MEMORY_TYPE 0x82 |
| 369 | #define MEMTYPE_INTERNAL_CODE 0x0002 |
| 370 | #define MEMTYPE_INTERNAL_DATA 0x0003 |
| 371 | #define MEMTYPE_MASK 0x0003 |
| 372 | |
| 373 | #define DSP_PORT_MEMORY_DATA 0x84 |
| 374 | |
| 375 | #define DSP_PORT_CONTROL_REG_A 0xA2 |
| 376 | #define DSP_PORT_CONTROL_REG_B 0xA4 |
| 377 | #define DSP_PORT_CONTROL_REG_C 0xA6 |
| 378 | |
| 379 | #define REV_A_CODE_MEMORY_BEGIN 0x0000 |
| 380 | #define REV_A_CODE_MEMORY_END 0x0FFF |
| 381 | #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 |
| 382 | #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) |
| 383 | |
| 384 | #define REV_B_CODE_MEMORY_BEGIN 0x0000 |
| 385 | #define REV_B_CODE_MEMORY_END 0x0BFF |
| 386 | #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 |
| 387 | #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) |
| 388 | |
| 389 | #define REV_A_DATA_MEMORY_BEGIN 0x1000 |
| 390 | #define REV_A_DATA_MEMORY_END 0x2FFF |
| 391 | #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 |
| 392 | #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) |
| 393 | |
| 394 | #define REV_B_DATA_MEMORY_BEGIN 0x1000 |
| 395 | #define REV_B_DATA_MEMORY_END 0x2BFF |
| 396 | #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 |
| 397 | #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) |
| 398 | |
| 399 | |
| 400 | #define NUM_UNITS_KERNEL_CODE 16 |
| 401 | #define NUM_UNITS_KERNEL_DATA 2 |
| 402 | |
| 403 | #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 |
| 404 | #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 |
| 405 | |
| 406 | /* |
| 407 | * Kernel data layout |
| 408 | */ |
| 409 | |
| 410 | #define DP_SHIFT_COUNT 7 |
| 411 | |
| 412 | #define KDATA_BASE_ADDR 0x1000 |
| 413 | #define KDATA_BASE_ADDR2 0x1080 |
| 414 | |
| 415 | #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) |
| 416 | #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) |
| 417 | #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) |
| 418 | #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) |
| 419 | #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) |
| 420 | #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) |
| 421 | #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) |
| 422 | #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) |
| 423 | #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) |
| 424 | |
| 425 | #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) |
| 426 | #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) |
| 427 | |
| 428 | #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) |
| 429 | #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) |
| 430 | #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) |
| 431 | #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) |
| 432 | #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) |
| 433 | #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) |
| 434 | #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) |
| 435 | #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) |
| 436 | #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) |
| 437 | #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) |
| 438 | |
| 439 | #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) |
| 440 | #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) |
| 441 | |
| 442 | #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) |
| 443 | #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) |
| 444 | |
| 445 | #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) |
| 446 | #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) |
| 447 | |
| 448 | #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) |
| 449 | #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) |
| 450 | #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) |
| 451 | |
| 452 | #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) |
| 453 | #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) |
| 454 | #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) |
| 455 | #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) |
| 456 | #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) |
| 457 | |
| 458 | #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) |
| 459 | #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) |
| 460 | #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) |
| 461 | |
| 462 | #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) |
| 463 | #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) |
| 464 | #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) |
| 465 | |
| 466 | #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) |
| 467 | #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) |
| 468 | #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) |
| 469 | #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) |
| 470 | #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) |
| 471 | #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) |
| 472 | #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) |
| 473 | #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) |
| 474 | #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) |
| 475 | #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) |
| 476 | |
| 477 | #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) |
| 478 | #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) |
| 479 | #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) |
| 480 | |
| 481 | #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) |
| 482 | #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) |
| 483 | |
| 484 | #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) |
| 485 | #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) |
| 486 | #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) |
| 487 | |
| 488 | #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) |
| 489 | #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) |
| 490 | #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) |
| 491 | #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) |
| 492 | #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) |
| 493 | #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) |
| 494 | |
| 495 | #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) |
| 496 | #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) |
| 497 | #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) |
| 498 | #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) |
| 499 | #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) |
| 500 | #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) |
| 501 | |
| 502 | #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) |
| 503 | #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) |
| 504 | #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) |
| 505 | #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) |
| 506 | #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) |
| 507 | #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) |
| 508 | |
| 509 | #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) |
| 510 | #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) |
| 511 | #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) |
| 512 | #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) |
| 513 | |
| 514 | #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) |
| 515 | #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) |
| 516 | |
| 517 | #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) |
| 518 | #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) |
| 519 | |
| 520 | #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) |
| 521 | #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) |
| 522 | #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) |
| 523 | #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) |
| 524 | #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) |
| 525 | |
| 526 | #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) |
| 527 | #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) |
| 528 | |
| 529 | #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) |
| 530 | #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) |
| 531 | #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) |
| 532 | |
| 533 | #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) |
| 534 | #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) |
| 535 | |
| 536 | #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) |
| 537 | |
| 538 | #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) |
| 539 | #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) |
| 540 | #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) |
| 541 | #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) |
| 542 | #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) |
| 543 | #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) |
| 544 | #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) |
| 545 | #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) |
| 546 | #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) |
| 547 | #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) |
| 548 | #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) |
| 549 | #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) |
| 550 | |
| 551 | #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) |
| 552 | #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) |
| 553 | #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) |
| 554 | #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) |
| 555 | |
| 556 | #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) |
| 557 | #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) |
| 558 | |
| 559 | #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) |
| 560 | #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) |
| 561 | #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) |
| 562 | #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) |
| 563 | |
| 564 | #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) |
| 565 | #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) |
| 566 | #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) |
| 567 | #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) |
| 568 | #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) |
| 569 | |
| 570 | /* |
| 571 | * second 'segment' (?) reserved for mixer |
| 572 | * buffers.. |
| 573 | */ |
| 574 | |
| 575 | #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) |
| 576 | #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) |
| 577 | #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) |
| 578 | #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) |
| 579 | #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) |
| 580 | #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) |
| 581 | #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) |
| 582 | #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) |
| 583 | #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) |
| 584 | #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) |
| 585 | #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) |
| 586 | #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) |
| 587 | #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) |
| 588 | #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) |
| 589 | #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) |
| 590 | #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) |
| 591 | |
| 592 | #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) |
| 593 | #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) |
| 594 | #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) |
| 595 | #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) |
| 596 | #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) |
| 597 | #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) |
| 598 | #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) |
| 599 | #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) |
| 600 | #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) |
| 601 | #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) |
| 602 | #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) |
| 603 | |
| 604 | #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) |
| 605 | #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) |
| 606 | #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) |
| 607 | #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) |
| 608 | #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) |
| 609 | #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) |
| 610 | |
| 611 | #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC) |
| 612 | #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0) |
| 613 | #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0) |
| 614 | #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0) |
| 615 | |
| 616 | /* |
| 617 | * client data area offsets |
| 618 | */ |
| 619 | #define CDATA_INSTANCE_READY 0x00 |
| 620 | |
| 621 | #define CDATA_HOST_SRC_ADDRL 0x01 |
| 622 | #define CDATA_HOST_SRC_ADDRH 0x02 |
| 623 | #define CDATA_HOST_SRC_END_PLUS_1L 0x03 |
| 624 | #define CDATA_HOST_SRC_END_PLUS_1H 0x04 |
| 625 | #define CDATA_HOST_SRC_CURRENTL 0x05 |
| 626 | #define CDATA_HOST_SRC_CURRENTH 0x06 |
| 627 | |
| 628 | #define CDATA_IN_BUF_CONNECT 0x07 |
| 629 | #define CDATA_OUT_BUF_CONNECT 0x08 |
| 630 | |
| 631 | #define CDATA_IN_BUF_BEGIN 0x09 |
| 632 | #define CDATA_IN_BUF_END_PLUS_1 0x0A |
| 633 | #define CDATA_IN_BUF_HEAD 0x0B |
| 634 | #define CDATA_IN_BUF_TAIL 0x0C |
| 635 | #define CDATA_OUT_BUF_BEGIN 0x0D |
| 636 | #define CDATA_OUT_BUF_END_PLUS_1 0x0E |
| 637 | #define CDATA_OUT_BUF_HEAD 0x0F |
| 638 | #define CDATA_OUT_BUF_TAIL 0x10 |
| 639 | |
| 640 | #define CDATA_DMA_CONTROL 0x11 |
| 641 | #define CDATA_RESERVED 0x12 |
| 642 | |
| 643 | #define CDATA_FREQUENCY 0x13 |
| 644 | #define CDATA_LEFT_VOLUME 0x14 |
| 645 | #define CDATA_RIGHT_VOLUME 0x15 |
| 646 | #define CDATA_LEFT_SUR_VOL 0x16 |
| 647 | #define CDATA_RIGHT_SUR_VOL 0x17 |
| 648 | |
| 649 | #define CDATA_HEADER_LEN 0x18 |
| 650 | |
| 651 | #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN |
| 652 | #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1) |
| 653 | #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2) |
| 654 | #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3) |
| 655 | #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8) |
| 656 | #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10) |
| 657 | #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16) |
| 658 | #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17) |
| 659 | |
| 660 | #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) |
| 661 | #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) |
| 662 | #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) |
| 663 | #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) |
| 664 | #define MINISRC_BIQUAD_STAGE 2 |
| 665 | #define MINISRC_COEF_LOC 0X175 |
| 666 | |
| 667 | #define DMACONTROL_BLOCK_MASK 0x000F |
| 668 | #define DMAC_BLOCK0_SELECTOR 0x0000 |
| 669 | #define DMAC_BLOCK1_SELECTOR 0x0001 |
| 670 | #define DMAC_BLOCK2_SELECTOR 0x0002 |
| 671 | #define DMAC_BLOCK3_SELECTOR 0x0003 |
| 672 | #define DMAC_BLOCK4_SELECTOR 0x0004 |
| 673 | #define DMAC_BLOCK5_SELECTOR 0x0005 |
| 674 | #define DMAC_BLOCK6_SELECTOR 0x0006 |
| 675 | #define DMAC_BLOCK7_SELECTOR 0x0007 |
| 676 | #define DMAC_BLOCK8_SELECTOR 0x0008 |
| 677 | #define DMAC_BLOCK9_SELECTOR 0x0009 |
| 678 | #define DMAC_BLOCKA_SELECTOR 0x000A |
| 679 | #define DMAC_BLOCKB_SELECTOR 0x000B |
| 680 | #define DMAC_BLOCKC_SELECTOR 0x000C |
| 681 | #define DMAC_BLOCKD_SELECTOR 0x000D |
| 682 | #define DMAC_BLOCKE_SELECTOR 0x000E |
| 683 | #define DMAC_BLOCKF_SELECTOR 0x000F |
| 684 | #define DMACONTROL_PAGE_MASK 0x00F0 |
| 685 | #define DMAC_PAGE0_SELECTOR 0x0030 |
| 686 | #define DMAC_PAGE1_SELECTOR 0x0020 |
| 687 | #define DMAC_PAGE2_SELECTOR 0x0010 |
| 688 | #define DMAC_PAGE3_SELECTOR 0x0000 |
| 689 | #define DMACONTROL_AUTOREPEAT 0x1000 |
| 690 | #define DMACONTROL_STOPPED 0x2000 |
| 691 | #define DMACONTROL_DIRECTION 0x0100 |
| 692 | |
| 693 | |
| 694 | /* |
| 695 | * DSP Code images |
| 696 | */ |
| 697 | |
| 698 | static u16 assp_kernel_image[] = { |
| 699 | 0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4, |
| 700 | 0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, |
| 701 | 0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, |
| 702 | 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4, |
| 703 | 0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08, |
| 704 | 0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909, |
| 705 | 0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41, |
| 706 | 0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308, |
| 707 | 0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910, |
| 708 | 0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00, |
| 709 | 0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026, |
| 710 | 0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0, |
| 711 | 0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012, |
| 712 | 0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A, |
| 713 | 0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000, |
| 714 | 0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05, |
| 715 | 0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26, |
| 716 | 0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300, |
| 717 | 0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88, |
| 718 | 0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008, |
| 719 | 0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80, |
| 720 | 0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71, |
| 721 | 0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A, |
| 722 | 0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100, |
| 723 | 0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900, |
| 724 | 0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903, |
| 725 | 0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309, |
| 726 | 0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B, |
| 727 | 0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540, |
| 728 | 0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C, |
| 729 | 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380, |
| 730 | 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340, |
| 731 | 0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041, |
| 732 | 0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18, |
| 733 | 0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, |
| 734 | 0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9, |
| 735 | 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8, |
| 736 | 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A, |
| 737 | 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80, |
| 738 | 0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, |
| 739 | 0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80, |
| 740 | 0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A, |
| 741 | 0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F, |
| 742 | 0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1, |
| 743 | 0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034, |
| 744 | 0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E, |
| 745 | 0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977, |
| 746 | 0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B, |
| 747 | 0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388, |
| 748 | 0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, |
| 749 | 0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473, |
| 750 | 0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473, |
| 751 | 0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880, |
| 752 | 0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80, |
| 753 | 0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6, |
| 754 | 0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909, |
| 755 | 0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED, |
| 756 | 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005, |
| 757 | 0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, |
| 758 | 0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4, |
| 759 | 0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, |
| 760 | 0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10, |
| 761 | 0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070, |
| 762 | 0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71, |
| 763 | 0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A, |
| 764 | 0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061, |
| 765 | 0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A, |
| 766 | 0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6, |
| 767 | 0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A, |
| 768 | 0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6, |
| 769 | 0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358, |
| 770 | 0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6, |
| 771 | 0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9, |
| 772 | 0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379, |
| 773 | 0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6, |
| 774 | 0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C, |
| 775 | 0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166, |
| 776 | 0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B, |
| 777 | 0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A, |
| 778 | 0xBE3A, |
| 779 | }; |
| 780 | |
| 781 | /* |
| 782 | * Mini sample rate converter code image |
| 783 | * that is to be loaded at 0x400 on the DSP. |
| 784 | */ |
| 785 | static u16 assp_minisrc_image[] = { |
| 786 | |
| 787 | 0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412, |
| 788 | 0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41, |
| 789 | 0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907, |
| 790 | 0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01, |
| 791 | 0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904, |
| 792 | 0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D, |
| 793 | 0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD, |
| 794 | 0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22, |
| 795 | 0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0, |
| 796 | 0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9, |
| 797 | 0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89, |
| 798 | 0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0, |
| 799 | 0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484, |
| 800 | 0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80, |
| 801 | 0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624, |
| 802 | 0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4, |
| 803 | 0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027, |
| 804 | 0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903, |
| 805 | 0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809, |
| 806 | 0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46, |
| 807 | 0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47, |
| 808 | 0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0, |
| 809 | 0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516, |
| 810 | 0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E, |
| 811 | 0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C, |
| 812 | 0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180, |
| 813 | 0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E, |
| 814 | 0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0, |
| 815 | 0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0, |
| 816 | 0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0, |
| 817 | 0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F, |
| 818 | 0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
| 819 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
| 820 | }; |
| 821 | |