| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-spear3xx/include/mach/spear.h |
| 3 | * |
| 4 | * SPEAr3xx Machine family specific definition |
| 5 | * |
| 6 | * Copyright (C) 2009 ST Microelectronics |
| 7 | * Viresh Kumar<viresh.kumar@st.com> |
| 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
| 14 | #ifndef __MACH_SPEAR3XX_H |
| 15 | #define __MACH_SPEAR3XX_H |
| 16 | |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 17 | #include <asm/memory.h> |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 18 | #include <mach/spear300.h> |
| 19 | #include <mach/spear310.h> |
| 20 | #include <mach/spear320.h> |
| 21 | |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 22 | #define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 23 | |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 24 | #define SPEAR3XX_ICM9_BASE UL(0xC0000000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 25 | |
| 26 | /* ICM1 - Low speed connection */ |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 27 | #define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) |
| 28 | #define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 29 | #define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 30 | #define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) |
| 31 | #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) |
| 32 | #define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) |
| 33 | #define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000) |
| 34 | #define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000) |
| 35 | #define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 36 | |
| 37 | /* ICM2 - Application Subsystem */ |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 38 | #define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000) |
| 39 | #define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 40 | |
| 41 | /* ICM4 - High Speed Connection */ |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 42 | #define SPEAR3XX_ICM4_BASE UL(0xE0000000) |
| 43 | #define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000) |
| 44 | #define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) |
| 45 | #define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000) |
| 46 | #define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) |
| 47 | #define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000) |
| 48 | #define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) |
| 49 | #define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) |
| 50 | #define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 51 | |
| 52 | /* ML1 - Multi Layer CPU Subsystem */ |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 53 | #define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) |
| 54 | #define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) |
| 55 | #define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 56 | #define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 57 | |
| 58 | /* ICM3 - Basic Subsystem */ |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 59 | #define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) |
| 60 | #define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) |
| 61 | #define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) |
| 62 | #define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) |
| 63 | #define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) |
| 64 | #define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000) |
| 65 | #define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) |
| 66 | #define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) |
| 67 | #define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 68 | #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 69 | #define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 70 | #define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) |
| Shiraz Hashim | 981a95d3 | 2011-03-07 05:57:08 +0100 | [diff] [blame] | 71 | #define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) |
| viresh kumar | a7e9c45 | 2010-04-01 12:30:19 +0100 | [diff] [blame] | 72 | |
| 73 | /* Debug uart for linux, will be used for debug and uncompress messages */ |
| 74 | #define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE |
| 75 | #define VA_SPEAR_DBG_UART_BASE VA_SPEAR3XX_ICM1_UART_BASE |
| 76 | |
| 77 | /* Sysctl base for spear platform */ |
| 78 | #define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE |
| 79 | #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE |
| 80 | |
| 81 | #endif /* __MACH_SPEAR3XX_H */ |