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Srinivas Kandagatla65ebcc12013-06-25 12:15:10 +01001/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
Gabriel FERNANDEZf317e682014-05-20 15:22:00 +02008
9#include <dt-bindings/clock/stih415-clks.h>
10
Srinivas Kandagatla65ebcc12013-06-25 12:15:10 +010011/ {
12 clocks {
Gabriel FERNANDEZf317e682014-05-20 15:22:00 +020013 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges;
16
Srinivas Kandagatla65ebcc12013-06-25 12:15:10 +010017 /*
18 * Fixed 30MHz oscillator input to SoC
19 */
Gabriel FERNANDEZed3593f2014-05-20 15:22:00 +020020 clk_sysin: clk-sysin {
Srinivas Kandagatla65ebcc12013-06-25 12:15:10 +010021 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 };
25
26 /*
Gabriel FERNANDEZf317e682014-05-20 15:22:00 +020027 * ClockGenAs on SASG1
28 */
29 clockgen-a@fee62000 {
30 reg = <0xfee62000 0xb48>;
31
32 clk_s_a0_pll: clk-s-a0-pll {
33 #clock-cells = <1>;
34 compatible = "st,clkgena-plls-c65";
35
36 clocks = <&clk_sysin>;
37
38 clock-output-names = "clk-s-a0-pll0-hs",
39 "clk-s-a0-pll0-ls",
40 "clk-s-a0-pll1";
41 };
42
43 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
44 #clock-cells = <0>;
45 compatible = "st,clkgena-prediv-c65",
46 "st,clkgena-prediv";
47
48 clocks = <&clk_sysin>;
49
50 clock-output-names = "clk-s-a0-osc-prediv";
51 };
52
53 clk_s_a0_hs: clk-s-a0-hs {
54 #clock-cells = <1>;
55 compatible = "st,clkgena-divmux-c65-hs",
56 "st,clkgena-divmux";
57
58 clocks = <&clk_s_a0_osc_prediv>,
59 <&clk_s_a0_pll 0>, /* PLL0 HS */
60 <&clk_s_a0_pll 2>; /* PLL1 */
61
62 clock-output-names = "clk-s-fdma-0",
63 "clk-s-fdma-1",
64 ""; /* clk-s-jit-sense */
65 /* Fourth output unused */
66 };
67
68 clk_s_a0_ls: clk-s-a0-ls {
69 #clock-cells = <1>;
70 compatible = "st,clkgena-divmux-c65-ls",
71 "st,clkgena-divmux";
72
73 clocks = <&clk_s_a0_osc_prediv>,
74 <&clk_s_a0_pll 1>, /* PLL0 LS */
75 <&clk_s_a0_pll 2>; /* PLL1 */
76
77 clock-output-names = "clk-s-icn-reg-0",
78 "clk-s-icn-if-0",
79 "clk-s-icn-reg-lp-0",
80 "clk-s-emiss",
81 "clk-s-eth1-phy",
82 "clk-s-mii-ref-out";
83 /* Remaining outputs unused */
84 };
85 };
86
87 clockgen-a@fee81000 {
88 reg = <0xfee81000 0xb48>;
89
90 clk_s_a1_pll: clk-s-a1-pll {
91 #clock-cells = <1>;
92 compatible = "st,clkgena-plls-c65";
93
94 clocks = <&clk_sysin>;
95
96 clock-output-names = "clk-s-a1-pll0-hs",
97 "clk-s-a1-pll0-ls",
98 "clk-s-a1-pll1";
99 };
100
101 clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
102 #clock-cells = <0>;
103 compatible = "st,clkgena-prediv-c65",
104 "st,clkgena-prediv";
105
106 clocks = <&clk_sysin>;
107
108 clock-output-names = "clk-s-a1-osc-prediv";
109 };
110
111 clk_s_a1_hs: clk-s-a1-hs {
112 #clock-cells = <1>;
113 compatible = "st,clkgena-divmux-c65-hs",
114 "st,clkgena-divmux";
115
116 clocks = <&clk_s_a1_osc_prediv>,
117 <&clk_s_a1_pll 0>, /* PLL0 HS */
118 <&clk_s_a1_pll 2>; /* PLL1 */
119
120 clock-output-names = "", /* Reserved */
121 "", /* Reserved */
122 "clk-s-stac-phy",
123 "clk-s-vtac-tx-phy";
124 };
125
126 clk_s_a1_ls: clk-s-a1-ls {
127 #clock-cells = <1>;
128 compatible = "st,clkgena-divmux-c65-ls",
129 "st,clkgena-divmux";
130
131 clocks = <&clk_s_a1_osc_prediv>,
132 <&clk_s_a1_pll 1>, /* PLL0 LS */
133 <&clk_s_a1_pll 2>; /* PLL1 */
134
135 clock-output-names = "clk-s-icn-if-2",
136 "clk-s-card-mmc",
137 "clk-s-icn-if-1",
138 "clk-s-gmac0-phy",
139 "clk-s-nand-ctrl",
140 "", /* Reserved */
141 "clk-s-mii0-ref-out",
142 ""; /* clk-s-stac-sys */
143 /* Remaining outputs unused */
144 };
145 };
146
147 /*
148 * ClockGenAs on MPE41
149 */
150 clockgen-a@fde12000 {
151 reg = <0xfde12000 0xb50>;
152
153 clk_m_a0_pll0: clk-m-a0-pll0 {
154 #clock-cells = <1>;
155 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
156
157 clocks = <&clk_sysin>;
158
159 clock-output-names = "clk-m-a0-pll0-phi0",
160 "clk-m-a0-pll0-phi1",
161 "clk-m-a0-pll0-phi2",
162 "clk-m-a0-pll0-phi3";
163 };
164
165 clk_m_a0_pll1: clk-m-a0-pll1 {
166 #clock-cells = <1>;
167 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
168
169 clocks = <&clk_sysin>;
170
171 clock-output-names = "clk-m-a0-pll1-phi0",
172 "clk-m-a0-pll1-phi1",
173 "clk-m-a0-pll1-phi2",
174 "clk-m-a0-pll1-phi3";
175 };
176
177 clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
178 #clock-cells = <0>;
179 compatible = "st,clkgena-prediv-c32",
180 "st,clkgena-prediv";
181
182 clocks = <&clk_sysin>;
183
184 clock-output-names = "clk-m-a0-osc-prediv";
185 };
186
187 clk_m_a0_div0: clk-m-a0-div0 {
188 #clock-cells = <1>;
189 compatible = "st,clkgena-divmux-c32-odf0",
190 "st,clkgena-divmux";
191
192 clocks = <&clk_m_a0_osc_prediv>,
193 <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
194 <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
195
196 clock-output-names = "clk-m-apb-pm", /* Unused */
197 "", /* Unused */
198 "", /* Unused */
199 "", /* Unused */
200 "clk-m-pp-dmu-0",
201 "clk-m-pp-dmu-1",
202 "clk-m-icm-disp",
203 ""; /* Unused */
204 };
205
206 clk_m_a0_div1: clk-m-a0-div1 {
207 #clock-cells = <1>;
208 compatible = "st,clkgena-divmux-c32-odf1",
209 "st,clkgena-divmux";
210
211 clocks = <&clk_m_a0_osc_prediv>,
212 <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
213 <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
214
215 clock-output-names = "", /* Unused */
216 "", /* Unused */
217 "clk-m-a9-ext2f",
218 "clk-m-st40rt",
219 "clk-m-st231-dmu-0",
220 "clk-m-st231-dmu-1",
221 "clk-m-st231-aud",
222 "clk-m-st231-gp-0";
223 };
224
225 clk_m_a0_div2: clk-m-a0-div2 {
226 #clock-cells = <1>;
227 compatible = "st,clkgena-divmux-c32-odf2",
228 "st,clkgena-divmux";
229
230 clocks = <&clk_m_a0_osc_prediv>,
231 <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
232 <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
233
234 clock-output-names = "clk-m-st231-gp-1",
235 "clk-m-icn-cpu",
236 "clk-m-icn-stac",
237 "clk-m-icn-dmu-0",
238 "clk-m-icn-dmu-1",
239 "", /* Unused */
240 "", /* Unused */
241 ""; /* Unused */
242 };
243
244 clk_m_a0_div3: clk-m-a0-div3 {
245 #clock-cells = <1>;
246 compatible = "st,clkgena-divmux-c32-odf3",
247 "st,clkgena-divmux";
248
249 clocks = <&clk_m_a0_osc_prediv>,
250 <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
251 <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
252
253 clock-output-names = "", /* Unused */
254 "", /* Unused */
255 "", /* Unused */
256 "", /* Unused */
257 "", /* Unused */
258 "", /* Unused */
259 "clk-m-icn-eram",
260 "clk-m-a9-trace";
261 };
262 };
263
264 clockgen-a@fd6db000 {
265 reg = <0xfd6db000 0xb50>;
266
267 clk_m_a1_pll0: clk-m-a1-pll0 {
268 #clock-cells = <1>;
269 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
270
271 clocks = <&clk_sysin>;
272
273 clock-output-names = "clk-m-a1-pll0-phi0",
274 "clk-m-a1-pll0-phi1",
275 "clk-m-a1-pll0-phi2",
276 "clk-m-a1-pll0-phi3";
277 };
278
279 clk_m_a1_pll1: clk-m-a1-pll1 {
280 #clock-cells = <1>;
281 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
282
283 clocks = <&clk_sysin>;
284
285 clock-output-names = "clk-m-a1-pll1-phi0",
286 "clk-m-a1-pll1-phi1",
287 "clk-m-a1-pll1-phi2",
288 "clk-m-a1-pll1-phi3";
289 };
290
291 clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
292 #clock-cells = <0>;
293 compatible = "st,clkgena-prediv-c32",
294 "st,clkgena-prediv";
295
296 clocks = <&clk_sysin>;
297
298 clock-output-names = "clk-m-a1-osc-prediv";
299 };
300
301 clk_m_a1_div0: clk-m-a1-div0 {
302 #clock-cells = <1>;
303 compatible = "st,clkgena-divmux-c32-odf0",
304 "st,clkgena-divmux";
305
306 clocks = <&clk_m_a1_osc_prediv>,
307 <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
308 <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
309
310 clock-output-names = "clk-m-fdma-12",
311 "clk-m-fdma-10",
312 "clk-m-fdma-11",
313 "clk-m-hva-lmi",
314 "clk-m-proc-sc",
315 "clk-m-tp",
316 "clk-m-icn-gpu",
317 "clk-m-icn-vdp-0";
318 };
319
320 clk_m_a1_div1: clk-m-a1-div1 {
321 #clock-cells = <1>;
322 compatible = "st,clkgena-divmux-c32-odf1",
323 "st,clkgena-divmux";
324
325 clocks = <&clk_m_a1_osc_prediv>,
326 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
327 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
328
329 clock-output-names = "clk-m-icn-vdp-1",
330 "clk-m-icn-vdp-2",
331 "clk-m-icn-vdp-3",
332 "clk-m-prv-t1-bus",
333 "clk-m-icn-vdp-4",
334 "clk-m-icn-reg-10",
335 "", /* Unused */
336 ""; /* clk-m-icn-st231 */
337 };
338
339 clk_m_a1_div2: clk-m-a1-div2 {
340 #clock-cells = <1>;
341 compatible = "st,clkgena-divmux-c32-odf2",
342 "st,clkgena-divmux";
343
344 clocks = <&clk_m_a1_osc_prediv>,
345 <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
346 <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
347
348 clock-output-names = "clk-m-fvdp-proc-alt",
349 "", /* Unused */
350 "", /* Unused */
351 "", /* Unused */
352 "", /* Unused */
353 "", /* Unused */
354 "", /* Unused */
355 ""; /* Unused */
356 };
357
358 clk_m_a1_div3: clk-m-a1-div3 {
359 #clock-cells = <1>;
360 compatible = "st,clkgena-divmux-c32-odf3",
361 "st,clkgena-divmux";
362
363 clocks = <&clk_m_a1_osc_prediv>,
364 <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
365 <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
366
367 clock-output-names = "", /* Unused */
368 "", /* Unused */
369 "", /* Unused */
370 "", /* Unused */
371 "", /* Unused */
372 "", /* Unused */
373 "", /* Unused */
374 ""; /* Unused */
375 };
376 };
377
378 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
379 #clock-cells = <0>;
380 compatible = "fixed-factor-clock";
381 clocks = <&clk_m_a0_div1 2>;
382 clock-div = <2>;
383 clock-mult = <1>;
384 };
385
386 clockgen-a@fd345000 {
387 reg = <0xfd345000 0xb50>;
388
389 clk_m_a2_pll0: clk-m-a2-pll0 {
390 #clock-cells = <1>;
391 compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
392
393 clocks = <&clk_sysin>;
394
395 clock-output-names = "clk-m-a2-pll0-phi0",
396 "clk-m-a2-pll0-phi1",
397 "clk-m-a2-pll0-phi2",
398 "clk-m-a2-pll0-phi3";
399 };
400
401 clk_m_a2_pll1: clk-m-a2-pll1 {
402 #clock-cells = <1>;
403 compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
404
405 clocks = <&clk_sysin>;
406
407 clock-output-names = "clk-m-a2-pll1-phi0",
408 "clk-m-a2-pll1-phi1",
409 "clk-m-a2-pll1-phi2",
410 "clk-m-a2-pll1-phi3";
411 };
412
413 clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
414 #clock-cells = <0>;
415 compatible = "st,clkgena-prediv-c32",
416 "st,clkgena-prediv";
417
418 clocks = <&clk_sysin>;
419
420 clock-output-names = "clk-m-a2-osc-prediv";
421 };
422
423 clk_m_a2_div0: clk-m-a2-div0 {
424 #clock-cells = <1>;
425 compatible = "st,clkgena-divmux-c32-odf0",
426 "st,clkgena-divmux";
427
428 clocks = <&clk_m_a2_osc_prediv>,
429 <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
430 <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
431
432 clock-output-names = "clk-m-vtac-main-phy",
433 "clk-m-vtac-aux-phy",
434 "clk-m-stac-phy",
435 "clk-m-stac-sys",
436 "", /* clk-m-mpestac-pg */
437 "", /* clk-m-mpestac-wc */
438 "", /* clk-m-mpevtacaux-pg*/
439 ""; /* clk-m-mpevtacmain-pg*/
440 };
441
442 clk_m_a2_div1: clk-m-a2-div1 {
443 #clock-cells = <1>;
444 compatible = "st,clkgena-divmux-c32-odf1",
445 "st,clkgena-divmux";
446
447 clocks = <&clk_m_a2_osc_prediv>,
448 <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
449 <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
450
451 clock-output-names = "", /* clk-m-mpevtacrx0-wc */
452 "", /* clk-m-mpevtacrx1-wc */
453 "clk-m-compo-main",
454 "clk-m-compo-aux",
455 "clk-m-bdisp-0",
456 "clk-m-bdisp-1",
457 "clk-m-icn-bdisp-0",
458 "clk-m-icn-bdisp-1";
459 };
460
461 clk_m_a2_div2: clk-m-a2-div2 {
462 #clock-cells = <1>;
463 compatible = "st,clkgena-divmux-c32-odf2",
464 "st,clkgena-divmux";
465
466 clocks = <&clk_m_a2_osc_prediv>,
467 <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
468 <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
469
470 clock-output-names = "", /* clk-m-icn-hqvdp0 */
471 "", /* clk-m-icn-hqvdp1 */
472 "clk-m-icn-compo",
473 "", /* clk-m-icn-vdpaux */
474 "clk-m-icn-ts",
475 "clk-m-icn-reg-lp-10",
476 "clk-m-dcephy-impctrl",
477 ""; /* Unused */
478 };
479
480 clk_m_a2_div3: clk-m-a2-div3 {
481 #clock-cells = <1>;
482 compatible = "st,clkgena-divmux-c32-odf3",
483 "st,clkgena-divmux";
484
485 clocks = <&clk_m_a2_osc_prediv>,
486 <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
487 <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
488
489 clock-output-names = ""; /* Unused */
490 /* Remaining outputs unused */
491 };
492 };
Gabriel FERNANDEZ20e40ed2014-05-20 15:22:00 +0200493
494 /*
495 * A9 PLL
496 */
497 clockgen-a9@fdde00d8 {
498 reg = <0xfdde00d8 0x70>;
499
500 clockgen_a9_pll: clockgen-a9-pll {
501 #clock-cells = <1>;
502 compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32";
503
504 clocks = <&clk_sysin>;
505 clock-output-names = "clockgen-a9-pll-odf";
506 };
507 };
508
509 /*
510 * ARM CPU related clocks
511 */
512 clk_m_a9: clk-m-a9@fdde00d8 {
513 #clock-cells = <0>;
514 compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux";
515 reg = <0xfdde00d8 0x4>;
516 clocks = <&clockgen_a9_pll 0>,
517 <&clockgen_a9_pll 0>,
518 <&clk_m_a0_div1 2>,
519 <&clk_m_a9_ext2f_div2>;
520 };
521
522 /*
523 * ARM Peripheral clock for timers
524 */
525 arm_periph_clk: clk-m-a9-periphs {
526 #clock-cells = <0>;
527 compatible = "fixed-factor-clock";
528 clocks = <&clk_m_a9>;
529 clock-div = <2>;
530 clock-mult = <1>;
531 };
Srinivas Kandagatla65ebcc12013-06-25 12:15:10 +0100532 };
533};