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Zhang, Yanmin47402402006-07-31 15:15:18 +08001 The PCI Express Advanced Error Reporting Driver Guide HOWTO
2 T. Long Nguyen <tom.l.nguyen@intel.com>
3 Yanmin Zhang <yanmin.zhang@intel.com>
4 07/29/2006
5
6
71. Overview
8
91.1 About this guide
10
11This guide describes the basics of the PCI Express Advanced Error
12Reporting (AER) driver and provides information on how to use it, as
13well as how to enable the drivers of endpoint devices to conform with
14PCI Express AER driver.
15
Randy Dunlap4b5ff462008-03-10 17:16:32 -0700161.2 Copyright © Intel Corporation 2006.
Zhang, Yanmin47402402006-07-31 15:15:18 +080017
181.3 What is the PCI Express AER Driver?
19
20PCI Express error signaling can occur on the PCI Express link itself
21or on behalf of transactions initiated on the link. PCI Express
22defines two error reporting paradigms: the baseline capability and
23the Advanced Error Reporting capability. The baseline capability is
24required of all PCI Express components providing a minimum defined
25set of error reporting requirements. Advanced Error Reporting
26capability is implemented with a PCI Express advanced error reporting
27extended capability structure providing more robust error reporting.
28
29The PCI Express AER driver provides the infrastructure to support PCI
30Express Advanced Error Reporting capability. The PCI Express AER
31driver provides three basic functions:
32
33- Gathers the comprehensive error information if errors occurred.
34- Reports error to the users.
35- Performs error recovery actions.
36
37AER driver only attaches root ports which support PCI-Express AER
38capability.
39
40
412. User Guide
42
432.1 Include the PCI Express AER Root Driver into the Linux Kernel
44
45The PCI Express AER Root driver is a Root Port service driver attached
46to the PCI Express Port Bus driver. If a user wants to use it, the driver
47has to be compiled. Option CONFIG_PCIEAER supports this capability. It
48depends on CONFIG_PCIEPORTBUS, so pls. set CONFIG_PCIEPORTBUS=y and
49CONFIG_PCIEAER = y.
50
512.2 Load PCI Express AER Root Driver
52There is a case where a system has AER support in BIOS. Enabling the AER
53Root driver and having AER support in BIOS may result unpredictable
54behavior. To avoid this conflict, a successful load of the AER Root driver
55requires ACPI _OSC support in the BIOS to allow the AER Root driver to
56request for native control of AER. See the PCI FW 3.0 Specification for
57details regarding OSC usage. Currently, lots of firmwares don't provide
58_OSC support while they use PCI Express. To support such firmwares,
59forceload, a parameter of type bool, could enable AER to continue to
60be initiated although firmwares have no _OSC support. To enable the
61walkaround, pls. add aerdriver.forceload=y to kernel boot parameter line
62when booting kernel. Note that forceload=n by default.
63
Zhang, Yanmin28eb27c2009-06-16 13:35:11 +080064nosourceid, another parameter of type bool, can be used when broken
65hardware (mostly chipsets) has root ports that cannot obtain the reporting
66source ID. nosourceid=n by default.
67
Zhang, Yanmin47402402006-07-31 15:15:18 +0800682.3 AER error output
69When a PCI-E AER error is captured, an error message will be outputed to
70console. If it's a correctable error, it is outputed as a warning.
71Otherwise, it is printed as an error. So users could choose different
72log level to filter out correctable error messages.
73
74Below shows an example.
75+------ PCI-Express Device Error -----+
76Error Severity : Uncorrected (Fatal)
77PCIE Bus Error type : Transaction Layer
78Unsupported Request : First
79Requester ID : 0500
80VendorID=8086h, DeviceID=0329h, Bus=05h, Device=00h, Function=00h
81TLB Header:
8204000001 00200a03 05010000 00050100
83
84In the example, 'Requester ID' means the ID of the device who sends
85the error message to root port. Pls. refer to pci express specs for
86other fields.
87
88
893. Developer Guide
90
91To enable AER aware support requires a software driver to configure
92the AER capability structure within its device and to provide callbacks.
93
94To support AER better, developers need understand how AER does work
95firstly.
96
97PCI Express errors are classified into two types: correctable errors
98and uncorrectable errors. This classification is based on the impacts
99of those errors, which may result in degraded performance or function
100failure.
101
102Correctable errors pose no impacts on the functionality of the
103interface. The PCI Express protocol can recover without any software
104intervention or any loss of data. These errors are detected and
105corrected by hardware. Unlike correctable errors, uncorrectable
106errors impact functionality of the interface. Uncorrectable errors
107can cause a particular transaction or a particular PCI Express link
108to be unreliable. Depending on those error conditions, uncorrectable
109errors are further classified into non-fatal errors and fatal errors.
110Non-fatal errors cause the particular transaction to be unreliable,
111but the PCI Express link itself is fully functional. Fatal errors, on
112the other hand, cause the link to be unreliable.
113
114When AER is enabled, a PCI Express device will automatically send an
115error message to the PCIE root port above it when the device captures
116an error. The Root Port, upon receiving an error reporting message,
117internally processes and logs the error message in its PCI Express
118capability structure. Error information being logged includes storing
119the error reporting agent's requestor ID into the Error Source
120Identification Registers and setting the error bits of the Root Error
121Status Register accordingly. If AER error reporting is enabled in Root
122Error Command Register, the Root Port generates an interrupt if an
123error is detected.
124
125Note that the errors as described above are related to the PCI Express
126hierarchy and links. These errors do not include any device specific
127errors because device specific errors will still get sent directly to
128the device driver.
129
1303.1 Configure the AER capability structure
131
132AER aware drivers of PCI Express component need change the device
133control registers to enable AER. They also could change AER registers,
134including mask and severity registers. Helper function
135pci_enable_pcie_error_reporting could be used to enable AER. See
136section 3.3.
137
1383.2. Provide callbacks
139
1403.2.1 callback reset_link to reset pci express link
141
142This callback is used to reset the pci express physical link when a
143fatal error happens. The root port aer service driver provides a
144default reset_link function, but different upstream ports might
145have different specifications to reset pci express link, so all
146upstream ports should provide their own reset_link functions.
147
148In struct pcie_port_service_driver, a new pointer, reset_link, is
149added.
150
151pci_ers_result_t (*reset_link) (struct pci_dev *dev);
152
153Section 3.2.2.2 provides more detailed info on when to call
154reset_link.
155
1563.2.2 PCI error-recovery callbacks
157
158The PCI Express AER Root driver uses error callbacks to coordinate
159with downstream device drivers associated with a hierarchy in question
160when performing error recovery actions.
161
162Data struct pci_driver has a pointer, err_handler, to point to
163pci_error_handlers who consists of a couple of callback function
164pointers. AER driver follows the rules defined in
165pci-error-recovery.txt except pci express specific parts (e.g.
166reset_link). Pls. refer to pci-error-recovery.txt for detailed
167definitions of the callbacks.
168
169Below sections specify when to call the error callback functions.
170
1713.2.2.1 Correctable errors
172
173Correctable errors pose no impacts on the functionality of
174the interface. The PCI Express protocol can recover without any
175software intervention or any loss of data. These errors do not
176require any recovery actions. The AER driver clears the device's
177correctable error status register accordingly and logs these errors.
178
1793.2.2.2 Non-correctable (non-fatal and fatal) errors
180
181If an error message indicates a non-fatal error, performing link reset
182at upstream is not required. The AER driver calls error_detected(dev,
183pci_channel_io_normal) to all drivers associated within a hierarchy in
184question. for example,
185EndPoint<==>DownstreamPort B<==>UpstreamPort A<==>RootPort.
186If Upstream port A captures an AER error, the hierarchy consists of
187Downstream port B and EndPoint.
188
189A driver may return PCI_ERS_RESULT_CAN_RECOVER,
190PCI_ERS_RESULT_DISCONNECT, or PCI_ERS_RESULT_NEED_RESET, depending on
191whether it can recover or the AER driver calls mmio_enabled as next.
192
193If an error message indicates a fatal error, kernel will broadcast
194error_detected(dev, pci_channel_io_frozen) to all drivers within
195a hierarchy in question. Then, performing link reset at upstream is
196necessary. As different kinds of devices might use different approaches
197to reset link, AER port service driver is required to provide the
198function to reset link. Firstly, kernel looks for if the upstream
199component has an aer driver. If it has, kernel uses the reset_link
200callback of the aer driver. If the upstream component has no aer driver
201and the port is downstream port, we will use the aer driver of the
202root port who reports the AER error. As for upstream ports,
203they should provide their own aer service drivers with reset_link
204function. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER and
205reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes
206to mmio_enabled.
207
2083.3 helper functions
209
Yu Zhao270c66b2008-10-19 20:35:20 +08002103.3.1 int pci_enable_pcie_error_reporting(struct pci_dev *dev);
Zhang, Yanmin47402402006-07-31 15:15:18 +0800211pci_enable_pcie_error_reporting enables the device to send error
212messages to root port when an error is detected. Note that devices
213don't enable the error reporting by default, so device drivers need
214call this function to enable it.
215
Yu Zhao270c66b2008-10-19 20:35:20 +08002163.3.2 int pci_disable_pcie_error_reporting(struct pci_dev *dev);
Zhang, Yanmin47402402006-07-31 15:15:18 +0800217pci_disable_pcie_error_reporting disables the device to send error
218messages to root port when an error is detected.
219
Yu Zhao270c66b2008-10-19 20:35:20 +08002203.3.3 int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);
Zhang, Yanmin47402402006-07-31 15:15:18 +0800221pci_cleanup_aer_uncorrect_error_status cleanups the uncorrectable
222error status register.
223
2243.4 Frequent Asked Questions
225
226Q: What happens if a PCI Express device driver does not provide an
227error recovery handler (pci_driver->err_handler is equal to NULL)?
228
229A: The devices attached with the driver won't be recovered. If the
230error is fatal, kernel will print out warning messages. Please refer
231to section 3 for more information.
232
233Q: What happens if an upstream port service driver does not provide
234callback reset_link?
235
236A: Fatal error recovery will fail if the errors are reported by the
237upstream ports who are attached by the service driver.
238
239Q: How does this infrastructure deal with driver that is not PCI
240Express aware?
241
242A: This infrastructure calls the error callback functions of the
243driver when an error happens. But if the driver is not aware of
244PCI Express, the device might not report its own errors to root
245port.
246
247Q: What modifications will that driver need to make it compatible
248with the PCI Express AER Root driver?
249
250A: It could call the helper functions to enable AER in devices and
251cleanup uncorrectable status register. Pls. refer to section 3.3.
252
Huang Yingbfe5a742009-04-24 10:45:31 +0800253
2544. Software error injection
255
256Debugging PCIE AER error recovery code is quite difficult because it
257is hard to trigger real hardware errors. Software based error
258injection can be used to fake various kinds of PCIE errors.
259
260First you should enable PCIE AER software error injection in kernel
261configuration, that is, following item should be in your .config.
262
263CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m
264
265After reboot with new kernel or insert the module, a device file named
266/dev/aer_inject should be created.
267
268Then, you need a user space tool named aer-inject, which can be gotten
269from:
Huang Yingc465def2009-06-15 10:42:57 +0800270 http://www.kernel.org/pub/linux/utils/pci/aer-inject/
Huang Yingbfe5a742009-04-24 10:45:31 +0800271
272More information about aer-inject can be found in the document comes
273with its source code.