Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel PRO/1000 Linux driver |
Bruce Allan | 0d6057e | 2011-01-04 01:16:44 +0000 | [diff] [blame] | 4 | Copyright(c) 1999 - 2011 Intel Corporation. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | Linux NICS <linux.nics@intel.com> |
| 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | |
| 27 | *******************************************************************************/ |
| 28 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 29 | #include "e1000.h" |
| 30 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 31 | /** |
| 32 | * e1000e_get_bus_info_pcie - Get PCIe bus information |
| 33 | * @hw: pointer to the HW structure |
| 34 | * |
| 35 | * Determines and stores the system bus information for a particular |
| 36 | * network interface. The following bus information is determined and stored: |
| 37 | * bus speed, bus width, type (PCIe), and PCIe function. |
| 38 | **/ |
| 39 | s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) |
| 40 | { |
Bruce Allan | f4d2dd4 | 2010-01-13 02:05:18 +0000 | [diff] [blame] | 41 | struct e1000_mac_info *mac = &hw->mac; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 42 | struct e1000_bus_info *bus = &hw->bus; |
| 43 | struct e1000_adapter *adapter = hw->adapter; |
Bruce Allan | f4d2dd4 | 2010-01-13 02:05:18 +0000 | [diff] [blame] | 44 | u16 pcie_link_status, cap_offset; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 45 | |
Jon Mason | 353064d | 2011-06-27 07:43:47 +0000 | [diff] [blame] | 46 | cap_offset = adapter->pdev->pcie_cap; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 47 | if (!cap_offset) { |
| 48 | bus->width = e1000_bus_width_unknown; |
| 49 | } else { |
| 50 | pci_read_config_word(adapter->pdev, |
| 51 | cap_offset + PCIE_LINK_STATUS, |
| 52 | &pcie_link_status); |
| 53 | bus->width = (enum e1000_bus_width)((pcie_link_status & |
| 54 | PCIE_LINK_WIDTH_MASK) >> |
| 55 | PCIE_LINK_WIDTH_SHIFT); |
| 56 | } |
| 57 | |
Bruce Allan | f4d2dd4 | 2010-01-13 02:05:18 +0000 | [diff] [blame] | 58 | mac->ops.set_lan_id(hw); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 59 | |
| 60 | return 0; |
| 61 | } |
| 62 | |
| 63 | /** |
Bruce Allan | f4d2dd4 | 2010-01-13 02:05:18 +0000 | [diff] [blame] | 64 | * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices |
| 65 | * |
| 66 | * @hw: pointer to the HW structure |
| 67 | * |
| 68 | * Determines the LAN function id by reading memory-mapped registers |
| 69 | * and swaps the port value if requested. |
| 70 | **/ |
| 71 | void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) |
| 72 | { |
| 73 | struct e1000_bus_info *bus = &hw->bus; |
| 74 | u32 reg; |
| 75 | |
| 76 | /* |
| 77 | * The status register reports the correct function number |
| 78 | * for the device regardless of function swap state. |
| 79 | */ |
| 80 | reg = er32(STATUS); |
| 81 | bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; |
| 82 | } |
| 83 | |
| 84 | /** |
| 85 | * e1000_set_lan_id_single_port - Set LAN id for a single port device |
| 86 | * @hw: pointer to the HW structure |
| 87 | * |
| 88 | * Sets the LAN function id to zero for a single port device. |
| 89 | **/ |
| 90 | void e1000_set_lan_id_single_port(struct e1000_hw *hw) |
| 91 | { |
| 92 | struct e1000_bus_info *bus = &hw->bus; |
| 93 | |
| 94 | bus->func = 0; |
| 95 | } |
| 96 | |
| 97 | /** |
Bruce Allan | caaddaf | 2009-12-01 15:46:43 +0000 | [diff] [blame] | 98 | * e1000_clear_vfta_generic - Clear VLAN filter table |
| 99 | * @hw: pointer to the HW structure |
| 100 | * |
| 101 | * Clears the register array which contains the VLAN filter table by |
| 102 | * setting all the values to 0. |
| 103 | **/ |
| 104 | void e1000_clear_vfta_generic(struct e1000_hw *hw) |
| 105 | { |
| 106 | u32 offset; |
| 107 | |
| 108 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
| 109 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); |
| 110 | e1e_flush(); |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | /** |
| 115 | * e1000_write_vfta_generic - Write value to VLAN filter table |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 116 | * @hw: pointer to the HW structure |
| 117 | * @offset: register offset in VLAN filter table |
| 118 | * @value: register value written to VLAN filter table |
| 119 | * |
| 120 | * Writes value at the given offset in the register array which stores |
| 121 | * the VLAN filter table. |
| 122 | **/ |
Bruce Allan | caaddaf | 2009-12-01 15:46:43 +0000 | [diff] [blame] | 123 | void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 124 | { |
| 125 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); |
| 126 | e1e_flush(); |
| 127 | } |
| 128 | |
| 129 | /** |
| 130 | * e1000e_init_rx_addrs - Initialize receive address's |
| 131 | * @hw: pointer to the HW structure |
| 132 | * @rar_count: receive address registers |
| 133 | * |
Bruce Allan | d64a6f4 | 2011-05-13 07:19:58 +0000 | [diff] [blame] | 134 | * Setup the receive address registers by setting the base receive address |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 135 | * register to the devices MAC address and clearing all the other receive |
| 136 | * address registers to 0. |
| 137 | **/ |
| 138 | void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) |
| 139 | { |
| 140 | u32 i; |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 141 | u8 mac_addr[ETH_ALEN] = { 0 }; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 142 | |
| 143 | /* Setup the receive address */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 144 | e_dbg("Programming MAC Address into RAR[0]\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 145 | |
| 146 | e1000e_rar_set(hw, hw->mac.addr, 0); |
| 147 | |
| 148 | /* Zero out the other (rar_entry_count - 1) receive addresses */ |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 149 | e_dbg("Clearing RAR[1-%u]\n", rar_count - 1); |
Bruce Allan | b7a9216 | 2010-01-07 16:32:13 +0000 | [diff] [blame] | 150 | for (i = 1; i < rar_count; i++) |
| 151 | e1000e_rar_set(hw, mac_addr, i); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | /** |
Bruce Allan | 608f8a0 | 2010-01-13 02:04:58 +0000 | [diff] [blame] | 155 | * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr |
| 156 | * @hw: pointer to the HW structure |
| 157 | * |
| 158 | * Checks the nvm for an alternate MAC address. An alternate MAC address |
| 159 | * can be setup by pre-boot software and must be treated like a permanent |
| 160 | * address and must override the actual permanent MAC address. If an |
| 161 | * alternate MAC address is found it is programmed into RAR0, replacing |
| 162 | * the permanent address that was installed into RAR0 by the Si on reset. |
| 163 | * This function will return SUCCESS unless it encounters an error while |
| 164 | * reading the EEPROM. |
| 165 | **/ |
| 166 | s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) |
| 167 | { |
| 168 | u32 i; |
| 169 | s32 ret_val = 0; |
| 170 | u16 offset, nvm_alt_mac_addr_offset, nvm_data; |
| 171 | u8 alt_mac_addr[ETH_ALEN]; |
| 172 | |
Bruce Allan | 1aef70e | 2010-08-19 15:48:52 -0700 | [diff] [blame] | 173 | ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data); |
| 174 | if (ret_val) |
| 175 | goto out; |
| 176 | |
Bruce Allan | 7ee9135 | 2011-12-16 00:45:35 +0000 | [diff] [blame] | 177 | /* not supported on older hardware or 82573 */ |
| 178 | if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) |
Bruce Allan | 1aef70e | 2010-08-19 15:48:52 -0700 | [diff] [blame] | 179 | goto out; |
| 180 | |
Bruce Allan | 608f8a0 | 2010-01-13 02:04:58 +0000 | [diff] [blame] | 181 | ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 182 | &nvm_alt_mac_addr_offset); |
Bruce Allan | 608f8a0 | 2010-01-13 02:04:58 +0000 | [diff] [blame] | 183 | if (ret_val) { |
| 184 | e_dbg("NVM Read Error\n"); |
| 185 | goto out; |
| 186 | } |
| 187 | |
Bruce Allan | 244735f | 2011-07-29 05:53:07 +0000 | [diff] [blame] | 188 | if ((nvm_alt_mac_addr_offset == 0xFFFF) || |
| 189 | (nvm_alt_mac_addr_offset == 0x0000)) |
Bruce Allan | 608f8a0 | 2010-01-13 02:04:58 +0000 | [diff] [blame] | 190 | /* There is no Alternate MAC Address */ |
| 191 | goto out; |
Bruce Allan | 608f8a0 | 2010-01-13 02:04:58 +0000 | [diff] [blame] | 192 | |
| 193 | if (hw->bus.func == E1000_FUNC_1) |
| 194 | nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; |
| 195 | for (i = 0; i < ETH_ALEN; i += 2) { |
| 196 | offset = nvm_alt_mac_addr_offset + (i >> 1); |
| 197 | ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); |
| 198 | if (ret_val) { |
| 199 | e_dbg("NVM Read Error\n"); |
| 200 | goto out; |
| 201 | } |
| 202 | |
| 203 | alt_mac_addr[i] = (u8)(nvm_data & 0xFF); |
| 204 | alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); |
| 205 | } |
| 206 | |
| 207 | /* if multicast bit is set, the alternate address will not be used */ |
Tobias Klauser | 3e714ad | 2011-07-03 23:47:04 +0000 | [diff] [blame] | 208 | if (is_multicast_ether_addr(alt_mac_addr)) { |
Bruce Allan | 608f8a0 | 2010-01-13 02:04:58 +0000 | [diff] [blame] | 209 | e_dbg("Ignoring Alternate Mac Address with MC bit set\n"); |
| 210 | goto out; |
| 211 | } |
| 212 | |
| 213 | /* |
| 214 | * We have a valid alternate MAC address, and we want to treat it the |
| 215 | * same as the normal permanent MAC address stored by the HW into the |
| 216 | * RAR. Do this by mapping this address into RAR0. |
| 217 | */ |
| 218 | e1000e_rar_set(hw, alt_mac_addr, 0); |
| 219 | |
| 220 | out: |
| 221 | return ret_val; |
| 222 | } |
| 223 | |
| 224 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 225 | * e1000e_rar_set - Set receive address register |
| 226 | * @hw: pointer to the HW structure |
| 227 | * @addr: pointer to the receive address |
| 228 | * @index: receive address array register |
| 229 | * |
| 230 | * Sets the receive address array register at index to the address passed |
| 231 | * in by addr. |
| 232 | **/ |
| 233 | void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) |
| 234 | { |
| 235 | u32 rar_low, rar_high; |
| 236 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 237 | /* |
| 238 | * HW expects these in little endian so we reverse the byte order |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 239 | * from network order (big endian) to little endian |
| 240 | */ |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 241 | rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | |
| 242 | ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 243 | |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 244 | rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 245 | |
Bruce Allan | b7a9216 | 2010-01-07 16:32:13 +0000 | [diff] [blame] | 246 | /* If MAC address zero, no need to set the AV bit */ |
| 247 | if (rar_low || rar_high) |
| 248 | rar_high |= E1000_RAH_AV; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 249 | |
Bruce Allan | b7a9216 | 2010-01-07 16:32:13 +0000 | [diff] [blame] | 250 | /* |
| 251 | * Some bridges will combine consecutive 32-bit writes into |
| 252 | * a single burst write, which will malfunction on some parts. |
| 253 | * The flushes avoid this. |
| 254 | */ |
| 255 | ew32(RAL(index), rar_low); |
| 256 | e1e_flush(); |
| 257 | ew32(RAH(index), rar_high); |
| 258 | e1e_flush(); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 259 | } |
| 260 | |
| 261 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 262 | * e1000_hash_mc_addr - Generate a multicast hash value |
| 263 | * @hw: pointer to the HW structure |
| 264 | * @mc_addr: pointer to a multicast address |
| 265 | * |
| 266 | * Generates a multicast address hash value which is used to determine |
| 267 | * the multicast filter table array address and new table value. See |
| 268 | * e1000_mta_set_generic() |
| 269 | **/ |
| 270 | static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) |
| 271 | { |
| 272 | u32 hash_value, hash_mask; |
| 273 | u8 bit_shift = 0; |
| 274 | |
| 275 | /* Register count multiplied by bits per register */ |
| 276 | hash_mask = (hw->mac.mta_reg_count * 32) - 1; |
| 277 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 278 | /* |
| 279 | * For a mc_filter_type of 0, bit_shift is the number of left-shifts |
| 280 | * where 0xFF would still fall within the hash mask. |
| 281 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 282 | while (hash_mask >> bit_shift != 0xFF) |
| 283 | bit_shift++; |
| 284 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 285 | /* |
| 286 | * The portion of the address that is used for the hash table |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 287 | * is determined by the mc_filter_type setting. |
| 288 | * The algorithm is such that there is a total of 8 bits of shifting. |
| 289 | * The bit_shift for a mc_filter_type of 0 represents the number of |
| 290 | * left-shifts where the MSB of mc_addr[5] would still fall within |
| 291 | * the hash_mask. Case 0 does this exactly. Since there are a total |
| 292 | * of 8 bits of shifting, then mc_addr[4] will shift right the |
| 293 | * remaining number of bits. Thus 8 - bit_shift. The rest of the |
| 294 | * cases are a variation of this algorithm...essentially raising the |
| 295 | * number of bits to shift mc_addr[5] left, while still keeping the |
| 296 | * 8-bit shifting total. |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 297 | * |
| 298 | * For example, given the following Destination MAC Address and an |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 299 | * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), |
| 300 | * we can see that the bit_shift for case 0 is 4. These are the hash |
| 301 | * values resulting from each mc_filter_type... |
| 302 | * [0] [1] [2] [3] [4] [5] |
| 303 | * 01 AA 00 12 34 56 |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 304 | * LSB MSB |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 305 | * |
| 306 | * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 |
| 307 | * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 |
| 308 | * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 |
| 309 | * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 |
| 310 | */ |
| 311 | switch (hw->mac.mc_filter_type) { |
| 312 | default: |
| 313 | case 0: |
| 314 | break; |
| 315 | case 1: |
| 316 | bit_shift += 1; |
| 317 | break; |
| 318 | case 2: |
| 319 | bit_shift += 2; |
| 320 | break; |
| 321 | case 3: |
| 322 | bit_shift += 4; |
| 323 | break; |
| 324 | } |
| 325 | |
| 326 | hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 327 | (((u16)mc_addr[5]) << bit_shift))); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 328 | |
| 329 | return hash_value; |
| 330 | } |
| 331 | |
| 332 | /** |
Jeff Kirsher | e2de3eb | 2008-03-28 09:15:11 -0700 | [diff] [blame] | 333 | * e1000e_update_mc_addr_list_generic - Update Multicast addresses |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 334 | * @hw: pointer to the HW structure |
| 335 | * @mc_addr_list: array of multicast addresses to program |
| 336 | * @mc_addr_count: number of multicast addresses to program |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 337 | * |
Bruce Allan | ab8932f | 2010-01-13 02:05:38 +0000 | [diff] [blame] | 338 | * Updates entire Multicast Table Array. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 339 | * The caller must have a packed mc_addr_list of multicast addresses. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 340 | **/ |
Jeff Kirsher | e2de3eb | 2008-03-28 09:15:11 -0700 | [diff] [blame] | 341 | void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, |
Bruce Allan | ab8932f | 2010-01-13 02:05:38 +0000 | [diff] [blame] | 342 | u8 *mc_addr_list, u32 mc_addr_count) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 343 | { |
Bruce Allan | ab8932f | 2010-01-13 02:05:38 +0000 | [diff] [blame] | 344 | u32 hash_value, hash_bit, hash_reg; |
| 345 | int i; |
Jesse Brandeburg | a72d2b2 | 2009-03-25 22:05:21 +0000 | [diff] [blame] | 346 | |
Bruce Allan | ab8932f | 2010-01-13 02:05:38 +0000 | [diff] [blame] | 347 | /* clear mta_shadow */ |
| 348 | memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 349 | |
Bruce Allan | ab8932f | 2010-01-13 02:05:38 +0000 | [diff] [blame] | 350 | /* update mta_shadow from mc_addr_list */ |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 351 | for (i = 0; (u32)i < mc_addr_count; i++) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 352 | hash_value = e1000_hash_mc_addr(hw, mc_addr_list); |
Bruce Allan | ab8932f | 2010-01-13 02:05:38 +0000 | [diff] [blame] | 353 | |
Jesse Brandeburg | a72d2b2 | 2009-03-25 22:05:21 +0000 | [diff] [blame] | 354 | hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); |
| 355 | hash_bit = hash_value & 0x1F; |
Bruce Allan | ab8932f | 2010-01-13 02:05:38 +0000 | [diff] [blame] | 356 | |
| 357 | hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); |
| 358 | mc_addr_list += (ETH_ALEN); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 359 | } |
Jesse Brandeburg | a72d2b2 | 2009-03-25 22:05:21 +0000 | [diff] [blame] | 360 | |
Bruce Allan | ab8932f | 2010-01-13 02:05:38 +0000 | [diff] [blame] | 361 | /* replace the entire MTA table */ |
| 362 | for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) |
| 363 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); |
Jesse Brandeburg | a72d2b2 | 2009-03-25 22:05:21 +0000 | [diff] [blame] | 364 | e1e_flush(); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 365 | } |
| 366 | |
| 367 | /** |
| 368 | * e1000e_clear_hw_cntrs_base - Clear base hardware counters |
| 369 | * @hw: pointer to the HW structure |
| 370 | * |
| 371 | * Clears the base hardware counters by reading the counter registers. |
| 372 | **/ |
| 373 | void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw) |
| 374 | { |
Bruce Allan | 99673d9 | 2009-11-20 23:27:21 +0000 | [diff] [blame] | 375 | er32(CRCERRS); |
| 376 | er32(SYMERRS); |
| 377 | er32(MPC); |
| 378 | er32(SCC); |
| 379 | er32(ECOL); |
| 380 | er32(MCC); |
| 381 | er32(LATECOL); |
| 382 | er32(COLC); |
| 383 | er32(DC); |
| 384 | er32(SEC); |
| 385 | er32(RLEC); |
| 386 | er32(XONRXC); |
| 387 | er32(XONTXC); |
| 388 | er32(XOFFRXC); |
| 389 | er32(XOFFTXC); |
| 390 | er32(FCRUC); |
| 391 | er32(GPRC); |
| 392 | er32(BPRC); |
| 393 | er32(MPRC); |
| 394 | er32(GPTC); |
| 395 | er32(GORCL); |
| 396 | er32(GORCH); |
| 397 | er32(GOTCL); |
| 398 | er32(GOTCH); |
| 399 | er32(RNBC); |
| 400 | er32(RUC); |
| 401 | er32(RFC); |
| 402 | er32(ROC); |
| 403 | er32(RJC); |
| 404 | er32(TORL); |
| 405 | er32(TORH); |
| 406 | er32(TOTL); |
| 407 | er32(TOTH); |
| 408 | er32(TPR); |
| 409 | er32(TPT); |
| 410 | er32(MPTC); |
| 411 | er32(BPTC); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 412 | } |
| 413 | |
| 414 | /** |
| 415 | * e1000e_check_for_copper_link - Check for link (Copper) |
| 416 | * @hw: pointer to the HW structure |
| 417 | * |
| 418 | * Checks to see of the link status of the hardware has changed. If a |
| 419 | * change in link status has been detected, then we read the PHY registers |
| 420 | * to get the current speed/duplex if link exists. |
| 421 | **/ |
| 422 | s32 e1000e_check_for_copper_link(struct e1000_hw *hw) |
| 423 | { |
| 424 | struct e1000_mac_info *mac = &hw->mac; |
| 425 | s32 ret_val; |
| 426 | bool link; |
| 427 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 428 | /* |
| 429 | * We only want to go out to the PHY registers to see if Auto-Neg |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 430 | * has completed and/or if our link status has changed. The |
| 431 | * get_link_status flag is set upon receiving a Link Status |
| 432 | * Change or Rx Sequence Error interrupt. |
| 433 | */ |
| 434 | if (!mac->get_link_status) |
| 435 | return 0; |
| 436 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 437 | /* |
| 438 | * First we want to see if the MII Status Register reports |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 439 | * link. If so, then we want to get the current speed/duplex |
| 440 | * of the PHY. |
| 441 | */ |
| 442 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
| 443 | if (ret_val) |
| 444 | return ret_val; |
| 445 | |
| 446 | if (!link) |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 447 | return ret_val; /* No link detected */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 448 | |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 449 | mac->get_link_status = false; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 450 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 451 | /* |
| 452 | * Check if there was DownShift, must be checked |
| 453 | * immediately after link-up |
| 454 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 455 | e1000e_check_downshift(hw); |
| 456 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 457 | /* |
| 458 | * If we are forcing speed/duplex, then we simply return since |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 459 | * we have already determined whether we have link or not. |
| 460 | */ |
| 461 | if (!mac->autoneg) { |
| 462 | ret_val = -E1000_ERR_CONFIG; |
| 463 | return ret_val; |
| 464 | } |
| 465 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 466 | /* |
| 467 | * Auto-Neg is enabled. Auto Speed Detection takes care |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 468 | * of MAC speed/duplex configuration. So we only need to |
| 469 | * configure Collision Distance in the MAC. |
| 470 | */ |
| 471 | e1000e_config_collision_dist(hw); |
| 472 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 473 | /* |
| 474 | * Configure Flow Control now that Auto-Neg has completed. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 475 | * First, we need to restore the desired flow control |
| 476 | * settings because we may have had to re-autoneg with a |
| 477 | * different link partner. |
| 478 | */ |
| 479 | ret_val = e1000e_config_fc_after_link_up(hw); |
Bruce Allan | b1cdfea | 2010-12-11 05:53:47 +0000 | [diff] [blame] | 480 | if (ret_val) |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 481 | e_dbg("Error configuring flow control\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 482 | |
| 483 | return ret_val; |
| 484 | } |
| 485 | |
| 486 | /** |
| 487 | * e1000e_check_for_fiber_link - Check for link (Fiber) |
| 488 | * @hw: pointer to the HW structure |
| 489 | * |
| 490 | * Checks for link up on the hardware. If link is not up and we have |
| 491 | * a signal, then we need to force link up. |
| 492 | **/ |
| 493 | s32 e1000e_check_for_fiber_link(struct e1000_hw *hw) |
| 494 | { |
| 495 | struct e1000_mac_info *mac = &hw->mac; |
| 496 | u32 rxcw; |
| 497 | u32 ctrl; |
| 498 | u32 status; |
| 499 | s32 ret_val; |
| 500 | |
| 501 | ctrl = er32(CTRL); |
| 502 | status = er32(STATUS); |
| 503 | rxcw = er32(RXCW); |
| 504 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 505 | /* |
| 506 | * If we don't have link (auto-negotiation failed or link partner |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 507 | * cannot auto-negotiate), the cable is plugged in (we have signal), |
| 508 | * and our link partner is not trying to auto-negotiate with us (we |
| 509 | * are receiving idles or data), we need to force link up. We also |
| 510 | * need to give auto-negotiation time to complete, in case the cable |
| 511 | * was just plugged in. The autoneg_failed flag does this. |
| 512 | */ |
| 513 | /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ |
| 514 | if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && |
| 515 | (!(rxcw & E1000_RXCW_C))) { |
| 516 | if (mac->autoneg_failed == 0) { |
| 517 | mac->autoneg_failed = 1; |
| 518 | return 0; |
| 519 | } |
Bruce Allan | af667a2 | 2010-12-31 06:10:01 +0000 | [diff] [blame] | 520 | e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 521 | |
| 522 | /* Disable auto-negotiation in the TXCW register */ |
| 523 | ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
| 524 | |
| 525 | /* Force link-up and also force full-duplex. */ |
| 526 | ctrl = er32(CTRL); |
| 527 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
| 528 | ew32(CTRL, ctrl); |
| 529 | |
| 530 | /* Configure Flow Control after forcing link up. */ |
| 531 | ret_val = e1000e_config_fc_after_link_up(hw); |
| 532 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 533 | e_dbg("Error configuring flow control\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 534 | return ret_val; |
| 535 | } |
| 536 | } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 537 | /* |
| 538 | * If we are forcing link and we are receiving /C/ ordered |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 539 | * sets, re-enable auto-negotiation in the TXCW register |
| 540 | * and disable forced link in the Device Control register |
| 541 | * in an attempt to auto-negotiate with our link partner. |
| 542 | */ |
Bruce Allan | af667a2 | 2010-12-31 06:10:01 +0000 | [diff] [blame] | 543 | e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 544 | ew32(TXCW, mac->txcw); |
| 545 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
| 546 | |
Alex Chiang | 612e244 | 2009-02-05 23:55:45 -0800 | [diff] [blame] | 547 | mac->serdes_has_link = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 548 | } |
| 549 | |
| 550 | return 0; |
| 551 | } |
| 552 | |
| 553 | /** |
| 554 | * e1000e_check_for_serdes_link - Check for link (Serdes) |
| 555 | * @hw: pointer to the HW structure |
| 556 | * |
| 557 | * Checks for link up on the hardware. If link is not up and we have |
| 558 | * a signal, then we need to force link up. |
| 559 | **/ |
| 560 | s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) |
| 561 | { |
| 562 | struct e1000_mac_info *mac = &hw->mac; |
| 563 | u32 rxcw; |
| 564 | u32 ctrl; |
| 565 | u32 status; |
| 566 | s32 ret_val; |
| 567 | |
| 568 | ctrl = er32(CTRL); |
| 569 | status = er32(STATUS); |
| 570 | rxcw = er32(RXCW); |
| 571 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 572 | /* |
| 573 | * If we don't have link (auto-negotiation failed or link partner |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 574 | * cannot auto-negotiate), and our link partner is not trying to |
| 575 | * auto-negotiate with us (we are receiving idles or data), |
| 576 | * we need to force link up. We also need to give auto-negotiation |
| 577 | * time to complete. |
| 578 | */ |
| 579 | /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ |
| 580 | if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { |
| 581 | if (mac->autoneg_failed == 0) { |
| 582 | mac->autoneg_failed = 1; |
| 583 | return 0; |
| 584 | } |
Bruce Allan | af667a2 | 2010-12-31 06:10:01 +0000 | [diff] [blame] | 585 | e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 586 | |
| 587 | /* Disable auto-negotiation in the TXCW register */ |
| 588 | ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
| 589 | |
| 590 | /* Force link-up and also force full-duplex. */ |
| 591 | ctrl = er32(CTRL); |
| 592 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
| 593 | ew32(CTRL, ctrl); |
| 594 | |
| 595 | /* Configure Flow Control after forcing link up. */ |
| 596 | ret_val = e1000e_config_fc_after_link_up(hw); |
| 597 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 598 | e_dbg("Error configuring flow control\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 599 | return ret_val; |
| 600 | } |
| 601 | } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 602 | /* |
| 603 | * If we are forcing link and we are receiving /C/ ordered |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 604 | * sets, re-enable auto-negotiation in the TXCW register |
| 605 | * and disable forced link in the Device Control register |
| 606 | * in an attempt to auto-negotiate with our link partner. |
| 607 | */ |
Bruce Allan | af667a2 | 2010-12-31 06:10:01 +0000 | [diff] [blame] | 608 | e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 609 | ew32(TXCW, mac->txcw); |
| 610 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
| 611 | |
Alex Chiang | 612e244 | 2009-02-05 23:55:45 -0800 | [diff] [blame] | 612 | mac->serdes_has_link = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 613 | } else if (!(E1000_TXCW_ANE & er32(TXCW))) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 614 | /* |
| 615 | * If we force link for non-auto-negotiation switch, check |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 616 | * link status based on MAC synchronization for internal |
| 617 | * serdes media type. |
| 618 | */ |
| 619 | /* SYNCH bit and IV bit are sticky. */ |
| 620 | udelay(10); |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 621 | rxcw = er32(RXCW); |
| 622 | if (rxcw & E1000_RXCW_SYNCH) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 623 | if (!(rxcw & E1000_RXCW_IV)) { |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 624 | mac->serdes_has_link = true; |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 625 | e_dbg("SERDES: Link up - forced.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 626 | } |
| 627 | } else { |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 628 | mac->serdes_has_link = false; |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 629 | e_dbg("SERDES: Link down - force failed.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 630 | } |
| 631 | } |
| 632 | |
| 633 | if (E1000_TXCW_ANE & er32(TXCW)) { |
| 634 | status = er32(STATUS); |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 635 | if (status & E1000_STATUS_LU) { |
| 636 | /* SYNCH bit and IV bit are sticky, so reread rxcw. */ |
| 637 | udelay(10); |
| 638 | rxcw = er32(RXCW); |
| 639 | if (rxcw & E1000_RXCW_SYNCH) { |
| 640 | if (!(rxcw & E1000_RXCW_IV)) { |
| 641 | mac->serdes_has_link = true; |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 642 | e_dbg("SERDES: Link up - autoneg completed successfully.\n"); |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 643 | } else { |
| 644 | mac->serdes_has_link = false; |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 645 | e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n"); |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 646 | } |
| 647 | } else { |
| 648 | mac->serdes_has_link = false; |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 649 | e_dbg("SERDES: Link down - no sync.\n"); |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 650 | } |
| 651 | } else { |
| 652 | mac->serdes_has_link = false; |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 653 | e_dbg("SERDES: Link down - autoneg failed\n"); |
Bruce Allan | 63dcf3d | 2008-11-21 16:50:34 -0800 | [diff] [blame] | 654 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 655 | } |
| 656 | |
| 657 | return 0; |
| 658 | } |
| 659 | |
| 660 | /** |
| 661 | * e1000_set_default_fc_generic - Set flow control default values |
| 662 | * @hw: pointer to the HW structure |
| 663 | * |
| 664 | * Read the EEPROM for the default values for flow control and store the |
| 665 | * values. |
| 666 | **/ |
| 667 | static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) |
| 668 | { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 669 | s32 ret_val; |
| 670 | u16 nvm_data; |
| 671 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 672 | /* |
| 673 | * Read and store word 0x0F of the EEPROM. This word contains bits |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 674 | * that determine the hardware's default PAUSE (flow control) mode, |
| 675 | * a bit that determines whether the HW defaults to enabling or |
| 676 | * disabling auto-negotiation, and the direction of the |
| 677 | * SW defined pins. If there is no SW over-ride of the flow |
| 678 | * control setting, then the variable hw->fc will |
| 679 | * be initialized based on a value in the EEPROM. |
| 680 | */ |
| 681 | ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); |
| 682 | |
| 683 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 684 | e_dbg("NVM Read Error\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 685 | return ret_val; |
| 686 | } |
| 687 | |
| 688 | if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 689 | hw->fc.requested_mode = e1000_fc_none; |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 690 | else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR) |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 691 | hw->fc.requested_mode = e1000_fc_tx_pause; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 692 | else |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 693 | hw->fc.requested_mode = e1000_fc_full; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 694 | |
| 695 | return 0; |
| 696 | } |
| 697 | |
| 698 | /** |
| 699 | * e1000e_setup_link - Setup flow control and link settings |
| 700 | * @hw: pointer to the HW structure |
| 701 | * |
| 702 | * Determines which flow control settings to use, then configures flow |
| 703 | * control. Calls the appropriate media-specific link configuration |
| 704 | * function. Assuming the adapter has a valid link partner, a valid link |
| 705 | * should be established. Assumes the hardware has previously been reset |
| 706 | * and the transmitter and receiver are not enabled. |
| 707 | **/ |
| 708 | s32 e1000e_setup_link(struct e1000_hw *hw) |
| 709 | { |
| 710 | struct e1000_mac_info *mac = &hw->mac; |
| 711 | s32 ret_val; |
| 712 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 713 | /* |
| 714 | * In the case of the phy reset being blocked, we already have a link. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 715 | * We do not need to set it up again. |
| 716 | */ |
| 717 | if (e1000_check_reset_block(hw)) |
| 718 | return 0; |
| 719 | |
Auke Kok | 309af40 | 2007-10-05 15:22:02 -0700 | [diff] [blame] | 720 | /* |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 721 | * If requested flow control is set to default, set flow control |
| 722 | * based on the EEPROM flow control settings. |
Auke Kok | 309af40 | 2007-10-05 15:22:02 -0700 | [diff] [blame] | 723 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 724 | if (hw->fc.requested_mode == e1000_fc_default) { |
Auke Kok | 309af40 | 2007-10-05 15:22:02 -0700 | [diff] [blame] | 725 | ret_val = e1000_set_default_fc_generic(hw); |
| 726 | if (ret_val) |
| 727 | return ret_val; |
| 728 | } |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 729 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 730 | /* |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 731 | * Save off the requested flow control mode for use later. Depending |
| 732 | * on the link partner's capabilities, we may or may not use this mode. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 733 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 734 | hw->fc.current_mode = hw->fc.requested_mode; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 735 | |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 736 | e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 737 | |
| 738 | /* Call the necessary media_type subroutine to configure the link. */ |
| 739 | ret_val = mac->ops.setup_physical_interface(hw); |
| 740 | if (ret_val) |
| 741 | return ret_val; |
| 742 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 743 | /* |
| 744 | * Initialize the flow control address, type, and PAUSE timer |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 745 | * registers to their default values. This is done even if flow |
| 746 | * control is disabled, because it does not hurt anything to |
| 747 | * initialize these registers. |
| 748 | */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 749 | e_dbg("Initializing the Flow Control address, type and timer regs\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 750 | ew32(FCT, FLOW_CONTROL_TYPE); |
| 751 | ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
| 752 | ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); |
| 753 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 754 | ew32(FCTTV, hw->fc.pause_time); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 755 | |
| 756 | return e1000e_set_fc_watermarks(hw); |
| 757 | } |
| 758 | |
| 759 | /** |
| 760 | * e1000_commit_fc_settings_generic - Configure flow control |
| 761 | * @hw: pointer to the HW structure |
| 762 | * |
| 763 | * Write the flow control settings to the Transmit Config Word Register (TXCW) |
| 764 | * base on the flow control settings in e1000_mac_info. |
| 765 | **/ |
| 766 | static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) |
| 767 | { |
| 768 | struct e1000_mac_info *mac = &hw->mac; |
| 769 | u32 txcw; |
| 770 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 771 | /* |
| 772 | * Check for a software override of the flow control settings, and |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 773 | * setup the device accordingly. If auto-negotiation is enabled, then |
| 774 | * software will have to set the "PAUSE" bits to the correct value in |
| 775 | * the Transmit Config Word Register (TXCW) and re-start auto- |
| 776 | * negotiation. However, if auto-negotiation is disabled, then |
| 777 | * software will have to manually configure the two flow control enable |
| 778 | * bits in the CTRL register. |
| 779 | * |
| 780 | * The possible values of the "fc" parameter are: |
| 781 | * 0: Flow control is completely disabled |
| 782 | * 1: Rx flow control is enabled (we can receive pause frames, |
Bruce Allan | af667a2 | 2010-12-31 06:10:01 +0000 | [diff] [blame] | 783 | * but not send pause frames). |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 784 | * 2: Tx flow control is enabled (we can send pause frames but we |
Bruce Allan | af667a2 | 2010-12-31 06:10:01 +0000 | [diff] [blame] | 785 | * do not support receiving pause frames). |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 786 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 787 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 788 | switch (hw->fc.current_mode) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 789 | case e1000_fc_none: |
| 790 | /* Flow control completely disabled by a software over-ride. */ |
| 791 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
| 792 | break; |
| 793 | case e1000_fc_rx_pause: |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 794 | /* |
| 795 | * Rx Flow control is enabled and Tx Flow control is disabled |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 796 | * by a software over-ride. Since there really isn't a way to |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 797 | * advertise that we are capable of Rx Pause ONLY, we will |
| 798 | * advertise that we support both symmetric and asymmetric Rx |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 799 | * PAUSE. Later, we will disable the adapter's ability to send |
| 800 | * PAUSE frames. |
| 801 | */ |
| 802 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
| 803 | break; |
| 804 | case e1000_fc_tx_pause: |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 805 | /* |
| 806 | * Tx Flow control is enabled, and Rx Flow control is disabled, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 807 | * by a software over-ride. |
| 808 | */ |
| 809 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
| 810 | break; |
| 811 | case e1000_fc_full: |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 812 | /* |
| 813 | * Flow control (both Rx and Tx) is enabled by a software |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 814 | * over-ride. |
| 815 | */ |
| 816 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
| 817 | break; |
| 818 | default: |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 819 | e_dbg("Flow control param set incorrectly\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 820 | return -E1000_ERR_CONFIG; |
| 821 | break; |
| 822 | } |
| 823 | |
| 824 | ew32(TXCW, txcw); |
| 825 | mac->txcw = txcw; |
| 826 | |
| 827 | return 0; |
| 828 | } |
| 829 | |
| 830 | /** |
| 831 | * e1000_poll_fiber_serdes_link_generic - Poll for link up |
| 832 | * @hw: pointer to the HW structure |
| 833 | * |
| 834 | * Polls for link up by reading the status register, if link fails to come |
| 835 | * up with auto-negotiation, then the link is forced if a signal is detected. |
| 836 | **/ |
| 837 | static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) |
| 838 | { |
| 839 | struct e1000_mac_info *mac = &hw->mac; |
| 840 | u32 i, status; |
| 841 | s32 ret_val; |
| 842 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 843 | /* |
| 844 | * If we have a signal (the cable is plugged in, or assumed true for |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 845 | * serdes media) then poll for a "Link-Up" indication in the Device |
| 846 | * Status Register. Time-out if a link isn't seen in 500 milliseconds |
| 847 | * seconds (Auto-negotiation should complete in less than 500 |
| 848 | * milliseconds even if the other end is doing it in SW). |
| 849 | */ |
| 850 | for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 851 | usleep_range(10000, 20000); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 852 | status = er32(STATUS); |
| 853 | if (status & E1000_STATUS_LU) |
| 854 | break; |
| 855 | } |
| 856 | if (i == FIBER_LINK_UP_LIMIT) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 857 | e_dbg("Never got a valid link from auto-neg!!!\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 858 | mac->autoneg_failed = 1; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 859 | /* |
| 860 | * AutoNeg failed to achieve a link, so we'll call |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 861 | * mac->check_for_link. This routine will force the |
| 862 | * link up if we detect a signal. This will allow us to |
| 863 | * communicate with non-autonegotiating link partners. |
| 864 | */ |
| 865 | ret_val = mac->ops.check_for_link(hw); |
| 866 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 867 | e_dbg("Error while checking for link\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 868 | return ret_val; |
| 869 | } |
| 870 | mac->autoneg_failed = 0; |
| 871 | } else { |
| 872 | mac->autoneg_failed = 0; |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 873 | e_dbg("Valid Link Found\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 874 | } |
| 875 | |
| 876 | return 0; |
| 877 | } |
| 878 | |
| 879 | /** |
| 880 | * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes |
| 881 | * @hw: pointer to the HW structure |
| 882 | * |
| 883 | * Configures collision distance and flow control for fiber and serdes |
| 884 | * links. Upon successful setup, poll for link. |
| 885 | **/ |
| 886 | s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw) |
| 887 | { |
| 888 | u32 ctrl; |
| 889 | s32 ret_val; |
| 890 | |
| 891 | ctrl = er32(CTRL); |
| 892 | |
| 893 | /* Take the link out of reset */ |
| 894 | ctrl &= ~E1000_CTRL_LRST; |
| 895 | |
| 896 | e1000e_config_collision_dist(hw); |
| 897 | |
| 898 | ret_val = e1000_commit_fc_settings_generic(hw); |
| 899 | if (ret_val) |
| 900 | return ret_val; |
| 901 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 902 | /* |
| 903 | * Since auto-negotiation is enabled, take the link out of reset (the |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 904 | * link will be in reset, because we previously reset the chip). This |
| 905 | * will restart auto-negotiation. If auto-negotiation is successful |
| 906 | * then the link-up status bit will be set and the flow control enable |
| 907 | * bits (RFCE and TFCE) will be set according to their negotiated value. |
| 908 | */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 909 | e_dbg("Auto-negotiation enabled\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 910 | |
| 911 | ew32(CTRL, ctrl); |
| 912 | e1e_flush(); |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 913 | usleep_range(1000, 2000); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 914 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 915 | /* |
| 916 | * For these adapters, the SW definable pin 1 is set when the optics |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 917 | * detect a signal. If we have a signal, then poll for a "Link-Up" |
| 918 | * indication. |
| 919 | */ |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 920 | if (hw->phy.media_type == e1000_media_type_internal_serdes || |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 921 | (er32(CTRL) & E1000_CTRL_SWDPIN1)) { |
| 922 | ret_val = e1000_poll_fiber_serdes_link_generic(hw); |
| 923 | } else { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 924 | e_dbg("No signal detected\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 925 | } |
| 926 | |
| 927 | return 0; |
| 928 | } |
| 929 | |
| 930 | /** |
| 931 | * e1000e_config_collision_dist - Configure collision distance |
| 932 | * @hw: pointer to the HW structure |
| 933 | * |
| 934 | * Configures the collision distance to the default value and is used |
| 935 | * during link setup. Currently no func pointer exists and all |
| 936 | * implementations are handled in the generic version of this function. |
| 937 | **/ |
| 938 | void e1000e_config_collision_dist(struct e1000_hw *hw) |
| 939 | { |
| 940 | u32 tctl; |
| 941 | |
| 942 | tctl = er32(TCTL); |
| 943 | |
| 944 | tctl &= ~E1000_TCTL_COLD; |
| 945 | tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; |
| 946 | |
| 947 | ew32(TCTL, tctl); |
| 948 | e1e_flush(); |
| 949 | } |
| 950 | |
| 951 | /** |
| 952 | * e1000e_set_fc_watermarks - Set flow control high/low watermarks |
| 953 | * @hw: pointer to the HW structure |
| 954 | * |
| 955 | * Sets the flow control high/low threshold (watermark) registers. If |
| 956 | * flow control XON frame transmission is enabled, then set XON frame |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 957 | * transmission as well. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 958 | **/ |
| 959 | s32 e1000e_set_fc_watermarks(struct e1000_hw *hw) |
| 960 | { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 961 | u32 fcrtl = 0, fcrth = 0; |
| 962 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 963 | /* |
| 964 | * Set the flow control receive threshold registers. Normally, |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 965 | * these registers will be set to a default threshold that may be |
| 966 | * adjusted later by the driver's runtime code. However, if the |
| 967 | * ability to transmit pause frames is not enabled, then these |
| 968 | * registers will be set to 0. |
| 969 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 970 | if (hw->fc.current_mode & e1000_fc_tx_pause) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 971 | /* |
| 972 | * We need to set up the Receive Threshold high and low water |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 973 | * marks as well as (optionally) enabling the transmission of |
| 974 | * XON frames. |
| 975 | */ |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 976 | fcrtl = hw->fc.low_water; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 977 | fcrtl |= E1000_FCRTL_XONE; |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 978 | fcrth = hw->fc.high_water; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 979 | } |
| 980 | ew32(FCRTL, fcrtl); |
| 981 | ew32(FCRTH, fcrth); |
| 982 | |
| 983 | return 0; |
| 984 | } |
| 985 | |
| 986 | /** |
| 987 | * e1000e_force_mac_fc - Force the MAC's flow control settings |
| 988 | * @hw: pointer to the HW structure |
| 989 | * |
| 990 | * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the |
| 991 | * device control register to reflect the adapter settings. TFCE and RFCE |
| 992 | * need to be explicitly set by software when a copper PHY is used because |
| 993 | * autonegotiation is managed by the PHY rather than the MAC. Software must |
| 994 | * also configure these bits when link is forced on a fiber connection. |
| 995 | **/ |
| 996 | s32 e1000e_force_mac_fc(struct e1000_hw *hw) |
| 997 | { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 998 | u32 ctrl; |
| 999 | |
| 1000 | ctrl = er32(CTRL); |
| 1001 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1002 | /* |
| 1003 | * Because we didn't get link via the internal auto-negotiation |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1004 | * mechanism (we either forced link or we got link via PHY |
| 1005 | * auto-neg), we have to manually enable/disable transmit an |
| 1006 | * receive flow control. |
| 1007 | * |
| 1008 | * The "Case" statement below enables/disable flow control |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1009 | * according to the "hw->fc.current_mode" parameter. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1010 | * |
| 1011 | * The possible values of the "fc" parameter are: |
| 1012 | * 0: Flow control is completely disabled |
| 1013 | * 1: Rx flow control is enabled (we can receive pause |
Bruce Allan | af667a2 | 2010-12-31 06:10:01 +0000 | [diff] [blame] | 1014 | * frames but not send pause frames). |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1015 | * 2: Tx flow control is enabled (we can send pause frames |
Bruce Allan | af667a2 | 2010-12-31 06:10:01 +0000 | [diff] [blame] | 1016 | * frames but we do not receive pause frames). |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1017 | * 3: Both Rx and Tx flow control (symmetric) is enabled. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1018 | * other: No other values should be possible at this point. |
| 1019 | */ |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1020 | e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1021 | |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1022 | switch (hw->fc.current_mode) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1023 | case e1000_fc_none: |
| 1024 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
| 1025 | break; |
| 1026 | case e1000_fc_rx_pause: |
| 1027 | ctrl &= (~E1000_CTRL_TFCE); |
| 1028 | ctrl |= E1000_CTRL_RFCE; |
| 1029 | break; |
| 1030 | case e1000_fc_tx_pause: |
| 1031 | ctrl &= (~E1000_CTRL_RFCE); |
| 1032 | ctrl |= E1000_CTRL_TFCE; |
| 1033 | break; |
| 1034 | case e1000_fc_full: |
| 1035 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
| 1036 | break; |
| 1037 | default: |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1038 | e_dbg("Flow control param set incorrectly\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1039 | return -E1000_ERR_CONFIG; |
| 1040 | } |
| 1041 | |
| 1042 | ew32(CTRL, ctrl); |
| 1043 | |
| 1044 | return 0; |
| 1045 | } |
| 1046 | |
| 1047 | /** |
| 1048 | * e1000e_config_fc_after_link_up - Configures flow control after link |
| 1049 | * @hw: pointer to the HW structure |
| 1050 | * |
| 1051 | * Checks the status of auto-negotiation after link up to ensure that the |
| 1052 | * speed and duplex were not forced. If the link needed to be forced, then |
| 1053 | * flow control needs to be forced also. If auto-negotiation is enabled |
| 1054 | * and did not fail, then we configure flow control based on our link |
| 1055 | * partner. |
| 1056 | **/ |
| 1057 | s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) |
| 1058 | { |
| 1059 | struct e1000_mac_info *mac = &hw->mac; |
| 1060 | s32 ret_val = 0; |
| 1061 | u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; |
| 1062 | u16 speed, duplex; |
| 1063 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1064 | /* |
| 1065 | * Check for the case where we have fiber media and auto-neg failed |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1066 | * so we had to force link. In this case, we need to force the |
| 1067 | * configuration of the MAC to match the "fc" parameter. |
| 1068 | */ |
| 1069 | if (mac->autoneg_failed) { |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1070 | if (hw->phy.media_type == e1000_media_type_fiber || |
| 1071 | hw->phy.media_type == e1000_media_type_internal_serdes) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1072 | ret_val = e1000e_force_mac_fc(hw); |
| 1073 | } else { |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1074 | if (hw->phy.media_type == e1000_media_type_copper) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1075 | ret_val = e1000e_force_mac_fc(hw); |
| 1076 | } |
| 1077 | |
| 1078 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1079 | e_dbg("Error forcing flow control settings\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1080 | return ret_val; |
| 1081 | } |
| 1082 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1083 | /* |
| 1084 | * Check for the case where we have copper media and auto-neg is |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1085 | * enabled. In this case, we need to check and see if Auto-Neg |
| 1086 | * has completed, and if so, how the PHY and link partner has |
| 1087 | * flow control configured. |
| 1088 | */ |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1089 | if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1090 | /* |
| 1091 | * Read the MII Status Register and check to see if AutoNeg |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1092 | * has completed. We read this twice because this reg has |
| 1093 | * some "sticky" (latched) bits. |
| 1094 | */ |
| 1095 | ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); |
| 1096 | if (ret_val) |
| 1097 | return ret_val; |
| 1098 | ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); |
| 1099 | if (ret_val) |
| 1100 | return ret_val; |
| 1101 | |
| 1102 | if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 1103 | e_dbg("Copper PHY and Auto Neg has not completed.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1104 | return ret_val; |
| 1105 | } |
| 1106 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1107 | /* |
| 1108 | * The AutoNeg process has completed, so we now need to |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1109 | * read both the Auto Negotiation Advertisement |
| 1110 | * Register (Address 4) and the Auto_Negotiation Base |
| 1111 | * Page Ability Register (Address 5) to determine how |
| 1112 | * flow control was negotiated. |
| 1113 | */ |
| 1114 | ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg); |
| 1115 | if (ret_val) |
| 1116 | return ret_val; |
Bruce Allan | 482fed8 | 2011-01-06 14:29:49 +0000 | [diff] [blame] | 1117 | ret_val = |
| 1118 | e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1119 | if (ret_val) |
| 1120 | return ret_val; |
| 1121 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1122 | /* |
| 1123 | * Two bits in the Auto Negotiation Advertisement Register |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1124 | * (Address 4) and two bits in the Auto Negotiation Base |
| 1125 | * Page Ability Register (Address 5) determine flow control |
| 1126 | * for both the PHY and the link partner. The following |
| 1127 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
| 1128 | * 1999, describes these PAUSE resolution bits and how flow |
| 1129 | * control is determined based upon these settings. |
| 1130 | * NOTE: DC = Don't Care |
| 1131 | * |
| 1132 | * LOCAL DEVICE | LINK PARTNER |
| 1133 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
| 1134 | *-------|---------|-------|---------|-------------------- |
| 1135 | * 0 | 0 | DC | DC | e1000_fc_none |
| 1136 | * 0 | 1 | 0 | DC | e1000_fc_none |
| 1137 | * 0 | 1 | 1 | 0 | e1000_fc_none |
| 1138 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
| 1139 | * 1 | 0 | 0 | DC | e1000_fc_none |
| 1140 | * 1 | DC | 1 | DC | e1000_fc_full |
| 1141 | * 1 | 1 | 0 | 0 | e1000_fc_none |
| 1142 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
| 1143 | * |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1144 | * Are both PAUSE bits set to 1? If so, this implies |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1145 | * Symmetric Flow Control is enabled at both ends. The |
| 1146 | * ASM_DIR bits are irrelevant per the spec. |
| 1147 | * |
| 1148 | * For Symmetric Flow Control: |
| 1149 | * |
| 1150 | * LOCAL DEVICE | LINK PARTNER |
| 1151 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 1152 | *-------|---------|-------|---------|-------------------- |
| 1153 | * 1 | DC | 1 | DC | E1000_fc_full |
| 1154 | * |
| 1155 | */ |
| 1156 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 1157 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1158 | /* |
| 1159 | * Now we need to check if the user selected Rx ONLY |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1160 | * of pause frames. In this case, we had to advertise |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1161 | * FULL flow control because we could not advertise Rx |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1162 | * ONLY. Hence, we must now check to see if we need to |
Bruce Allan | d64a6f4 | 2011-05-13 07:19:58 +0000 | [diff] [blame] | 1163 | * turn OFF the TRANSMISSION of PAUSE frames. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1164 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1165 | if (hw->fc.requested_mode == e1000_fc_full) { |
| 1166 | hw->fc.current_mode = e1000_fc_full; |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 1167 | e_dbg("Flow Control = FULL.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1168 | } else { |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1169 | hw->fc.current_mode = e1000_fc_rx_pause; |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 1170 | e_dbg("Flow Control = Rx PAUSE frames only.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1171 | } |
| 1172 | } |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1173 | /* |
| 1174 | * For receiving PAUSE frames ONLY. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1175 | * |
| 1176 | * LOCAL DEVICE | LINK PARTNER |
| 1177 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 1178 | *-------|---------|-------|---------|-------------------- |
| 1179 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1180 | */ |
| 1181 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 1182 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 1183 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 1184 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1185 | hw->fc.current_mode = e1000_fc_tx_pause; |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 1186 | e_dbg("Flow Control = Tx PAUSE frames only.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1187 | } |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1188 | /* |
| 1189 | * For transmitting PAUSE frames ONLY. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1190 | * |
| 1191 | * LOCAL DEVICE | LINK PARTNER |
| 1192 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 1193 | *-------|---------|-------|---------|-------------------- |
| 1194 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1195 | */ |
| 1196 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 1197 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 1198 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 1199 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1200 | hw->fc.current_mode = e1000_fc_rx_pause; |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 1201 | e_dbg("Flow Control = Rx PAUSE frames only.\n"); |
Jesse Brandeburg | de92d84 | 2008-02-21 15:11:02 -0800 | [diff] [blame] | 1202 | } else { |
| 1203 | /* |
| 1204 | * Per the IEEE spec, at this point flow control |
| 1205 | * should be disabled. |
| 1206 | */ |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1207 | hw->fc.current_mode = e1000_fc_none; |
Bruce Allan | 434f139 | 2011-12-16 00:46:54 +0000 | [diff] [blame] | 1208 | e_dbg("Flow Control = NONE.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1209 | } |
| 1210 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1211 | /* |
| 1212 | * Now we need to do one last check... If we auto- |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1213 | * negotiated to HALF DUPLEX, flow control should not be |
| 1214 | * enabled per IEEE 802.3 spec. |
| 1215 | */ |
| 1216 | ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); |
| 1217 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1218 | e_dbg("Error getting link speed and duplex\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1219 | return ret_val; |
| 1220 | } |
| 1221 | |
| 1222 | if (duplex == HALF_DUPLEX) |
Bruce Allan | 5c48ef3e2 | 2008-11-21 16:57:36 -0800 | [diff] [blame] | 1223 | hw->fc.current_mode = e1000_fc_none; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1224 | |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1225 | /* |
| 1226 | * Now we call a subroutine to actually force the MAC |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1227 | * controller to use the correct flow control settings. |
| 1228 | */ |
| 1229 | ret_val = e1000e_force_mac_fc(hw); |
| 1230 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1231 | e_dbg("Error forcing flow control settings\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1232 | return ret_val; |
| 1233 | } |
| 1234 | } |
| 1235 | |
| 1236 | return 0; |
| 1237 | } |
| 1238 | |
| 1239 | /** |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1240 | * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1241 | * @hw: pointer to the HW structure |
| 1242 | * @speed: stores the current speed |
| 1243 | * @duplex: stores the current duplex |
| 1244 | * |
| 1245 | * Read the status register for the current speed/duplex and store the current |
| 1246 | * speed and duplex for copper connections. |
| 1247 | **/ |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 1248 | s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, |
| 1249 | u16 *duplex) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1250 | { |
| 1251 | u32 status; |
| 1252 | |
| 1253 | status = er32(STATUS); |
Joe Perches | 2c73e1f | 2010-03-26 20:16:59 +0000 | [diff] [blame] | 1254 | if (status & E1000_STATUS_SPEED_1000) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1255 | *speed = SPEED_1000; |
Joe Perches | 2c73e1f | 2010-03-26 20:16:59 +0000 | [diff] [blame] | 1256 | else if (status & E1000_STATUS_SPEED_100) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1257 | *speed = SPEED_100; |
Joe Perches | 2c73e1f | 2010-03-26 20:16:59 +0000 | [diff] [blame] | 1258 | else |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1259 | *speed = SPEED_10; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1260 | |
Joe Perches | 2c73e1f | 2010-03-26 20:16:59 +0000 | [diff] [blame] | 1261 | if (status & E1000_STATUS_FD) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1262 | *duplex = FULL_DUPLEX; |
Joe Perches | 2c73e1f | 2010-03-26 20:16:59 +0000 | [diff] [blame] | 1263 | else |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1264 | *duplex = HALF_DUPLEX; |
Joe Perches | 2c73e1f | 2010-03-26 20:16:59 +0000 | [diff] [blame] | 1265 | |
| 1266 | e_dbg("%u Mbps, %s Duplex\n", |
| 1267 | *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10, |
| 1268 | *duplex == FULL_DUPLEX ? "Full" : "Half"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1269 | |
| 1270 | return 0; |
| 1271 | } |
| 1272 | |
| 1273 | /** |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1274 | * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1275 | * @hw: pointer to the HW structure |
| 1276 | * @speed: stores the current speed |
| 1277 | * @duplex: stores the current duplex |
| 1278 | * |
| 1279 | * Sets the speed and duplex to gigabit full duplex (the only possible option) |
| 1280 | * for fiber/serdes links. |
| 1281 | **/ |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 1282 | s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, |
| 1283 | u16 *duplex) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1284 | { |
| 1285 | *speed = SPEED_1000; |
| 1286 | *duplex = FULL_DUPLEX; |
| 1287 | |
| 1288 | return 0; |
| 1289 | } |
| 1290 | |
| 1291 | /** |
| 1292 | * e1000e_get_hw_semaphore - Acquire hardware semaphore |
| 1293 | * @hw: pointer to the HW structure |
| 1294 | * |
| 1295 | * Acquire the HW semaphore to access the PHY or NVM |
| 1296 | **/ |
| 1297 | s32 e1000e_get_hw_semaphore(struct e1000_hw *hw) |
| 1298 | { |
| 1299 | u32 swsm; |
| 1300 | s32 timeout = hw->nvm.word_size + 1; |
| 1301 | s32 i = 0; |
| 1302 | |
| 1303 | /* Get the SW semaphore */ |
| 1304 | while (i < timeout) { |
| 1305 | swsm = er32(SWSM); |
| 1306 | if (!(swsm & E1000_SWSM_SMBI)) |
| 1307 | break; |
| 1308 | |
| 1309 | udelay(50); |
| 1310 | i++; |
| 1311 | } |
| 1312 | |
| 1313 | if (i == timeout) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1314 | e_dbg("Driver can't access device - SMBI bit is set.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1315 | return -E1000_ERR_NVM; |
| 1316 | } |
| 1317 | |
| 1318 | /* Get the FW semaphore. */ |
| 1319 | for (i = 0; i < timeout; i++) { |
| 1320 | swsm = er32(SWSM); |
| 1321 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); |
| 1322 | |
| 1323 | /* Semaphore acquired if bit latched */ |
| 1324 | if (er32(SWSM) & E1000_SWSM_SWESMBI) |
| 1325 | break; |
| 1326 | |
| 1327 | udelay(50); |
| 1328 | } |
| 1329 | |
| 1330 | if (i == timeout) { |
| 1331 | /* Release semaphores */ |
| 1332 | e1000e_put_hw_semaphore(hw); |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1333 | e_dbg("Driver can't access the NVM\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1334 | return -E1000_ERR_NVM; |
| 1335 | } |
| 1336 | |
| 1337 | return 0; |
| 1338 | } |
| 1339 | |
| 1340 | /** |
| 1341 | * e1000e_put_hw_semaphore - Release hardware semaphore |
| 1342 | * @hw: pointer to the HW structure |
| 1343 | * |
| 1344 | * Release hardware semaphore used to access the PHY or NVM |
| 1345 | **/ |
| 1346 | void e1000e_put_hw_semaphore(struct e1000_hw *hw) |
| 1347 | { |
| 1348 | u32 swsm; |
| 1349 | |
| 1350 | swsm = er32(SWSM); |
| 1351 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
| 1352 | ew32(SWSM, swsm); |
| 1353 | } |
| 1354 | |
| 1355 | /** |
| 1356 | * e1000e_get_auto_rd_done - Check for auto read completion |
| 1357 | * @hw: pointer to the HW structure |
| 1358 | * |
| 1359 | * Check EEPROM for Auto Read done bit. |
| 1360 | **/ |
| 1361 | s32 e1000e_get_auto_rd_done(struct e1000_hw *hw) |
| 1362 | { |
| 1363 | s32 i = 0; |
| 1364 | |
| 1365 | while (i < AUTO_READ_DONE_TIMEOUT) { |
| 1366 | if (er32(EECD) & E1000_EECD_AUTO_RD) |
| 1367 | break; |
Bruce Allan | 1bba438 | 2011-03-19 00:27:20 +0000 | [diff] [blame] | 1368 | usleep_range(1000, 2000); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1369 | i++; |
| 1370 | } |
| 1371 | |
| 1372 | if (i == AUTO_READ_DONE_TIMEOUT) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1373 | e_dbg("Auto read by HW from NVM has not completed.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1374 | return -E1000_ERR_RESET; |
| 1375 | } |
| 1376 | |
| 1377 | return 0; |
| 1378 | } |
| 1379 | |
| 1380 | /** |
| 1381 | * e1000e_valid_led_default - Verify a valid default LED config |
| 1382 | * @hw: pointer to the HW structure |
| 1383 | * @data: pointer to the NVM (EEPROM) |
| 1384 | * |
| 1385 | * Read the EEPROM for the current default LED configuration. If the |
| 1386 | * LED configuration is not valid, set to a valid LED configuration. |
| 1387 | **/ |
| 1388 | s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data) |
| 1389 | { |
| 1390 | s32 ret_val; |
| 1391 | |
| 1392 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); |
| 1393 | if (ret_val) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1394 | e_dbg("NVM Read Error\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1395 | return ret_val; |
| 1396 | } |
| 1397 | |
| 1398 | if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) |
| 1399 | *data = ID_LED_DEFAULT; |
| 1400 | |
| 1401 | return 0; |
| 1402 | } |
| 1403 | |
| 1404 | /** |
| 1405 | * e1000e_id_led_init - |
| 1406 | * @hw: pointer to the HW structure |
| 1407 | * |
| 1408 | **/ |
| 1409 | s32 e1000e_id_led_init(struct e1000_hw *hw) |
| 1410 | { |
| 1411 | struct e1000_mac_info *mac = &hw->mac; |
| 1412 | s32 ret_val; |
| 1413 | const u32 ledctl_mask = 0x000000FF; |
| 1414 | const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
| 1415 | const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
| 1416 | u16 data, i, temp; |
| 1417 | const u16 led_mask = 0x0F; |
| 1418 | |
| 1419 | ret_val = hw->nvm.ops.valid_led_default(hw, &data); |
| 1420 | if (ret_val) |
| 1421 | return ret_val; |
| 1422 | |
| 1423 | mac->ledctl_default = er32(LEDCTL); |
| 1424 | mac->ledctl_mode1 = mac->ledctl_default; |
| 1425 | mac->ledctl_mode2 = mac->ledctl_default; |
| 1426 | |
| 1427 | for (i = 0; i < 4; i++) { |
| 1428 | temp = (data >> (i << 2)) & led_mask; |
| 1429 | switch (temp) { |
| 1430 | case ID_LED_ON1_DEF2: |
| 1431 | case ID_LED_ON1_ON2: |
| 1432 | case ID_LED_ON1_OFF2: |
| 1433 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 1434 | mac->ledctl_mode1 |= ledctl_on << (i << 3); |
| 1435 | break; |
| 1436 | case ID_LED_OFF1_DEF2: |
| 1437 | case ID_LED_OFF1_ON2: |
| 1438 | case ID_LED_OFF1_OFF2: |
| 1439 | mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 1440 | mac->ledctl_mode1 |= ledctl_off << (i << 3); |
| 1441 | break; |
| 1442 | default: |
| 1443 | /* Do nothing */ |
| 1444 | break; |
| 1445 | } |
| 1446 | switch (temp) { |
| 1447 | case ID_LED_DEF1_ON2: |
| 1448 | case ID_LED_ON1_ON2: |
| 1449 | case ID_LED_OFF1_ON2: |
| 1450 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 1451 | mac->ledctl_mode2 |= ledctl_on << (i << 3); |
| 1452 | break; |
| 1453 | case ID_LED_DEF1_OFF2: |
| 1454 | case ID_LED_ON1_OFF2: |
| 1455 | case ID_LED_OFF1_OFF2: |
| 1456 | mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 1457 | mac->ledctl_mode2 |= ledctl_off << (i << 3); |
| 1458 | break; |
| 1459 | default: |
| 1460 | /* Do nothing */ |
| 1461 | break; |
| 1462 | } |
| 1463 | } |
| 1464 | |
| 1465 | return 0; |
| 1466 | } |
| 1467 | |
| 1468 | /** |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1469 | * e1000e_setup_led_generic - Configures SW controllable LED |
| 1470 | * @hw: pointer to the HW structure |
| 1471 | * |
| 1472 | * This prepares the SW controllable LED for use and saves the current state |
| 1473 | * of the LED so it can be later restored. |
| 1474 | **/ |
| 1475 | s32 e1000e_setup_led_generic(struct e1000_hw *hw) |
| 1476 | { |
| 1477 | u32 ledctl; |
| 1478 | |
Bruce Allan | b1cdfea | 2010-12-11 05:53:47 +0000 | [diff] [blame] | 1479 | if (hw->mac.ops.setup_led != e1000e_setup_led_generic) |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1480 | return -E1000_ERR_CONFIG; |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1481 | |
| 1482 | if (hw->phy.media_type == e1000_media_type_fiber) { |
| 1483 | ledctl = er32(LEDCTL); |
| 1484 | hw->mac.ledctl_default = ledctl; |
| 1485 | /* Turn off LED0 */ |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 1486 | ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | |
| 1487 | E1000_LEDCTL_LED0_MODE_MASK); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1488 | ledctl |= (E1000_LEDCTL_MODE_LED_OFF << |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 1489 | E1000_LEDCTL_LED0_MODE_SHIFT); |
Bruce Allan | a4f58f5 | 2009-06-02 11:29:18 +0000 | [diff] [blame] | 1490 | ew32(LEDCTL, ledctl); |
| 1491 | } else if (hw->phy.media_type == e1000_media_type_copper) { |
| 1492 | ew32(LEDCTL, hw->mac.ledctl_mode1); |
| 1493 | } |
| 1494 | |
| 1495 | return 0; |
| 1496 | } |
| 1497 | |
| 1498 | /** |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1499 | * e1000e_cleanup_led_generic - Set LED config to default operation |
| 1500 | * @hw: pointer to the HW structure |
| 1501 | * |
| 1502 | * Remove the current LED configuration and set the LED configuration |
| 1503 | * to the default value, saved from the EEPROM. |
| 1504 | **/ |
| 1505 | s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) |
| 1506 | { |
| 1507 | ew32(LEDCTL, hw->mac.ledctl_default); |
| 1508 | return 0; |
| 1509 | } |
| 1510 | |
| 1511 | /** |
Bruce Allan | dbf80dc | 2011-04-16 00:34:40 +0000 | [diff] [blame] | 1512 | * e1000e_blink_led_generic - Blink LED |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1513 | * @hw: pointer to the HW structure |
| 1514 | * |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1515 | * Blink the LEDs which are set to be on. |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1516 | **/ |
Bruce Allan | dbf80dc | 2011-04-16 00:34:40 +0000 | [diff] [blame] | 1517 | s32 e1000e_blink_led_generic(struct e1000_hw *hw) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1518 | { |
| 1519 | u32 ledctl_blink = 0; |
| 1520 | u32 i; |
| 1521 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1522 | if (hw->phy.media_type == e1000_media_type_fiber) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1523 | /* always blink LED0 for PCI-E fiber */ |
| 1524 | ledctl_blink = E1000_LEDCTL_LED0_BLINK | |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 1525 | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1526 | } else { |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1527 | /* |
| 1528 | * set the blink bit for each LED that's "on" (0x0E) |
| 1529 | * in ledctl_mode2 |
| 1530 | */ |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1531 | ledctl_blink = hw->mac.ledctl_mode2; |
| 1532 | for (i = 0; i < 4; i++) |
| 1533 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == |
| 1534 | E1000_LEDCTL_MODE_LED_ON) |
| 1535 | ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << |
| 1536 | (i * 8)); |
| 1537 | } |
| 1538 | |
| 1539 | ew32(LEDCTL, ledctl_blink); |
| 1540 | |
| 1541 | return 0; |
| 1542 | } |
| 1543 | |
| 1544 | /** |
| 1545 | * e1000e_led_on_generic - Turn LED on |
| 1546 | * @hw: pointer to the HW structure |
| 1547 | * |
| 1548 | * Turn LED on. |
| 1549 | **/ |
| 1550 | s32 e1000e_led_on_generic(struct e1000_hw *hw) |
| 1551 | { |
| 1552 | u32 ctrl; |
| 1553 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1554 | switch (hw->phy.media_type) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1555 | case e1000_media_type_fiber: |
| 1556 | ctrl = er32(CTRL); |
| 1557 | ctrl &= ~E1000_CTRL_SWDPIN0; |
| 1558 | ctrl |= E1000_CTRL_SWDPIO0; |
| 1559 | ew32(CTRL, ctrl); |
| 1560 | break; |
| 1561 | case e1000_media_type_copper: |
| 1562 | ew32(LEDCTL, hw->mac.ledctl_mode2); |
| 1563 | break; |
| 1564 | default: |
| 1565 | break; |
| 1566 | } |
| 1567 | |
| 1568 | return 0; |
| 1569 | } |
| 1570 | |
| 1571 | /** |
| 1572 | * e1000e_led_off_generic - Turn LED off |
| 1573 | * @hw: pointer to the HW structure |
| 1574 | * |
| 1575 | * Turn LED off. |
| 1576 | **/ |
| 1577 | s32 e1000e_led_off_generic(struct e1000_hw *hw) |
| 1578 | { |
| 1579 | u32 ctrl; |
| 1580 | |
Jeff Kirsher | 318a94d | 2008-03-28 09:15:16 -0700 | [diff] [blame] | 1581 | switch (hw->phy.media_type) { |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1582 | case e1000_media_type_fiber: |
| 1583 | ctrl = er32(CTRL); |
| 1584 | ctrl |= E1000_CTRL_SWDPIN0; |
| 1585 | ctrl |= E1000_CTRL_SWDPIO0; |
| 1586 | ew32(CTRL, ctrl); |
| 1587 | break; |
| 1588 | case e1000_media_type_copper: |
| 1589 | ew32(LEDCTL, hw->mac.ledctl_mode1); |
| 1590 | break; |
| 1591 | default: |
| 1592 | break; |
| 1593 | } |
| 1594 | |
| 1595 | return 0; |
| 1596 | } |
| 1597 | |
| 1598 | /** |
| 1599 | * e1000e_set_pcie_no_snoop - Set PCI-express capabilities |
| 1600 | * @hw: pointer to the HW structure |
| 1601 | * @no_snoop: bitmap of snoop events |
| 1602 | * |
| 1603 | * Set the PCI-express register to snoop for events enabled in 'no_snoop'. |
| 1604 | **/ |
| 1605 | void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) |
| 1606 | { |
| 1607 | u32 gcr; |
| 1608 | |
| 1609 | if (no_snoop) { |
| 1610 | gcr = er32(GCR); |
| 1611 | gcr &= ~(PCIE_NO_SNOOP_ALL); |
| 1612 | gcr |= no_snoop; |
| 1613 | ew32(GCR, gcr); |
| 1614 | } |
| 1615 | } |
| 1616 | |
| 1617 | /** |
| 1618 | * e1000e_disable_pcie_master - Disables PCI-express master access |
| 1619 | * @hw: pointer to the HW structure |
| 1620 | * |
| 1621 | * Returns 0 if successful, else returns -10 |
Auke Kok | 489815c | 2008-02-21 15:11:07 -0800 | [diff] [blame] | 1622 | * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1623 | * the master requests to be disabled. |
| 1624 | * |
| 1625 | * Disables PCI-Express master access and verifies there are no pending |
| 1626 | * requests. |
| 1627 | **/ |
| 1628 | s32 e1000e_disable_pcie_master(struct e1000_hw *hw) |
| 1629 | { |
| 1630 | u32 ctrl; |
| 1631 | s32 timeout = MASTER_DISABLE_TIMEOUT; |
| 1632 | |
| 1633 | ctrl = er32(CTRL); |
| 1634 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
| 1635 | ew32(CTRL, ctrl); |
| 1636 | |
| 1637 | while (timeout) { |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 1638 | if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1639 | break; |
| 1640 | udelay(100); |
| 1641 | timeout--; |
| 1642 | } |
| 1643 | |
| 1644 | if (!timeout) { |
Bruce Allan | 3bb99fe | 2009-11-20 23:25:07 +0000 | [diff] [blame] | 1645 | e_dbg("Master requests are pending.\n"); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1646 | return -E1000_ERR_MASTER_REQUESTS_PENDING; |
| 1647 | } |
| 1648 | |
| 1649 | return 0; |
| 1650 | } |
| 1651 | |
| 1652 | /** |
| 1653 | * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing |
| 1654 | * @hw: pointer to the HW structure |
| 1655 | * |
| 1656 | * Reset the Adaptive Interframe Spacing throttle to default values. |
| 1657 | **/ |
| 1658 | void e1000e_reset_adaptive(struct e1000_hw *hw) |
| 1659 | { |
| 1660 | struct e1000_mac_info *mac = &hw->mac; |
| 1661 | |
Bruce Allan | f464ba8 | 2010-01-07 16:31:35 +0000 | [diff] [blame] | 1662 | if (!mac->adaptive_ifs) { |
| 1663 | e_dbg("Not in Adaptive IFS mode!\n"); |
| 1664 | goto out; |
| 1665 | } |
| 1666 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1667 | mac->current_ifs_val = 0; |
| 1668 | mac->ifs_min_val = IFS_MIN; |
| 1669 | mac->ifs_max_val = IFS_MAX; |
| 1670 | mac->ifs_step_size = IFS_STEP; |
| 1671 | mac->ifs_ratio = IFS_RATIO; |
| 1672 | |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 1673 | mac->in_ifs_mode = false; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1674 | ew32(AIT, 0); |
Bruce Allan | f464ba8 | 2010-01-07 16:31:35 +0000 | [diff] [blame] | 1675 | out: |
| 1676 | return; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1677 | } |
| 1678 | |
| 1679 | /** |
| 1680 | * e1000e_update_adaptive - Update Adaptive Interframe Spacing |
| 1681 | * @hw: pointer to the HW structure |
| 1682 | * |
| 1683 | * Update the Adaptive Interframe Spacing Throttle value based on the |
| 1684 | * time between transmitted packets and time between collisions. |
| 1685 | **/ |
| 1686 | void e1000e_update_adaptive(struct e1000_hw *hw) |
| 1687 | { |
| 1688 | struct e1000_mac_info *mac = &hw->mac; |
| 1689 | |
Bruce Allan | f464ba8 | 2010-01-07 16:31:35 +0000 | [diff] [blame] | 1690 | if (!mac->adaptive_ifs) { |
| 1691 | e_dbg("Not in Adaptive IFS mode!\n"); |
| 1692 | goto out; |
| 1693 | } |
| 1694 | |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1695 | if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { |
| 1696 | if (mac->tx_packet_delta > MIN_NUM_XMITS) { |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 1697 | mac->in_ifs_mode = true; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1698 | if (mac->current_ifs_val < mac->ifs_max_val) { |
| 1699 | if (!mac->current_ifs_val) |
| 1700 | mac->current_ifs_val = mac->ifs_min_val; |
| 1701 | else |
| 1702 | mac->current_ifs_val += |
Bruce Allan | fe2ddfb | 2011-12-21 09:47:10 +0000 | [diff] [blame^] | 1703 | mac->ifs_step_size; |
Bruce Allan | ad68076 | 2008-03-28 09:15:03 -0700 | [diff] [blame] | 1704 | ew32(AIT, mac->current_ifs_val); |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1705 | } |
| 1706 | } |
| 1707 | } else { |
| 1708 | if (mac->in_ifs_mode && |
| 1709 | (mac->tx_packet_delta <= MIN_NUM_XMITS)) { |
| 1710 | mac->current_ifs_val = 0; |
Bruce Allan | 564ea9b | 2009-11-20 23:26:44 +0000 | [diff] [blame] | 1711 | mac->in_ifs_mode = false; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1712 | ew32(AIT, 0); |
| 1713 | } |
| 1714 | } |
Bruce Allan | f464ba8 | 2010-01-07 16:31:35 +0000 | [diff] [blame] | 1715 | out: |
| 1716 | return; |
Auke Kok | bc7f75f | 2007-09-17 12:30:59 -0700 | [diff] [blame] | 1717 | } |