David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 1 | /* |
| 2 | * winbond-cir.c - Driver for the Consumer IR functionality of Winbond |
| 3 | * SuperI/O chips. |
| 4 | * |
| 5 | * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but |
| 6 | * could probably support others (Winbond WEC102X, NatSemi, etc) |
| 7 | * with minor modifications. |
| 8 | * |
| 9 | * Original Author: David Härdeman <david@hardeman.nu> |
| 10 | * Copyright (C) 2009 - 2010 David Härdeman <david@hardeman.nu> |
| 11 | * |
| 12 | * Dedicated to my daughter Matilda, without whose loving attention this |
| 13 | * driver would have been finished in half the time and with a fraction |
| 14 | * of the bugs. |
| 15 | * |
| 16 | * Written using: |
| 17 | * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel |
| 18 | * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff) |
| 19 | * o DSDT dumps |
| 20 | * |
| 21 | * Supported features: |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 22 | * o IR Receive |
| 23 | * o IR Transmit |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 24 | * o Wake-On-CIR functionality |
| 25 | * |
| 26 | * To do: |
| 27 | * o Learning |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 28 | * |
| 29 | * This program is free software; you can redistribute it and/or modify |
| 30 | * it under the terms of the GNU General Public License as published by |
| 31 | * the Free Software Foundation; either version 2 of the License, or |
| 32 | * (at your option) any later version. |
| 33 | * |
| 34 | * This program is distributed in the hope that it will be useful, |
| 35 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 36 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 37 | * GNU General Public License for more details. |
| 38 | * |
| 39 | * You should have received a copy of the GNU General Public License |
| 40 | * along with this program; if not, write to the Free Software |
| 41 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 42 | */ |
| 43 | |
| 44 | #include <linux/module.h> |
| 45 | #include <linux/pnp.h> |
| 46 | #include <linux/interrupt.h> |
| 47 | #include <linux/timer.h> |
| 48 | #include <linux/leds.h> |
| 49 | #include <linux/spinlock.h> |
| 50 | #include <linux/pci_ids.h> |
| 51 | #include <linux/io.h> |
| 52 | #include <linux/bitrev.h> |
| 53 | #include <linux/slab.h> |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 54 | #include <linux/wait.h> |
| 55 | #include <linux/sched.h> |
Mauro Carvalho Chehab | 6bda964 | 2010-11-17 13:28:38 -0300 | [diff] [blame] | 56 | #include <media/rc-core.h> |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 57 | |
| 58 | #define DRVNAME "winbond-cir" |
| 59 | |
| 60 | /* CEIR Wake-Up Registers, relative to data->wbase */ |
| 61 | #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */ |
| 62 | #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */ |
| 63 | #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */ |
| 64 | #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */ |
| 65 | #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */ |
| 66 | #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */ |
| 67 | #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */ |
| 68 | #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */ |
| 69 | #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */ |
| 70 | #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */ |
| 71 | |
| 72 | /* CEIR Enhanced Functionality Registers, relative to data->ebase */ |
| 73 | #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */ |
| 74 | #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */ |
| 75 | #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */ |
| 76 | #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */ |
| 77 | #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */ |
| 78 | |
| 79 | /* SP3 Banked Registers, relative to data->sbase */ |
| 80 | #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */ |
| 81 | /* Bank 0 */ |
| 82 | #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */ |
| 83 | #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */ |
| 84 | #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */ |
| 85 | #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */ |
| 86 | #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */ |
| 87 | #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */ |
| 88 | #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */ |
| 89 | #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */ |
| 90 | #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */ |
| 91 | /* Bank 2 */ |
| 92 | #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */ |
| 93 | #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */ |
| 94 | #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */ |
| 95 | #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */ |
| 96 | #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */ |
| 97 | #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */ |
| 98 | /* Bank 3 */ |
| 99 | #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */ |
| 100 | #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */ |
| 101 | #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */ |
| 102 | /* Bank 4 */ |
| 103 | #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */ |
| 104 | /* Bank 5 */ |
| 105 | #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */ |
| 106 | /* Bank 6 */ |
| 107 | #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */ |
| 108 | #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */ |
| 109 | /* Bank 7 */ |
| 110 | #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */ |
| 111 | #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */ |
| 112 | #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */ |
| 113 | #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */ |
| 114 | #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */ |
| 115 | |
| 116 | /* |
| 117 | * Magic values follow |
| 118 | */ |
| 119 | |
| 120 | /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
| 121 | #define WBCIR_IRQ_NONE 0x00 |
| 122 | /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
| 123 | #define WBCIR_IRQ_RX 0x01 |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 124 | /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
| 125 | #define WBCIR_IRQ_TX_LOW 0x02 |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 126 | /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
| 127 | #define WBCIR_IRQ_ERR 0x04 |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 128 | /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
| 129 | #define WBCIR_IRQ_TX_EMPTY 0x20 |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 130 | /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */ |
| 131 | #define WBCIR_LED_ENABLE 0x80 |
| 132 | /* RX data available bit for WBCIR_REG_SP3_LSR */ |
| 133 | #define WBCIR_RX_AVAIL 0x01 |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 134 | /* RX data overrun error bit for WBCIR_REG_SP3_LSR */ |
| 135 | #define WBCIR_RX_OVERRUN 0x02 |
| 136 | /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */ |
| 137 | #define WBCIR_TX_EOT 0x04 |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 138 | /* RX disable bit for WBCIR_REG_SP3_ASCR */ |
| 139 | #define WBCIR_RX_DISABLE 0x20 |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 140 | /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */ |
| 141 | #define WBCIR_TX_UNDERRUN 0x40 |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 142 | /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */ |
| 143 | #define WBCIR_EXT_ENABLE 0x01 |
| 144 | /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ |
| 145 | #define WBCIR_REGSEL_COMPARE 0x10 |
| 146 | /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ |
| 147 | #define WBCIR_REGSEL_MASK 0x20 |
| 148 | /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */ |
| 149 | #define WBCIR_REG_ADDR0 0x00 |
| 150 | |
| 151 | /* Valid banks for the SP3 UART */ |
| 152 | enum wbcir_bank { |
| 153 | WBCIR_BANK_0 = 0x00, |
| 154 | WBCIR_BANK_1 = 0x80, |
| 155 | WBCIR_BANK_2 = 0xE0, |
| 156 | WBCIR_BANK_3 = 0xE4, |
| 157 | WBCIR_BANK_4 = 0xE8, |
| 158 | WBCIR_BANK_5 = 0xEC, |
| 159 | WBCIR_BANK_6 = 0xF0, |
| 160 | WBCIR_BANK_7 = 0xF4, |
| 161 | }; |
| 162 | |
| 163 | /* Supported power-on IR Protocols */ |
| 164 | enum wbcir_protocol { |
| 165 | IR_PROTOCOL_RC5 = 0x0, |
| 166 | IR_PROTOCOL_NEC = 0x1, |
| 167 | IR_PROTOCOL_RC6 = 0x2, |
| 168 | }; |
| 169 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 170 | /* Possible states for IR reception */ |
| 171 | enum wbcir_rxstate { |
| 172 | WBCIR_RXSTATE_INACTIVE = 0, |
| 173 | WBCIR_RXSTATE_ACTIVE, |
| 174 | WBCIR_RXSTATE_ERROR |
| 175 | }; |
| 176 | |
| 177 | /* Possible states for IR transmission */ |
| 178 | enum wbcir_txstate { |
| 179 | WBCIR_TXSTATE_INACTIVE = 0, |
| 180 | WBCIR_TXSTATE_ACTIVE, |
| 181 | WBCIR_TXSTATE_DONE, |
| 182 | WBCIR_TXSTATE_ERROR |
| 183 | }; |
| 184 | |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 185 | /* Misc */ |
| 186 | #define WBCIR_NAME "Winbond CIR" |
| 187 | #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */ |
| 188 | #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */ |
| 189 | #define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */ |
| 190 | #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */ |
| 191 | #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */ |
| 192 | #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */ |
| 193 | |
| 194 | /* Per-device data */ |
| 195 | struct wbcir_data { |
| 196 | spinlock_t spinlock; |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 197 | struct rc_dev *dev; |
| 198 | struct led_classdev led; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 199 | |
| 200 | unsigned long wbase; /* Wake-Up Baseaddr */ |
| 201 | unsigned long ebase; /* Enhanced Func. Baseaddr */ |
| 202 | unsigned long sbase; /* Serial Port Baseaddr */ |
| 203 | unsigned int irq; /* Serial Port IRQ */ |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 204 | u8 irqmask; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 205 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 206 | /* RX state */ |
| 207 | enum wbcir_rxstate rxstate; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 208 | struct led_trigger *rxtrigger; |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 209 | struct ir_raw_event rxev; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 210 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 211 | /* TX state */ |
| 212 | enum wbcir_txstate txstate; |
| 213 | struct led_trigger *txtrigger; |
| 214 | u32 txlen; |
| 215 | u32 txoff; |
| 216 | u32 *txbuf; |
| 217 | wait_queue_head_t txwaitq; |
| 218 | u8 txmask; |
| 219 | u32 txcarrier; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 220 | }; |
| 221 | |
| 222 | static enum wbcir_protocol protocol = IR_PROTOCOL_RC6; |
| 223 | module_param(protocol, uint, 0444); |
| 224 | MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command " |
| 225 | "(0 = RC5, 1 = NEC, 2 = RC6A, default)"); |
| 226 | |
| 227 | static int invert; /* default = 0 */ |
| 228 | module_param(invert, bool, 0444); |
| 229 | MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver"); |
| 230 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 231 | static int txandrx; /* default = 0 */ |
| 232 | module_param(txandrx, bool, 0444); |
| 233 | MODULE_PARM_DESC(invert, "Allow simultaneous TX and RX"); |
| 234 | |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 235 | static unsigned int wake_sc = 0x800F040C; |
| 236 | module_param(wake_sc, uint, 0644); |
| 237 | MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command"); |
| 238 | |
| 239 | static unsigned int wake_rc6mode = 6; |
| 240 | module_param(wake_rc6mode, uint, 0644); |
| 241 | MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command " |
| 242 | "(0 = 0, 6 = 6A, default)"); |
| 243 | |
| 244 | |
| 245 | |
| 246 | /***************************************************************************** |
| 247 | * |
| 248 | * UTILITY FUNCTIONS |
| 249 | * |
| 250 | *****************************************************************************/ |
| 251 | |
| 252 | /* Caller needs to hold wbcir_lock */ |
| 253 | static void |
| 254 | wbcir_set_bits(unsigned long addr, u8 bits, u8 mask) |
| 255 | { |
| 256 | u8 val; |
| 257 | |
| 258 | val = inb(addr); |
| 259 | val = ((val & ~mask) | (bits & mask)); |
| 260 | outb(val, addr); |
| 261 | } |
| 262 | |
| 263 | /* Selects the register bank for the serial port */ |
| 264 | static inline void |
| 265 | wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank) |
| 266 | { |
| 267 | outb(bank, data->sbase + WBCIR_REG_SP3_BSR); |
| 268 | } |
| 269 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 270 | static inline void |
| 271 | wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) |
| 272 | { |
| 273 | if (data->irqmask == irqmask) |
| 274 | return; |
| 275 | |
| 276 | wbcir_select_bank(data, WBCIR_BANK_0); |
| 277 | outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); |
| 278 | data->irqmask = irqmask; |
| 279 | } |
| 280 | |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 281 | static enum led_brightness |
| 282 | wbcir_led_brightness_get(struct led_classdev *led_cdev) |
| 283 | { |
| 284 | struct wbcir_data *data = container_of(led_cdev, |
| 285 | struct wbcir_data, |
| 286 | led); |
| 287 | |
| 288 | if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE) |
| 289 | return LED_FULL; |
| 290 | else |
| 291 | return LED_OFF; |
| 292 | } |
| 293 | |
| 294 | static void |
| 295 | wbcir_led_brightness_set(struct led_classdev *led_cdev, |
| 296 | enum led_brightness brightness) |
| 297 | { |
| 298 | struct wbcir_data *data = container_of(led_cdev, |
| 299 | struct wbcir_data, |
| 300 | led); |
| 301 | |
| 302 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, |
| 303 | brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE, |
| 304 | WBCIR_LED_ENABLE); |
| 305 | } |
| 306 | |
| 307 | /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */ |
| 308 | static u8 |
| 309 | wbcir_to_rc6cells(u8 val) |
| 310 | { |
| 311 | u8 coded = 0x00; |
| 312 | int i; |
| 313 | |
| 314 | val &= 0x0F; |
| 315 | for (i = 0; i < 4; i++) { |
| 316 | if (val & 0x01) |
| 317 | coded |= 0x02 << (i * 2); |
| 318 | else |
| 319 | coded |= 0x01 << (i * 2); |
| 320 | val >>= 1; |
| 321 | } |
| 322 | |
| 323 | return coded; |
| 324 | } |
| 325 | |
| 326 | /***************************************************************************** |
| 327 | * |
| 328 | * INTERRUPT FUNCTIONS |
| 329 | * |
| 330 | *****************************************************************************/ |
| 331 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 332 | static void |
David Härdeman | 488ebc4 | 2011-04-28 12:13:27 -0300 | [diff] [blame] | 333 | wbcir_idle_rx(struct rc_dev *dev, bool idle) |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 334 | { |
David Härdeman | 488ebc4 | 2011-04-28 12:13:27 -0300 | [diff] [blame] | 335 | struct wbcir_data *data = dev->priv; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 336 | |
David Härdeman | 488ebc4 | 2011-04-28 12:13:27 -0300 | [diff] [blame] | 337 | if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) { |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 338 | data->rxstate = WBCIR_RXSTATE_ACTIVE; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 339 | led_trigger_event(data->rxtrigger, LED_FULL); |
| 340 | } |
| 341 | |
David Härdeman | 488ebc4 | 2011-04-28 12:13:27 -0300 | [diff] [blame] | 342 | if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) |
| 343 | /* Tell hardware to go idle by setting RXINACTIVE */ |
| 344 | outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR); |
| 345 | } |
| 346 | |
| 347 | static void |
| 348 | wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device) |
| 349 | { |
| 350 | u8 irdata; |
| 351 | DEFINE_IR_RAW_EVENT(rawir); |
| 352 | |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 353 | /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */ |
David Härdeman | 488ebc4 | 2011-04-28 12:13:27 -0300 | [diff] [blame] | 354 | while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) { |
| 355 | irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA); |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 356 | if (data->rxstate == WBCIR_RXSTATE_ERROR) |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 357 | continue; |
David Härdeman | 488ebc4 | 2011-04-28 12:13:27 -0300 | [diff] [blame] | 358 | rawir.pulse = irdata & 0x80 ? false : true; |
| 359 | rawir.duration = US_TO_NS((irdata & 0x7F) * 10); |
| 360 | ir_raw_event_store_with_filter(data->dev, &rawir); |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 361 | } |
| 362 | |
David Härdeman | 488ebc4 | 2011-04-28 12:13:27 -0300 | [diff] [blame] | 363 | /* Check if we should go idle */ |
| 364 | if (data->dev->idle) { |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 365 | led_trigger_event(data->rxtrigger, LED_OFF); |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 366 | data->rxstate = WBCIR_RXSTATE_INACTIVE; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 367 | } |
| 368 | |
| 369 | ir_raw_event_handle(data->dev); |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 370 | } |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 371 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 372 | static void |
| 373 | wbcir_irq_tx(struct wbcir_data *data) |
| 374 | { |
| 375 | unsigned int space; |
| 376 | unsigned int used; |
| 377 | u8 bytes[16]; |
| 378 | u8 byte; |
| 379 | |
| 380 | if (!data->txbuf) |
| 381 | return; |
| 382 | |
| 383 | switch (data->txstate) { |
| 384 | case WBCIR_TXSTATE_INACTIVE: |
| 385 | /* TX FIFO empty */ |
| 386 | space = 16; |
| 387 | led_trigger_event(data->txtrigger, LED_FULL); |
| 388 | break; |
| 389 | case WBCIR_TXSTATE_ACTIVE: |
| 390 | /* TX FIFO low (3 bytes or less) */ |
| 391 | space = 13; |
| 392 | break; |
| 393 | case WBCIR_TXSTATE_ERROR: |
| 394 | space = 0; |
| 395 | break; |
| 396 | default: |
| 397 | return; |
| 398 | } |
| 399 | |
| 400 | /* |
| 401 | * TX data is run-length coded in bytes: YXXXXXXX |
| 402 | * Y = space (1) or pulse (0) |
| 403 | * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us) |
| 404 | */ |
| 405 | for (used = 0; used < space && data->txoff != data->txlen; used++) { |
| 406 | if (data->txbuf[data->txoff] == 0) { |
| 407 | data->txoff++; |
| 408 | continue; |
| 409 | } |
| 410 | byte = min((u32)0x80, data->txbuf[data->txoff]); |
| 411 | data->txbuf[data->txoff] -= byte; |
| 412 | byte--; |
| 413 | byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */ |
| 414 | bytes[used] = byte; |
| 415 | } |
| 416 | |
| 417 | while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen) |
| 418 | data->txoff++; |
| 419 | |
| 420 | if (used == 0) { |
| 421 | /* Finished */ |
| 422 | if (data->txstate == WBCIR_TXSTATE_ERROR) |
| 423 | /* Clear TX underrun bit */ |
| 424 | outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR); |
| 425 | else |
| 426 | data->txstate = WBCIR_TXSTATE_DONE; |
| 427 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); |
| 428 | led_trigger_event(data->txtrigger, LED_OFF); |
| 429 | wake_up(&data->txwaitq); |
| 430 | } else if (data->txoff == data->txlen) { |
| 431 | /* At the end of transmission, tell the hw before last byte */ |
| 432 | outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1); |
| 433 | outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR); |
| 434 | outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA); |
| 435 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | |
| 436 | WBCIR_IRQ_TX_EMPTY); |
| 437 | } else { |
| 438 | /* More data to follow... */ |
| 439 | outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used); |
| 440 | if (data->txstate == WBCIR_TXSTATE_INACTIVE) { |
| 441 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | |
| 442 | WBCIR_IRQ_TX_LOW); |
| 443 | data->txstate = WBCIR_TXSTATE_ACTIVE; |
| 444 | } |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | static irqreturn_t |
| 449 | wbcir_irq_handler(int irqno, void *cookie) |
| 450 | { |
| 451 | struct pnp_dev *device = cookie; |
| 452 | struct wbcir_data *data = pnp_get_drvdata(device); |
| 453 | unsigned long flags; |
| 454 | u8 status; |
| 455 | |
| 456 | spin_lock_irqsave(&data->spinlock, flags); |
| 457 | wbcir_select_bank(data, WBCIR_BANK_0); |
| 458 | status = inb(data->sbase + WBCIR_REG_SP3_EIR); |
| 459 | status &= data->irqmask; |
| 460 | |
| 461 | if (!status) { |
| 462 | spin_unlock_irqrestore(&data->spinlock, flags); |
| 463 | return IRQ_NONE; |
| 464 | } |
| 465 | |
| 466 | if (status & WBCIR_IRQ_ERR) { |
| 467 | /* RX overflow? (read clears bit) */ |
| 468 | if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) { |
| 469 | data->rxstate = WBCIR_RXSTATE_ERROR; |
| 470 | ir_raw_event_reset(data->dev); |
| 471 | } |
| 472 | |
| 473 | /* TX underflow? */ |
| 474 | if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN) |
| 475 | data->txstate = WBCIR_TXSTATE_ERROR; |
| 476 | } |
| 477 | |
| 478 | if (status & WBCIR_IRQ_RX) |
| 479 | wbcir_irq_rx(data, device); |
| 480 | |
| 481 | if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY)) |
| 482 | wbcir_irq_tx(data); |
| 483 | |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 484 | spin_unlock_irqrestore(&data->spinlock, flags); |
| 485 | return IRQ_HANDLED; |
| 486 | } |
| 487 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 488 | /***************************************************************************** |
| 489 | * |
| 490 | * RC-CORE INTERFACE FUNCTIONS |
| 491 | * |
| 492 | *****************************************************************************/ |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 493 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 494 | static int |
| 495 | wbcir_txcarrier(struct rc_dev *dev, u32 carrier) |
| 496 | { |
| 497 | struct wbcir_data *data = dev->priv; |
| 498 | unsigned long flags; |
| 499 | u8 val; |
| 500 | u32 freq; |
| 501 | |
| 502 | freq = DIV_ROUND_CLOSEST(carrier, 1000); |
| 503 | if (freq < 30 || freq > 60) |
| 504 | return -EINVAL; |
| 505 | |
| 506 | switch (freq) { |
| 507 | case 58: |
| 508 | case 59: |
| 509 | case 60: |
| 510 | val = freq - 58; |
| 511 | freq *= 1000; |
| 512 | break; |
| 513 | case 57: |
| 514 | val = freq - 27; |
| 515 | freq = 56900; |
| 516 | break; |
| 517 | default: |
| 518 | val = freq - 27; |
| 519 | freq *= 1000; |
| 520 | break; |
| 521 | } |
| 522 | |
| 523 | spin_lock_irqsave(&data->spinlock, flags); |
| 524 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { |
| 525 | spin_unlock_irqrestore(&data->spinlock, flags); |
| 526 | return -EBUSY; |
| 527 | } |
| 528 | |
| 529 | if (data->txcarrier != freq) { |
| 530 | wbcir_select_bank(data, WBCIR_BANK_7); |
| 531 | wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F); |
| 532 | data->txcarrier = freq; |
| 533 | } |
| 534 | |
| 535 | spin_unlock_irqrestore(&data->spinlock, flags); |
| 536 | return 0; |
| 537 | } |
| 538 | |
| 539 | static int |
| 540 | wbcir_txmask(struct rc_dev *dev, u32 mask) |
| 541 | { |
| 542 | struct wbcir_data *data = dev->priv; |
| 543 | unsigned long flags; |
| 544 | u8 val; |
| 545 | |
| 546 | /* Four outputs, only one output can be enabled at a time */ |
| 547 | switch (mask) { |
| 548 | case 0x1: |
| 549 | val = 0x0; |
| 550 | break; |
| 551 | case 0x2: |
| 552 | val = 0x1; |
| 553 | break; |
| 554 | case 0x4: |
| 555 | val = 0x2; |
| 556 | break; |
| 557 | case 0x8: |
| 558 | val = 0x3; |
| 559 | break; |
| 560 | default: |
| 561 | return -EINVAL; |
| 562 | } |
| 563 | |
| 564 | spin_lock_irqsave(&data->spinlock, flags); |
| 565 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { |
| 566 | spin_unlock_irqrestore(&data->spinlock, flags); |
| 567 | return -EBUSY; |
| 568 | } |
| 569 | |
| 570 | if (data->txmask != mask) { |
| 571 | wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c); |
| 572 | data->txmask = mask; |
| 573 | } |
| 574 | |
| 575 | spin_unlock_irqrestore(&data->spinlock, flags); |
| 576 | return 0; |
| 577 | } |
| 578 | |
| 579 | static int |
| 580 | wbcir_tx(struct rc_dev *dev, int *buf, u32 bufsize) |
| 581 | { |
| 582 | struct wbcir_data *data = dev->priv; |
| 583 | u32 count; |
| 584 | unsigned i; |
| 585 | unsigned long flags; |
| 586 | |
| 587 | /* bufsize has been sanity checked by the caller */ |
| 588 | count = bufsize / sizeof(int); |
| 589 | |
| 590 | /* Not sure if this is possible, but better safe than sorry */ |
| 591 | spin_lock_irqsave(&data->spinlock, flags); |
| 592 | if (data->txstate != WBCIR_TXSTATE_INACTIVE) { |
| 593 | spin_unlock_irqrestore(&data->spinlock, flags); |
| 594 | return -EBUSY; |
| 595 | } |
| 596 | |
| 597 | /* Convert values to multiples of 10us */ |
| 598 | for (i = 0; i < count; i++) |
| 599 | buf[i] = DIV_ROUND_CLOSEST(buf[i], 10); |
| 600 | |
| 601 | /* Fill the TX fifo once, the irq handler will do the rest */ |
| 602 | data->txbuf = buf; |
| 603 | data->txlen = count; |
| 604 | data->txoff = 0; |
| 605 | wbcir_irq_tx(data); |
| 606 | |
| 607 | /* Wait for the TX to complete */ |
| 608 | while (data->txstate == WBCIR_TXSTATE_ACTIVE) { |
| 609 | spin_unlock_irqrestore(&data->spinlock, flags); |
| 610 | wait_event(data->txwaitq, data->txstate != WBCIR_TXSTATE_ACTIVE); |
| 611 | spin_lock_irqsave(&data->spinlock, flags); |
| 612 | } |
| 613 | |
| 614 | /* We're done */ |
| 615 | if (data->txstate == WBCIR_TXSTATE_ERROR) |
| 616 | count = -EAGAIN; |
| 617 | data->txstate = WBCIR_TXSTATE_INACTIVE; |
| 618 | data->txbuf = NULL; |
| 619 | spin_unlock_irqrestore(&data->spinlock, flags); |
| 620 | |
| 621 | return count; |
| 622 | } |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 623 | |
| 624 | /***************************************************************************** |
| 625 | * |
| 626 | * SETUP/INIT/SUSPEND/RESUME FUNCTIONS |
| 627 | * |
| 628 | *****************************************************************************/ |
| 629 | |
| 630 | static void |
| 631 | wbcir_shutdown(struct pnp_dev *device) |
| 632 | { |
| 633 | struct device *dev = &device->dev; |
| 634 | struct wbcir_data *data = pnp_get_drvdata(device); |
David Härdeman | 67cdd42 | 2011-04-28 12:13:17 -0300 | [diff] [blame] | 635 | bool do_wake = true; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 636 | u8 match[11]; |
| 637 | u8 mask[11]; |
| 638 | u8 rc6_csl = 0; |
| 639 | int i; |
| 640 | |
| 641 | memset(match, 0, sizeof(match)); |
| 642 | memset(mask, 0, sizeof(mask)); |
| 643 | |
| 644 | if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) { |
David Härdeman | 67cdd42 | 2011-04-28 12:13:17 -0300 | [diff] [blame] | 645 | do_wake = false; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 646 | goto finish; |
| 647 | } |
| 648 | |
| 649 | switch (protocol) { |
| 650 | case IR_PROTOCOL_RC5: |
| 651 | if (wake_sc > 0xFFF) { |
David Härdeman | 67cdd42 | 2011-04-28 12:13:17 -0300 | [diff] [blame] | 652 | do_wake = false; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 653 | dev_err(dev, "RC5 - Invalid wake scancode\n"); |
| 654 | break; |
| 655 | } |
| 656 | |
| 657 | /* Mask = 13 bits, ex toggle */ |
| 658 | mask[0] = 0xFF; |
| 659 | mask[1] = 0x17; |
| 660 | |
| 661 | match[0] = (wake_sc & 0x003F); /* 6 command bits */ |
| 662 | match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */ |
| 663 | match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */ |
| 664 | if (!(wake_sc & 0x0040)) /* 2nd start bit */ |
| 665 | match[1] |= 0x10; |
| 666 | |
| 667 | break; |
| 668 | |
| 669 | case IR_PROTOCOL_NEC: |
| 670 | if (wake_sc > 0xFFFFFF) { |
David Härdeman | 67cdd42 | 2011-04-28 12:13:17 -0300 | [diff] [blame] | 671 | do_wake = false; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 672 | dev_err(dev, "NEC - Invalid wake scancode\n"); |
| 673 | break; |
| 674 | } |
| 675 | |
| 676 | mask[0] = mask[1] = mask[2] = mask[3] = 0xFF; |
| 677 | |
| 678 | match[1] = bitrev8((wake_sc & 0xFF)); |
| 679 | match[0] = ~match[1]; |
| 680 | |
| 681 | match[3] = bitrev8((wake_sc & 0xFF00) >> 8); |
| 682 | if (wake_sc > 0xFFFF) |
| 683 | match[2] = bitrev8((wake_sc & 0xFF0000) >> 16); |
| 684 | else |
| 685 | match[2] = ~match[3]; |
| 686 | |
| 687 | break; |
| 688 | |
| 689 | case IR_PROTOCOL_RC6: |
| 690 | |
| 691 | if (wake_rc6mode == 0) { |
| 692 | if (wake_sc > 0xFFFF) { |
David Härdeman | 67cdd42 | 2011-04-28 12:13:17 -0300 | [diff] [blame] | 693 | do_wake = false; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 694 | dev_err(dev, "RC6 - Invalid wake scancode\n"); |
| 695 | break; |
| 696 | } |
| 697 | |
| 698 | /* Command */ |
| 699 | match[0] = wbcir_to_rc6cells(wake_sc >> 0); |
| 700 | mask[0] = 0xFF; |
| 701 | match[1] = wbcir_to_rc6cells(wake_sc >> 4); |
| 702 | mask[1] = 0xFF; |
| 703 | |
| 704 | /* Address */ |
| 705 | match[2] = wbcir_to_rc6cells(wake_sc >> 8); |
| 706 | mask[2] = 0xFF; |
| 707 | match[3] = wbcir_to_rc6cells(wake_sc >> 12); |
| 708 | mask[3] = 0xFF; |
| 709 | |
| 710 | /* Header */ |
| 711 | match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */ |
| 712 | mask[4] = 0xF0; |
| 713 | match[5] = 0x09; /* start bit = 1, mode2 = 0 */ |
| 714 | mask[5] = 0x0F; |
| 715 | |
| 716 | rc6_csl = 44; |
| 717 | |
| 718 | } else if (wake_rc6mode == 6) { |
| 719 | i = 0; |
| 720 | |
| 721 | /* Command */ |
| 722 | match[i] = wbcir_to_rc6cells(wake_sc >> 0); |
| 723 | mask[i++] = 0xFF; |
| 724 | match[i] = wbcir_to_rc6cells(wake_sc >> 4); |
| 725 | mask[i++] = 0xFF; |
| 726 | |
| 727 | /* Address + Toggle */ |
| 728 | match[i] = wbcir_to_rc6cells(wake_sc >> 8); |
| 729 | mask[i++] = 0xFF; |
| 730 | match[i] = wbcir_to_rc6cells(wake_sc >> 12); |
| 731 | mask[i++] = 0x3F; |
| 732 | |
| 733 | /* Customer bits 7 - 0 */ |
| 734 | match[i] = wbcir_to_rc6cells(wake_sc >> 16); |
| 735 | mask[i++] = 0xFF; |
| 736 | match[i] = wbcir_to_rc6cells(wake_sc >> 20); |
| 737 | mask[i++] = 0xFF; |
| 738 | |
| 739 | if (wake_sc & 0x80000000) { |
| 740 | /* Customer range bit and bits 15 - 8 */ |
| 741 | match[i] = wbcir_to_rc6cells(wake_sc >> 24); |
| 742 | mask[i++] = 0xFF; |
| 743 | match[i] = wbcir_to_rc6cells(wake_sc >> 28); |
| 744 | mask[i++] = 0xFF; |
| 745 | rc6_csl = 76; |
| 746 | } else if (wake_sc <= 0x007FFFFF) { |
| 747 | rc6_csl = 60; |
| 748 | } else { |
David Härdeman | 67cdd42 | 2011-04-28 12:13:17 -0300 | [diff] [blame] | 749 | do_wake = false; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 750 | dev_err(dev, "RC6 - Invalid wake scancode\n"); |
| 751 | break; |
| 752 | } |
| 753 | |
| 754 | /* Header */ |
| 755 | match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */ |
| 756 | mask[i++] = 0xFF; |
| 757 | match[i] = 0x0A; /* start bit = 1, mode2 = 1 */ |
| 758 | mask[i++] = 0x0F; |
| 759 | |
| 760 | } else { |
David Härdeman | 67cdd42 | 2011-04-28 12:13:17 -0300 | [diff] [blame] | 761 | do_wake = false; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 762 | dev_err(dev, "RC6 - Invalid wake mode\n"); |
| 763 | } |
| 764 | |
| 765 | break; |
| 766 | |
| 767 | default: |
David Härdeman | 67cdd42 | 2011-04-28 12:13:17 -0300 | [diff] [blame] | 768 | do_wake = false; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 769 | break; |
| 770 | } |
| 771 | |
| 772 | finish: |
| 773 | if (do_wake) { |
| 774 | /* Set compare and compare mask */ |
| 775 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, |
| 776 | WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0, |
| 777 | 0x3F); |
| 778 | outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11); |
| 779 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, |
| 780 | WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0, |
| 781 | 0x3F); |
| 782 | outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11); |
| 783 | |
| 784 | /* RC6 Compare String Len */ |
| 785 | outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL); |
| 786 | |
| 787 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ |
| 788 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); |
| 789 | |
| 790 | /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */ |
| 791 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07); |
| 792 | |
| 793 | /* Set CEIR_EN */ |
| 794 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01); |
| 795 | |
| 796 | } else { |
| 797 | /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ |
| 798 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); |
| 799 | |
| 800 | /* Clear CEIR_EN */ |
| 801 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); |
| 802 | } |
| 803 | |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 804 | /* |
| 805 | * ACPI will set the HW disable bit for SP3 which means that the |
| 806 | * output signals are left in an undefined state which may cause |
| 807 | * spurious interrupts which we need to ignore until the hardware |
| 808 | * is reinitialized. |
| 809 | */ |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 810 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 811 | disable_irq(data->irq); |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 812 | |
| 813 | /* Disable LED */ |
| 814 | led_trigger_event(data->rxtrigger, LED_OFF); |
| 815 | led_trigger_event(data->txtrigger, LED_OFF); |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 816 | } |
| 817 | |
| 818 | static int |
| 819 | wbcir_suspend(struct pnp_dev *device, pm_message_t state) |
| 820 | { |
| 821 | wbcir_shutdown(device); |
| 822 | return 0; |
| 823 | } |
| 824 | |
| 825 | static void |
| 826 | wbcir_init_hw(struct wbcir_data *data) |
| 827 | { |
| 828 | u8 tmp; |
| 829 | |
| 830 | /* Disable interrupts */ |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 831 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 832 | |
| 833 | /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */ |
| 834 | tmp = protocol << 4; |
| 835 | if (invert) |
| 836 | tmp |= 0x08; |
| 837 | outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL); |
| 838 | |
| 839 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ |
| 840 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); |
| 841 | |
| 842 | /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ |
| 843 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); |
| 844 | |
| 845 | /* Set RC5 cell time to correspond to 36 kHz */ |
| 846 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F); |
| 847 | |
| 848 | /* Set IRTX_INV */ |
| 849 | if (invert) |
| 850 | outb(0x04, data->ebase + WBCIR_REG_ECEIR_CCTL); |
| 851 | else |
| 852 | outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL); |
| 853 | |
| 854 | /* |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 855 | * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1, |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 856 | * set SP3_IRRX_SW to binary 01, helpfully not documented |
| 857 | */ |
| 858 | outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS); |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 859 | data->txmask = 0x1; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 860 | |
| 861 | /* Enable extended mode */ |
| 862 | wbcir_select_bank(data, WBCIR_BANK_2); |
| 863 | outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1); |
| 864 | |
| 865 | /* |
| 866 | * Configure baud generator, IR data will be sampled at |
| 867 | * a bitrate of: (24Mhz * prescaler) / (divisor * 16). |
| 868 | * |
| 869 | * The ECIR registers include a flag to change the |
| 870 | * 24Mhz clock freq to 48Mhz. |
| 871 | * |
| 872 | * It's not documented in the specs, but fifo levels |
| 873 | * other than 16 seems to be unsupported. |
| 874 | */ |
| 875 | |
| 876 | /* prescaler 1.0, tx/rx fifo lvl 16 */ |
| 877 | outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2); |
| 878 | |
| 879 | /* Set baud divisor to generate one byte per bit/cell */ |
| 880 | switch (protocol) { |
| 881 | case IR_PROTOCOL_RC5: |
| 882 | outb(0xA7, data->sbase + WBCIR_REG_SP3_BGDL); |
| 883 | break; |
| 884 | case IR_PROTOCOL_RC6: |
| 885 | outb(0x53, data->sbase + WBCIR_REG_SP3_BGDL); |
| 886 | break; |
| 887 | case IR_PROTOCOL_NEC: |
| 888 | outb(0x69, data->sbase + WBCIR_REG_SP3_BGDL); |
| 889 | break; |
| 890 | } |
| 891 | outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); |
| 892 | |
| 893 | /* Set CEIR mode */ |
| 894 | wbcir_select_bank(data, WBCIR_BANK_0); |
| 895 | outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR); |
| 896 | inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */ |
| 897 | inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */ |
| 898 | |
| 899 | /* Disable RX demod, run-length encoding/decoding, set freq span */ |
| 900 | wbcir_select_bank(data, WBCIR_BANK_7); |
| 901 | outb(0x10, data->sbase + WBCIR_REG_SP3_RCCFG); |
| 902 | |
| 903 | /* Disable timer */ |
| 904 | wbcir_select_bank(data, WBCIR_BANK_4); |
| 905 | outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1); |
| 906 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 907 | /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */ |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 908 | wbcir_select_bank(data, WBCIR_BANK_5); |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 909 | outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2); |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 910 | |
| 911 | /* Disable CRC */ |
| 912 | wbcir_select_bank(data, WBCIR_BANK_6); |
| 913 | outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3); |
| 914 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 915 | /* Set RX demodulation freq, not really used */ |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 916 | wbcir_select_bank(data, WBCIR_BANK_7); |
| 917 | outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC); |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 918 | |
| 919 | /* Set TX modulation, 36kHz, 7us pulse width */ |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 920 | outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC); |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 921 | data->txcarrier = 36000; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 922 | |
| 923 | /* Set invert and pin direction */ |
| 924 | if (invert) |
| 925 | outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4); |
| 926 | else |
| 927 | outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4); |
| 928 | |
| 929 | /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */ |
| 930 | wbcir_select_bank(data, WBCIR_BANK_0); |
| 931 | outb(0x97, data->sbase + WBCIR_REG_SP3_FCR); |
| 932 | |
| 933 | /* Clear AUX status bits */ |
| 934 | outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR); |
| 935 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 936 | /* Clear RX state */ |
| 937 | data->rxstate = WBCIR_RXSTATE_INACTIVE; |
| 938 | data->rxev.duration = 0; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 939 | ir_raw_event_reset(data->dev); |
| 940 | ir_raw_event_handle(data->dev); |
| 941 | |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 942 | /* |
| 943 | * Check TX state, if we did a suspend/resume cycle while TX was |
| 944 | * active, we will have a process waiting in txwaitq. |
| 945 | */ |
| 946 | if (data->txstate == WBCIR_TXSTATE_ACTIVE) { |
| 947 | data->txstate = WBCIR_TXSTATE_ERROR; |
| 948 | wake_up(&data->txwaitq); |
| 949 | } |
| 950 | |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 951 | /* Enable interrupts */ |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 952 | wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 953 | } |
| 954 | |
| 955 | static int |
| 956 | wbcir_resume(struct pnp_dev *device) |
| 957 | { |
| 958 | struct wbcir_data *data = pnp_get_drvdata(device); |
| 959 | |
| 960 | wbcir_init_hw(data); |
| 961 | enable_irq(data->irq); |
| 962 | |
| 963 | return 0; |
| 964 | } |
| 965 | |
| 966 | static int __devinit |
| 967 | wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) |
| 968 | { |
| 969 | struct device *dev = &device->dev; |
| 970 | struct wbcir_data *data; |
| 971 | int err; |
| 972 | |
| 973 | if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN && |
| 974 | pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN && |
| 975 | pnp_port_len(device, 2) == SP_IOMEM_LEN)) { |
| 976 | dev_err(dev, "Invalid resources\n"); |
| 977 | return -ENODEV; |
| 978 | } |
| 979 | |
| 980 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
| 981 | if (!data) { |
| 982 | err = -ENOMEM; |
| 983 | goto exit; |
| 984 | } |
| 985 | |
| 986 | pnp_set_drvdata(device, data); |
| 987 | |
| 988 | spin_lock_init(&data->spinlock); |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 989 | init_waitqueue_head(&data->txwaitq); |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 990 | data->ebase = pnp_port_start(device, 0); |
| 991 | data->wbase = pnp_port_start(device, 1); |
| 992 | data->sbase = pnp_port_start(device, 2); |
| 993 | data->irq = pnp_irq(device, 0); |
| 994 | |
| 995 | if (data->wbase == 0 || data->ebase == 0 || |
| 996 | data->sbase == 0 || data->irq == 0) { |
| 997 | err = -ENODEV; |
| 998 | dev_err(dev, "Invalid resources\n"); |
| 999 | goto exit_free_data; |
| 1000 | } |
| 1001 | |
| 1002 | dev_dbg(&device->dev, "Found device " |
| 1003 | "(w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n", |
| 1004 | data->wbase, data->ebase, data->sbase, data->irq); |
| 1005 | |
| 1006 | if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) { |
| 1007 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", |
| 1008 | data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1); |
| 1009 | err = -EBUSY; |
| 1010 | goto exit_free_data; |
| 1011 | } |
| 1012 | |
| 1013 | if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) { |
| 1014 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", |
| 1015 | data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1); |
| 1016 | err = -EBUSY; |
| 1017 | goto exit_release_wbase; |
| 1018 | } |
| 1019 | |
| 1020 | if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) { |
| 1021 | dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", |
| 1022 | data->sbase, data->sbase + SP_IOMEM_LEN - 1); |
| 1023 | err = -EBUSY; |
| 1024 | goto exit_release_ebase; |
| 1025 | } |
| 1026 | |
| 1027 | err = request_irq(data->irq, wbcir_irq_handler, |
| 1028 | IRQF_DISABLED, DRVNAME, device); |
| 1029 | if (err) { |
| 1030 | dev_err(dev, "Failed to claim IRQ %u\n", data->irq); |
| 1031 | err = -EBUSY; |
| 1032 | goto exit_release_sbase; |
| 1033 | } |
| 1034 | |
| 1035 | led_trigger_register_simple("cir-tx", &data->txtrigger); |
| 1036 | if (!data->txtrigger) { |
| 1037 | err = -ENOMEM; |
| 1038 | goto exit_free_irq; |
| 1039 | } |
| 1040 | |
| 1041 | led_trigger_register_simple("cir-rx", &data->rxtrigger); |
| 1042 | if (!data->rxtrigger) { |
| 1043 | err = -ENOMEM; |
| 1044 | goto exit_unregister_txtrigger; |
| 1045 | } |
| 1046 | |
| 1047 | data->led.name = "cir::activity"; |
| 1048 | data->led.default_trigger = "cir-rx"; |
| 1049 | data->led.brightness_set = wbcir_led_brightness_set; |
| 1050 | data->led.brightness_get = wbcir_led_brightness_get; |
| 1051 | err = led_classdev_register(&device->dev, &data->led); |
| 1052 | if (err) |
| 1053 | goto exit_unregister_rxtrigger; |
| 1054 | |
| 1055 | data->dev = rc_allocate_device(); |
| 1056 | if (!data->dev) { |
| 1057 | err = -ENOMEM; |
| 1058 | goto exit_unregister_led; |
| 1059 | } |
| 1060 | |
| 1061 | data->dev->driver_name = WBCIR_NAME; |
| 1062 | data->dev->input_name = WBCIR_NAME; |
| 1063 | data->dev->input_phys = "wbcir/cir0"; |
| 1064 | data->dev->input_id.bustype = BUS_HOST; |
| 1065 | data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND; |
| 1066 | data->dev->input_id.product = WBCIR_ID_FAMILY; |
| 1067 | data->dev->input_id.version = WBCIR_ID_CHIP; |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 1068 | data->dev->map_name = RC_MAP_RC6_MCE; |
David Härdeman | 488ebc4 | 2011-04-28 12:13:27 -0300 | [diff] [blame] | 1069 | data->dev->s_idle = wbcir_idle_rx; |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 1070 | data->dev->s_tx_mask = wbcir_txmask; |
| 1071 | data->dev->s_tx_carrier = wbcir_txcarrier; |
| 1072 | data->dev->tx_ir = wbcir_tx; |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 1073 | data->dev->priv = data; |
| 1074 | data->dev->dev.parent = &device->dev; |
| 1075 | |
| 1076 | err = rc_register_device(data->dev); |
| 1077 | if (err) |
| 1078 | goto exit_free_rc; |
| 1079 | |
| 1080 | device_init_wakeup(&device->dev, 1); |
| 1081 | |
| 1082 | wbcir_init_hw(data); |
| 1083 | |
| 1084 | return 0; |
| 1085 | |
| 1086 | exit_free_rc: |
| 1087 | rc_free_device(data->dev); |
| 1088 | exit_unregister_led: |
| 1089 | led_classdev_unregister(&data->led); |
| 1090 | exit_unregister_rxtrigger: |
| 1091 | led_trigger_unregister_simple(data->rxtrigger); |
| 1092 | exit_unregister_txtrigger: |
| 1093 | led_trigger_unregister_simple(data->txtrigger); |
| 1094 | exit_free_irq: |
| 1095 | free_irq(data->irq, device); |
| 1096 | exit_release_sbase: |
| 1097 | release_region(data->sbase, SP_IOMEM_LEN); |
| 1098 | exit_release_ebase: |
| 1099 | release_region(data->ebase, EHFUNC_IOMEM_LEN); |
| 1100 | exit_release_wbase: |
| 1101 | release_region(data->wbase, WAKEUP_IOMEM_LEN); |
| 1102 | exit_free_data: |
| 1103 | kfree(data); |
| 1104 | pnp_set_drvdata(device, NULL); |
| 1105 | exit: |
| 1106 | return err; |
| 1107 | } |
| 1108 | |
| 1109 | static void __devexit |
| 1110 | wbcir_remove(struct pnp_dev *device) |
| 1111 | { |
| 1112 | struct wbcir_data *data = pnp_get_drvdata(device); |
| 1113 | |
| 1114 | /* Disable interrupts */ |
David Härdeman | c829f26 | 2011-04-28 12:13:22 -0300 | [diff] [blame] | 1115 | wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
David Härdeman | 5b2e303 | 2010-10-29 16:08:28 -0300 | [diff] [blame] | 1116 | free_irq(data->irq, device); |
| 1117 | |
| 1118 | /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ |
| 1119 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); |
| 1120 | |
| 1121 | /* Clear CEIR_EN */ |
| 1122 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); |
| 1123 | |
| 1124 | /* Clear BUFF_EN, END_EN, MATCH_EN */ |
| 1125 | wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); |
| 1126 | |
| 1127 | rc_unregister_device(data->dev); |
| 1128 | |
| 1129 | led_trigger_unregister_simple(data->rxtrigger); |
| 1130 | led_trigger_unregister_simple(data->txtrigger); |
| 1131 | led_classdev_unregister(&data->led); |
| 1132 | |
| 1133 | /* This is ok since &data->led isn't actually used */ |
| 1134 | wbcir_led_brightness_set(&data->led, LED_OFF); |
| 1135 | |
| 1136 | release_region(data->wbase, WAKEUP_IOMEM_LEN); |
| 1137 | release_region(data->ebase, EHFUNC_IOMEM_LEN); |
| 1138 | release_region(data->sbase, SP_IOMEM_LEN); |
| 1139 | |
| 1140 | kfree(data); |
| 1141 | |
| 1142 | pnp_set_drvdata(device, NULL); |
| 1143 | } |
| 1144 | |
| 1145 | static const struct pnp_device_id wbcir_ids[] = { |
| 1146 | { "WEC1022", 0 }, |
| 1147 | { "", 0 } |
| 1148 | }; |
| 1149 | MODULE_DEVICE_TABLE(pnp, wbcir_ids); |
| 1150 | |
| 1151 | static struct pnp_driver wbcir_driver = { |
| 1152 | .name = WBCIR_NAME, |
| 1153 | .id_table = wbcir_ids, |
| 1154 | .probe = wbcir_probe, |
| 1155 | .remove = __devexit_p(wbcir_remove), |
| 1156 | .suspend = wbcir_suspend, |
| 1157 | .resume = wbcir_resume, |
| 1158 | .shutdown = wbcir_shutdown |
| 1159 | }; |
| 1160 | |
| 1161 | static int __init |
| 1162 | wbcir_init(void) |
| 1163 | { |
| 1164 | int ret; |
| 1165 | |
| 1166 | switch (protocol) { |
| 1167 | case IR_PROTOCOL_RC5: |
| 1168 | case IR_PROTOCOL_NEC: |
| 1169 | case IR_PROTOCOL_RC6: |
| 1170 | break; |
| 1171 | default: |
| 1172 | printk(KERN_ERR DRVNAME ": Invalid power-on protocol\n"); |
| 1173 | } |
| 1174 | |
| 1175 | ret = pnp_register_driver(&wbcir_driver); |
| 1176 | if (ret) |
| 1177 | printk(KERN_ERR DRVNAME ": Unable to register driver\n"); |
| 1178 | |
| 1179 | return ret; |
| 1180 | } |
| 1181 | |
| 1182 | static void __exit |
| 1183 | wbcir_exit(void) |
| 1184 | { |
| 1185 | pnp_unregister_driver(&wbcir_driver); |
| 1186 | } |
| 1187 | |
| 1188 | module_init(wbcir_init); |
| 1189 | module_exit(wbcir_exit); |
| 1190 | |
| 1191 | MODULE_AUTHOR("David Härdeman <david@hardeman.nu>"); |
| 1192 | MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver"); |
| 1193 | MODULE_LICENSE("GPL"); |