David Brownell | b587b13 | 2007-02-12 00:52:48 -0800 | [diff] [blame] | 1 | #ifndef __LINUX_SPI_EEPROM_H |
| 2 | #define __LINUX_SPI_EEPROM_H |
| 3 | |
David Brownell | 14dd1ff | 2009-04-02 16:56:58 -0700 | [diff] [blame] | 4 | #include <linux/memory.h> |
| 5 | |
David Brownell | b587b13 | 2007-02-12 00:52:48 -0800 | [diff] [blame] | 6 | /* |
| 7 | * Put one of these structures in platform_data for SPI EEPROMS handled |
| 8 | * by the "at25" driver. On SPI, most EEPROMS understand the same core |
| 9 | * command set. If you need to support EEPROMs that don't yet fit, add |
| 10 | * flags to support those protocol options. These values all come from |
| 11 | * the chip datasheets. |
| 12 | */ |
| 13 | struct spi_eeprom { |
| 14 | u32 byte_len; |
| 15 | char name[10]; |
| 16 | u16 page_size; /* for writes */ |
| 17 | u16 flags; |
| 18 | #define EE_ADDR1 0x0001 /* 8 bit addrs */ |
| 19 | #define EE_ADDR2 0x0002 /* 16 bit addrs */ |
| 20 | #define EE_ADDR3 0x0004 /* 24 bit addrs */ |
| 21 | #define EE_READONLY 0x0008 /* disallow writes */ |
David Brownell | 14dd1ff | 2009-04-02 16:56:58 -0700 | [diff] [blame] | 22 | |
Ivo Sieben | b4161f0 | 2012-04-18 08:29:34 +0200 | [diff] [blame] | 23 | /* |
| 24 | * Certain EEPROMS have a size that is larger than the number of address |
| 25 | * bytes would allow (e.g. like M95040 from ST that has 512 Byte size |
| 26 | * but uses only one address byte (A0 to A7) for addressing.) For |
| 27 | * the extra address bit (A8, A16 or A24) bit 3 of the instruction byte |
| 28 | * is used. This instruction bit is normally defined as don't care for |
| 29 | * other AT25 like chips. |
| 30 | */ |
| 31 | #define EE_INSTR_BIT3_IS_ADDR 0x0010 |
| 32 | |
David Brownell | 14dd1ff | 2009-04-02 16:56:58 -0700 | [diff] [blame] | 33 | void *context; |
David Brownell | b587b13 | 2007-02-12 00:52:48 -0800 | [diff] [blame] | 34 | }; |
| 35 | |
| 36 | #endif /* __LINUX_SPI_EEPROM_H */ |