Paul Mundt | bbfbd8b | 2008-10-01 16:13:54 +0900 | [diff] [blame] | 1 | #ifndef __SH_INTC_H |
| 2 | #define __SH_INTC_H |
| 3 | |
| 4 | typedef unsigned char intc_enum; |
| 5 | |
| 6 | struct intc_vect { |
| 7 | intc_enum enum_id; |
| 8 | unsigned short vect; |
| 9 | }; |
| 10 | |
| 11 | #define INTC_VECT(enum_id, vect) { enum_id, vect } |
| 12 | #define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq)) |
| 13 | |
| 14 | struct intc_group { |
| 15 | intc_enum enum_id; |
| 16 | intc_enum enum_ids[32]; |
| 17 | }; |
| 18 | |
| 19 | #define INTC_GROUP(enum_id, ids...) { enum_id, { ids } } |
| 20 | |
| 21 | struct intc_mask_reg { |
| 22 | unsigned long set_reg, clr_reg, reg_width; |
| 23 | intc_enum enum_ids[32]; |
| 24 | #ifdef CONFIG_SMP |
| 25 | unsigned long smp; |
| 26 | #endif |
| 27 | }; |
| 28 | |
| 29 | struct intc_prio_reg { |
| 30 | unsigned long set_reg, clr_reg, reg_width, field_width; |
| 31 | intc_enum enum_ids[16]; |
| 32 | #ifdef CONFIG_SMP |
| 33 | unsigned long smp; |
| 34 | #endif |
| 35 | }; |
| 36 | |
| 37 | struct intc_sense_reg { |
| 38 | unsigned long reg, reg_width, field_width; |
| 39 | intc_enum enum_ids[16]; |
| 40 | }; |
| 41 | |
| 42 | #ifdef CONFIG_SMP |
| 43 | #define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8) |
| 44 | #else |
| 45 | #define INTC_SMP(stride, nr) |
| 46 | #endif |
| 47 | |
| 48 | struct intc_desc { |
| 49 | struct intc_vect *vectors; |
| 50 | unsigned int nr_vectors; |
| 51 | struct intc_group *groups; |
| 52 | unsigned int nr_groups; |
| 53 | struct intc_mask_reg *mask_regs; |
| 54 | unsigned int nr_mask_regs; |
| 55 | struct intc_prio_reg *prio_regs; |
| 56 | unsigned int nr_prio_regs; |
| 57 | struct intc_sense_reg *sense_regs; |
| 58 | unsigned int nr_sense_regs; |
| 59 | char *name; |
| 60 | #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) |
| 61 | struct intc_mask_reg *ack_regs; |
| 62 | unsigned int nr_ack_regs; |
| 63 | #endif |
| 64 | }; |
| 65 | |
| 66 | #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) |
| 67 | #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ |
| 68 | mask_regs, prio_regs, sense_regs) \ |
| 69 | struct intc_desc symbol __initdata = { \ |
| 70 | _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ |
| 71 | _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ |
| 72 | _INTC_ARRAY(sense_regs), \ |
| 73 | chipname, \ |
| 74 | } |
| 75 | |
| 76 | #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A) |
| 77 | #define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \ |
| 78 | mask_regs, prio_regs, sense_regs, ack_regs) \ |
| 79 | struct intc_desc symbol __initdata = { \ |
| 80 | _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ |
| 81 | _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ |
| 82 | _INTC_ARRAY(sense_regs), \ |
| 83 | chipname, \ |
| 84 | _INTC_ARRAY(ack_regs), \ |
| 85 | } |
| 86 | #endif |
| 87 | |
| 88 | void __init register_intc_controller(struct intc_desc *desc); |
| 89 | int intc_set_priority(unsigned int irq, unsigned int prio); |
| 90 | |
| 91 | #endif /* __SH_INTC_H */ |